VLD terminal capable of reducing surface electric field

Abstract

The VLD terminal is easy to implement, wide in voltage application range and capable of reducing the surface electric field, wavy uneven impurity distribution of the VLD terminal is improved through two times of ion implantation, impurity distribution is made to be closer to smooth gradient distribution, and the performance of the VLD terminal is improved. Therefore, the reliability problem of over-high surface electric field peak value caused by non-uniform impurity distribution of the terminal is improved, the voltage withstanding performance of the terminal is improved, and the terminal has good practical value.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices and relates to a VLD terminal for reducing surface electric field. Background Art

[0002] Power semiconductor devices are mainly composed of two parts: the cell region and the terminal region. The design of the terminal structure is crucial to the breakdown voltage characteristics of power devices. Field plate + field limiting ring is the most commonly used terminal structure, but with the increase of device withstand voltage, when the number of field limiting rings increases to a certain extent, the effect of improving the breakdown voltage is no longer obvious, and a large amount of chip area is wasted, increasing production costs. The Variable Lateral Doping (VLD) terminal structure proposed by the literature Stengl R, Gosele U. Variation of lateral doping-A new concept to avoid high voltage breakdown of planar junctions, Proceedings of International Electron Devices Meeting, 1985, etc., greatly reduces the terminal length and chip area, improves the withstand voltage efficiency, reduces the production cost, and is gradually widely used in devices such as power MOSFET. The lateral variable doping (VLD) terminal is one of the most common terminal design methods in medium and high voltage power devices. By injecting a region with a gradient impurity concentration at the edge of the device, it can effectively expand the depletion region, alleviate the electric field concentration, and make the device show better blocking performance. VLD termination is a method of forming a lateral variable doping structure by setting appropriate mask window shapes and window parameter values, and performing ion implantation near the heavily doped main junction. The closer to the main junction, the greater the amount of implantation, and the farther away, the smaller the amount of implantation. The implanted impurities are connected through lateral diffusion of impurities. Compared with field limiting ring and field plate terminations, VLD has a smaller termination area; compared with JTE terminations, VLD has better blocking performance and is less sensitive to terminal impurity implantation dose deviation. The industry and academia have been committed to improving VLD terminations to achieve better blocking performance and reliability.

[0003] Although the traditional VLD terminal is simple in design, in the process of ion implantation to form the VLD terminal, the impurity concentration gradient distribution is achieved by controlling the size of the mask shielding area and the window area. If the mask layout, high temperature annealing process, implantation dose, etc. are not properly set, the impurity concentration distribution formed after high temperature annealing will be wavy, deviating from the smooth gradient impurity distribution, such as Figure 1This wavy distribution will produce an excessively high electric field peak at the low impurity concentration position J, reducing the performance of the VLD terminal and affecting the voltage withstand capability and reliability of the device. Summary of the invention

[0004] The present invention provides a VLD terminal for reducing the surface electric field. The method is easy to implement and has a wide voltage application range. The wavy impurity distribution of the VLD terminal is improved by two ion implantations, so that the impurity distribution is closer to a smooth gradual impurity distribution, thereby improving the reliability problem of the VLD terminal having an excessively high surface electric field peak value caused by uneven impurity distribution and improving the withstand voltage performance of the VLD terminal, and having good practical value.

[0005] like Figure 2 The figure shows the overall structure of the power device layout. Figure 3 is a lateral variable doping terminal. Figure 2 The area indicated by the black dotted line ABCD has a structure like Figure 3 As shown, it includes: a drain electrode metal 1, a heavily doped first conductive type semiconductor substrate 2 located on the drain electrode metal, a lightly doped first conductive type semiconductor drift region 3 located on the heavily doped first conductive type semiconductor substrate 2, a second conductive type semiconductor main junction 4, a second conductive type semiconductor variable doping region 5 and a heavily doped second conductive type semiconductor cut-off ring 6 located on the upper surface of the first conductive type semiconductor drift region 3, a source electrode metal 7 located on the second conductive type semiconductor main junction 4, and an oxide layer 8 located on the second conductive type semiconductor variable doping region 5 and the second conductive type semiconductor cut-off ring 6. Definition: The direction from the oxide layer 8 vertically pointing to the lightly doped first conductive type semiconductor drift region 3 is the y-axis direction, and the parallel direction from the oxide layer 8 to the junction of the second conductive type semiconductor variable doping region 5 is the x-axis direction;

[0006] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0007] A VLD terminal that reduces the surface electric field improves the wavy impurity distribution of the VLD terminal through two ion implantations, making the impurity distribution closer to a smooth gradient impurity distribution, thereby improving the reliability problem of the VLD terminal with excessively high surface electric field peak value caused by uneven impurity distribution and improving the withstand voltage performance of the VLD terminal. The process flow for its implementation is as follows: Figure 4 shown.

[0008] (1) By setting a mask, etching the oxide layer 8 to open a window, and performing the first ion implantation;

[0009] (2) high temperature annealing to form a second conductivity type semiconductor doped region 5;

[0010] (3) Setting a mask, etching the oxide layer 8 to open a window, and performing a second ion implantation;

[0011] (4) high temperature annealing to obtain a smoother and more gradual second conductivity type semiconductor doping region 5.

[0012] As a preferred embodiment, step (1) is further:

[0013] Figure 5 Schematic diagram of the first ion implantation mask setting for the VLD terminal. The VLD terminal BC is divided into N segments, each with a length of L. VLD / N, where the length of the VLD terminal is L VLD The window width of the nth mask is a n , impurity injection is achieved in this area. The width of the shielding area is b n , both satisfy a n +b n =L VLD / N. The first ion implantation dose is dose1.

[0014] As a preferred embodiment, step (2) is further:

[0015] High temperature annealing, through the diffusion of impurities, makes the injected impurities connected into one piece, forming the second conductivity type semiconductor doping region 5. High temperature refers to more than 1100°C. n-1 and a n The impurity distribution of the two implants satisfies the Gaussian distribution function after high temperature annealing. n The impurity distribution under the window area a is approximately satisfied n-1 with a n The superposition of the implanted impurities, such as Figure 6 As shown, the mask shielding area b n The impurity distribution function C under (x) satisfy

[0016]

[0017] The first ion implantation dose is dose1, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as annealing temperature, and t represents the high-temperature annealing time. According to the impurity distribution function C (x) , obviously in the mask shielding area b n Next x J At position, there is a point J with the lowest impurity concentration.

[0018] As a preferred embodiment, step (3) is further:

[0019] The mask for the second ion implantation is as follows: Figure 7 As shown. Divide the VLD terminal BC into N segments, each segment is L in length VLD / N, where the length of the VLD terminal is L VLD The window width of the nth mask is c n , impurity injection is achieved in this area. The width of the shielding area is d n , both satisfy c n +d n =L VLD / N. The window width of the nth mask is c n Located in the first ion implantation mask shielding area b n Inside, that is, in the first ion implantation shielding area b n Ion implantation is performed on some areas inside.

[0020] Figure 1 The lowest impurity concentration point J is located at b n Below, to ensure that the second ion implantation can make up for the impurity concentration at the lowest impurity concentration point J, the wavy impurity distribution is improved to make the impurity distribution smoother and more gradual.

[0021] For x n The impurity distribution of the position approximately satisfies

[0022]

[0023] For x n-1 The impurity distribution of the position approximately satisfies

[0024]

[0025] If the shielding area b n The x-axis coordinate of the center position is According to C (x) Expression, x J satisfy

[0026]

[0027] Second ion implantation mask window area c n The range is x J The scope of location.

[0028] The second ion implantation dose is dose2, which should be less than the first ion implantation dose dose1, and the two meet

[0029] 0<dose2≤0.25dose1

[0030] As a preferred embodiment, step (4) is further:

[0031] High temperature annealing, through the diffusion of impurities, makes the injected impurities connected into one piece, forming a second conductivity type semiconductor variable doping region 5 with a smoother gradual impurity distribution, Figure 1 The depression at the position J of medium and low impurity concentration is supplemented, and the surface electric field is reduced. High temperature refers to more than 1100℃.

[0032] At this time x J Position impurity distribution satisfy

[0033]

[0034] The second ion implantation dose is dose2, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as the annealing temperature, t represents the high-temperature annealing time of the first ion implantation, and t′ represents the high-temperature annealing time of the second ion implantation.

[0035] At this time there is

[0036]

[0037] Thus, the impurity concentration at the lowest impurity concentration point J is increased, and the wavy impurity distribution is improved, making the impurity distribution smoother and more gradual. At this time, the surface electric field can be reduced, and the peak surface electric field at point J is reduced from E max1 Reduce to E max2 ,like Figure 1 shown.

[0038] As a preferred embodiment, the implementation process is used for the lateral variable doping terminal design of diodes, BJTs, MOSFETs, JFETs, and IGBT power semiconductor devices.

[0039] As a preferred embodiment, the power semiconductor device with the terminal is made of semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium phosphide, and gallium nitride.

[0040] The principle of the present invention is:

[0041] The present invention is based on the mask setting method of the traditional VLD terminal. On the basis of the first ion implantation, a second ion implantation is arranged to obtain a smoother gradual impurity distribution, thereby improving the reliability problem of the VLD terminal having an excessively high surface electric field peak value caused by uneven impurity distribution and improving the withstand voltage performance of the VLD terminal.

[0042] The beneficial effects of the present invention are:

[0043] It is highly feasible and can effectively improve the reliability problem of excessively high surface electric field peaks caused by uneven impurity distribution and low impurity concentration in some areas of the VLD terminal, thereby improving the withstand voltage performance of the VLD terminal. Figure 1 As shown in the figure, the second ion implantation effectively improves the problem of the wavy overall impurity distribution after the first implantation of the traditional VLD terminal, making the VLD impurity distribution smoother and the surface electric field from E max1 Reduce to E max2 . BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of a VLD termination principle for reducing the surface electric field.

[0045] Point J is the point with the lowest impurity concentration at the VLD terminal, and E max1 is the peak value of the surface electric field corresponding to point J of the actual wavy impurity distribution, E max2 is the peak value of the surface electric field corresponding to the J point of the smooth and gradual impurity distribution. n-1 with a n is the window area of ​​the first ion implantation mask, used for ion implantation, b n This is the shielding area of ​​the mask for the first ion implantation.

[0046] Figure 2 This is an overall structural diagram of a power device layout involved in the present invention.

[0047] AB represents the second conductivity type semiconductor main junction 4, BC represents the second conductivity type semiconductor variable doping region 5, and D represents the outermost edge of the layout.

[0048] Figure 3 The schematic cross-sectional view of the VLD terminal involved in the present invention is shown in FIG. Figure 2 ABCD corresponds in.

[0049] It includes a drain electrode metal 1, a heavily doped first conductive type semiconductor substrate 2 located on the drain electrode metal, a lightly doped first conductive type semiconductor drift region 3 located on the heavily doped first conductive type semiconductor substrate 2, a second conductive type semiconductor main junction 4, a second conductive type semiconductor variable doping region 5 and a heavily doped second conductive type semiconductor cut-off ring 6 located on the upper surface of the first conductive type semiconductor drift region 3, a source electrode metal 7 located on the second conductive type semiconductor main junction 4, and an oxide layer 8 located on the second conductive type semiconductor variable doping region 5 and the second conductive type semiconductor cut-off ring 6. Definition: The direction from the oxide layer 8 vertically pointing to the lightly doped first conductive type semiconductor drift region 3 is the y-axis direction, and the parallel direction from the oxide layer 8 to the junction of the second conductive type semiconductor variable doping region 5 is the x-axis direction.

[0050] Figure 4 The present invention is a schematic diagram of a process flow for realizing a VLD terminal for reducing the surface electric field.

[0051] Figure 5 It is a schematic diagram of the first ion implantation mask of the VLD terminal involved in the present invention.

[0052] Figure 6 The VLD terminal mask shielding area b of the present invention n Below the window area a n-1 with a n The impurity distribution formed by the high-temperature annealing of the injected impurities.

[0053] Figure 7 It is a schematic diagram of the second ion implantation mask of the VLD terminal involved in the present invention.

[0054] Figure 8 For example 3, only Figure 4 The process steps (1) and (2) shown in the figure and the implementation Figure 4 Schematic diagram showing how the breakdown voltage of the VLD terminal changes with the implantation dose dose1 in the process steps (1)-(4).

[0055] Fig. 9 Dose 1 in Example 3 is 1.5e13 cm -2 Only implemented when Figure 4 The process flow (1), (2) and implementation steps shown Figure 4 Schematic diagram of the partial surface electric field of the VLD terminal in the process flow (1)-(4) steps shown. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Example 1

[0058] A VLD terminal that reduces the surface electric field improves the wavy impurity distribution of the VLD terminal through two ion implantations, making the impurity distribution closer to a smooth gradient impurity distribution, thereby improving the reliability problem of the VLD terminal with excessively high surface electric field peak value caused by uneven impurity distribution and improving the withstand voltage performance of the VLD terminal. The process flow for its implementation is as follows: Figure 4 shown.

[0059] (1) By setting a mask, etching the oxide layer 8 to open a window, and performing the first ion implantation;

[0060] (2) high temperature annealing to form a second conductivity type semiconductor doped region 5;

[0061] (3) Setting a mask, etching the oxide layer 8 to open a window, and performing a second ion implantation;

[0062] (4) high temperature annealing to obtain a smoother and more gradual second conductivity type semiconductor doping region 5.

[0063] Example 2

[0064] A VLD terminal that reduces the surface electric field improves the wavy impurity distribution of the VLD terminal through two ion implantations, making the impurity distribution closer to a smooth gradient impurity distribution, thereby improving the reliability problem of the VLD terminal with excessively high surface electric field peak value caused by uneven impurity distribution and improving the withstand voltage performance of the VLD terminal. The process flow for its implementation is as follows: Figure 4 shown.

[0065] (1) By setting a mask, etching the oxide layer 8 to open a window, and performing the first ion implantation;

[0066] Step (1) is further: Figure 5 Schematic diagram of the first ion implantation mask setting for the VLD terminal. The VLD terminal BC is divided into N segments, each with a length of L. VLD / N, where the length of the VLD terminal is L VLD The window width of the nth mask is a n , impurity injection is achieved in this area. The width of the shielding area is b n , both satisfy a n +bn =L VLD / N. The first ion implantation dose is dose1.

[0067] (2) high temperature annealing to form a second conductivity type semiconductor doped region 5;

[0068] Step (2) is further: high temperature annealing, so that the injected impurities are connected into one piece through the diffusion of impurities, so as to form a second conductive type semiconductor variable doping region 5. n-1 and a n The impurity distribution of the two implants satisfies the Gaussian distribution function after high temperature annealing. n The impurity distribution under the window area a is approximately satisfied n-1 with a n The superposition of the implanted impurities, such as Figure 6 As shown, the mask shielding area b n The impurity distribution function C under (x) satisfy

[0069]

[0070] The first ion implantation dose is dose1, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as annealing temperature, and t represents the high-temperature annealing time. According to the impurity distribution function C (x) , obviously in the mask shielding area b n Next x J At position, there is a point J with the lowest impurity concentration.

[0071] (3) Setting a mask, etching the oxide layer 8 to open a window, and performing a second ion implantation;

[0072] Step (3) is further as follows: the mask for the second ion implantation is as follows: Figure 7 As shown. Divide the VLD terminal BC into N segments, each segment is L in length VLD / N, where the length of the VLD terminal is L VLD The window width of the nth mask is c n , impurity injection is achieved in this area. The width of the shielding area is d n , both satisfy c n +d n =L VLD / N. The window width of the nth mask is c n Located in the first ion implantation mask shielding area b nInside, that is, in the first ion implantation shielding area b n Ion implantation is performed on some areas inside.

[0073] Figure 1 The lowest impurity concentration point J is located at b n Below, to ensure that the second ion implantation can make up for the impurity concentration at the lowest impurity concentration point J, the wavy impurity distribution is improved to make the impurity distribution smoother and more gradual.

[0074] For x n The impurity distribution of the position approximately satisfies

[0075]

[0076] For x n-1 The impurity distribution of the position approximately satisfies

[0077]

[0078] If the shielding area b n The x-axis coordinate of the center position is According to C (x) Expression, x J satisfy

[0079]

[0080] Second ion implantation mask window area c n The range is x J The scope of location.

[0081] The second ion implantation dose is dose2, which should be less than the first ion implantation dose dose1, and the two meet

[0082] 0<dose2≤0.25dose1

[0083] (4) High temperature annealing to obtain a smoother and more gradual second conductivity type semiconductor variable doping region 5. High temperature refers to a temperature greater than 1100°C.

[0084] (5) Step (4) is further performed by high temperature annealing, so that the injected impurities are connected into one piece through the diffusion of impurities, thereby forming a second conductive type semiconductor variable doping region 5 with a smoother gradual impurity distribution. Figure 1 The depression at the low and medium impurity concentration position J is supplemented, and the surface electric field is reduced. The temperature of high temperature annealing is greater than 1100°C.

[0085] At this time x J Position impurity distribution satisfy

[0086]

[0087] The second ion implantation dose is dose2, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to factors such as annealing temperature, t represents the high-temperature annealing time of the first ion implantation, and t' represents the high-temperature annealing time of the second ion implantation.

[0088] At this time there is

[0089]

[0090] Thus, the impurity concentration at the lowest impurity concentration point J is increased, and the wavy impurity distribution is improved, making the impurity distribution smoother and more gradual. At this time, the surface electric field can be reduced, and the peak surface electric field at point J is reduced from E max1 Reduce to E max2 ,like Figure 1 shown.

[0091] The VLD terminal for reducing the surface electric field is used for the lateral variable doping terminal design of diodes, BJTs, MOSFETs, JFETs, and IGBT power semiconductor devices.

[0092] The power semiconductor device with the terminal is manufactured using semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium phosphide and gallium nitride.

[0093] Example 3

[0094] In this example, a VLD terminal for reducing the surface electric field proposed in the invention is applied to a VDMOS with a withstand voltage of 1400V. The specific steps are as follows:

[0095] (1) The VDMOS cell is designed through simulation, and the designed cell withstand voltage is 1615V. The total length of the VLD terminal is set to 180μm, the number of mask segments n is 12, and each segment is 15μm long. The length of the shielding area b n The change of the number of segments n is shown in Table 1. The ion implantation is performed with this mask, and the ion implantation dose dose1 is 1.5e13cm -2 .

[0096] Table 1 Length b of the VLD terminal shielding area for the first ion implantation in Example 3 n

[0097] n 1 2 3 4 5 6 <![CDATA[b n / μm]]> 2 3 4 5 6 7 n 7 8 9 10 11 12 <![CDATA[b n / μm]]> 8 9 10 11 12 13

[0098] (2) The first ion implantation high temperature annealing, the annealing temperature is 1150°C, and the time is 500 minutes.

[0099] (3) The number of segments n of the second ion implantation mask is 12, and each segment is 15 μm long. The length of the shielding area d n The change of the number of segments n is shown in Table 2. The ion implantation was performed with this mask, and the second ion implantation dose was 1e12 cm -2 .

[0100] Table 2 Length c of the VLD terminal window area for the second ion implantation in Example 3 n

[0101] n 1 2 3 4 5 6 <![CDATA[c n / μm]]> 1 1.5 2 2.5 3 3.5 n 7 8 9 10 11 12 <![CDATA[c n / μm]]> 4 4.5 5 5.5 6 6.5

[0102] (4) The second ion implantation high temperature annealing is performed at a temperature of 1150°C for 500 minutes.

[0103] (5) Carry out simulation experiments on the design scheme, such as Figure 8 The figure shows the breakdown voltage of the VLD terminal implemented by only performing steps (1) and (2) and the VLD terminal implemented by performing steps (1) to (4) as a function of the implantation dose dose1. It can be seen that the VLD terminal implemented by performing steps (1) to (4) has a better breakdown voltage. Fig. 9 FIG. 5 is a schematic diagram of a portion of the surface electric field of a VLD terminal implemented by performing only steps (1) and (2) and a VLD terminal implemented by performing steps (1) to (4). It can be seen that the VLD terminal implemented by performing steps (1) to (4) completely has a lower surface electric field peak value. The surface electric field at the same x-axis position can be reduced from 1.5e5 V / cm to below 1e5 V / cm, which is a large reduction. This means that the VLD terminal implemented by this design method has better reliability, the improvement effect is very obvious, and the withstand voltage performance has also been effectively improved.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A VLD terminal for reducing the surface electric field, which improves the wavy impurity distribution of the VLD terminal by two ion implantations, so that the impurity distribution is closer to a smooth gradual impurity distribution, thereby improving the reliability problem of the VLD terminal with too high surface electric field peak value caused by uneven impurity distribution and improving the performance of the VLD terminal, characterized in that The process flow is as follows: (1) by setting a mask, etching the oxide layer (8) to open a window, and performing the first ion implantation; (2) high temperature annealing to form a second conductivity type semiconductor variable doping region (5); (3) setting a mask, etching the oxide layer (8) to open a window, and performing a second ion implantation; (4) high temperature annealing to obtain a smoother and more gradual second conductivity type semiconductor doping region (5).

2. A VLD terminal for reducing surface electric field according to claim 1, characterized in that: Step (1) is further as follows: setting a mask for the first ion implantation of the VLD terminal, dividing the VLD terminal BC into N segments, each segment having a length of L VLD / N, where the length of the VLD terminal is L VLD , using positive photoresist for photolithography, the window width of the nth mask is a n , impurities are injected into this area, and the width of the shielding area is b n , both satisfy a n +b n =L VLD / N, the first ion implantation dose is dose1.

3. A VLD terminal for reducing surface electric field according to claim 1, characterized in that: Step (2) is further: high temperature annealing, through the diffusion of impurities, the injected impurities are connected into one piece to form a second conductive type semiconductor variable doping region (5), for the window area a n-1 and a n The impurity distribution of the two implants satisfies the Gaussian distribution function after high temperature annealing. n The impurity distribution under the window area a is approximately satisfied n-1 with a n The superposition of the injected impurities, the mask shielding area b n The impurity distribution function C(x) satisfies The first ion implantation dose is dise1, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to the annealing temperature factor, t represents the high temperature annealing time, according to the impurity distribution function C (x) , obviously in the mask shielding area b n Next x J At position, there is a point J with the lowest impurity concentration.

4. A VLD terminal for reducing surface electric field according to claim 1, characterized in that: Step (3) is further as follows: the mask for the second ion implantation is divided into N segments, each segment is L in length. VLD / N, where the length of the VLD terminal is L VLD , the window width of the nth mask is c n , impurities are injected into this area, and the width of the shielding area is d n , both satisfy c n +d n =L VLD / N, the window width of the nth mask is c n Located in the first ion implantation mask shielding area b n Inside, that is, in the first ion implantation shielding area b n Ion implantation is performed on some areas of the interior; The lowest impurity concentration point J is located at b n Below, to ensure that the second ion implantation can make up for the impurity concentration at the lowest impurity concentration point J, so as to improve the wavy impurity distribution and make the impurity distribution smoother and more gradual; For x n The impurity distribution of the position approximately satisfies For x n-1 The impurity distribution of the position approximately satisfies If the shielding area b n The x-axis coordinate of the center position is According to C (x) Expression, x J satisfy Second ion implantation mask window area c n The range is x J Scope of location; The second ion implantation dose is dose2, which should be less than the first ion implantation dose dose1, and the two meet 0 <dose2≤0.25dose1。 5. A VLD terminal for reducing surface electric field according to claim 1, characterized in that: Step (4) is further as follows: high temperature annealing, so that the injected impurities are connected into one piece through the diffusion of impurities, forming a second conductivity type semiconductor variable doping region 5 with a smoother gradual impurity distribution, the depression at the low impurity concentration position J is supplemented, and the surface electric field is reduced; At this time x J Position impurity distribution satisfy The second ion implantation dose is dose2, x n for a n The x-axis coordinate corresponding to the center position, x n-1 for a n-1 The x-axis coordinate corresponding to the center position, D is the impurity diffusion coefficient, which is related to the annealing temperature factor, t represents the high-temperature annealing time of the first ion implantation, and t′ represents the high-temperature annealing time of the second ion implantation; At this time there is Thus, the impurity concentration at the lowest impurity concentration point J is increased, and the wavy impurity distribution is improved, making the impurity distribution smoother and more gradual. At this time, the surface electric field can be reduced, and the peak surface electric field at point J is reduced from E max1 Reduce to E max2 .

6. A VLD terminal for reducing surface electric field according to claim 1, characterized in that: The process flow is implemented for the lateral variable doping terminal design of diodes, BJTs, MOSFETs, JFETs, and IGBT power semiconductor devices.

7. A VLD terminal for reducing surface electric field according to claim 1, characterized in that: The power semiconductor device with the terminal is manufactured using semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium phosphide and gallium nitride.

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