Film layer pattern transfer method and semiconductor structure

Abstract

The invention discloses a film layer pattern transfer method and a semiconductor structure. The film layer pattern transfer method comprises the following steps: forming a hard mask layer with an initial pattern on a semiconductor layer; a film layer is formed, the first part of the film layer is located on the hard mask layer, and the window part of the hard mask layer is filled with the second part of the film layer; and removing the first part of the film layer and the hard mask layer, and retaining the second part of the film layer, wherein the remaining second part of the film layer is provided with a target pattern complementary to the initial pattern, and the line width of the hard mask layer with the initial pattern limits the opening size of the second part of the film layer. According to the embodiment of the invention, the influence of lateral etching of a wet etching process is solved, and the size accuracy of the window of the film layer is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a film pattern transfer method and a semiconductor structure. Background Art

[0002] Etching is a process that selectively removes unwanted parts from semiconductor materials to meet the requirements of integrated circuit chip manufacturing. The combination of photolithography and wet etching processes is used in the semiconductor industry to manufacture transistors and integrated circuit chips. With the help of photolithography, the pattern of photoresist is defined on the surface of the semiconductor material, and then the pattern of device and circuit design is transferred to the semiconductor material through etching.

[0003] Integrated circuit chip manufacturing mainly relies on wet etching process. However, wet etching is isotropic etching. While etching vertically, etching also occurs horizontally. Lateral etching will lead to a decrease in the accuracy of the etching pattern, that is, critical dimension loss (CD loss). As the minimum feature size of semiconductor devices gradually decreases, the accuracy of the etching pattern decreases significantly. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a method for forming a window of a film layer, a method for transferring a film layer pattern and a semiconductor structure, so as to solve the problem of lateral etching in wet etching.

[0005] According to one aspect of the present invention, a method for transferring a film layer pattern is provided, comprising: forming a hard mask layer having an initial pattern on a semiconductor layer; forming a film layer, wherein a first portion of the film layer is located on the hard mask layer, and a second portion of the film layer fills a window portion of the hard mask layer; and removing the first portion of the film layer and the hard mask layer, retaining the second portion of the film layer; wherein the remaining second portion of the film layer has a target pattern complementary to the initial pattern, and the line width of the hard mask layer having the initial pattern defines the opening size of the second portion of the film layer.

[0006] Optionally, a method for forming a hard mask layer having an initial pattern on a semiconductor layer includes: sequentially forming a protective layer and a hard mask layer on the semiconductor layer; forming a patterned resist layer on the hard mask layer; etching the hard mask layer through the patterned resist layer to form a hard mask layer having an initial pattern; and patterning the protective layer through the hard mask layer; wherein the hard mask layer is etched using a dry etching process, and during the dry etching process, the protective layer serves as a protective layer for the semiconductor layer.

[0007] Optionally, the protection layer and the hard mask layer have different etching selectivities, and a wet etching process is used to pattern the protection layer.

[0008] Optionally, during the process of patterning the protective layer, a depression is generated on the sidewall of the protective layer, the protective layer after patterning has the same pattern as the hard mask layer, and the line width of the patterned protective layer is smaller than the line width of the patterned hard mask layer.

[0009] Optionally, the film layer is formed by an APCVD process, the sidewall of the second portion of the film layer contacts the sidewall of the hard mask layer, and the sidewall of the second portion of the film layer is spaced from the sidewall of the protective layer via a recess.

[0010] Optionally, there is a height difference between the first portion and the second portion of the film layer, and a chemical mechanical polishing process is used to remove the first portion of the film layer and the hard mask layer.

[0011] Optionally, the chemical mechanical polishing stops when the protective layer is exposed and the remaining second portion is flush with the top of the protective layer.

[0012] Optionally, the method further includes a step of removing the protective layer, wherein the protective layer and the film layer have different etching selectivities, and a wet etching process is used to remove the protective layer.

[0013] Optionally, the protective layer is an oxide layer, the hard mask layer is a nitride layer, and the film layer is a nitride layer.

[0014] According to another aspect of the present invention, a semiconductor structure is provided, comprising: a semiconductor layer; and a film layer formed by the above-mentioned film layer pattern transfer method, wherein the film layer is located on the semiconductor layer and has a target pattern.

[0015] The unexpected technical effects of this application are:

[0016] In the transfer method of the film layer pattern of the embodiment of the present application, a hard mask layer having an initial pattern is formed, and a film layer is formed via the hard mask layer, wherein the first part of the film layer is located on the hard mask layer, and the second part of the film layer fills the window part of the hard mask layer, and after removing the first part of the film layer, the remaining second part has a target pattern complementary to the initial pattern, and the line width of the hard mask layer having the initial pattern defines the opening size of the second part of the film layer. In this embodiment, the pattern of the second part of the film layer is defined by the hard mask layer, and the opening size of the second part of the film layer is defined by the line width of the hard mask layer having the initial pattern, which solves the influence of lateral etching in the wet etching process and ensures the dimensional accuracy of the window of the film layer.

[0017] In a preferred embodiment, dry etching is used to form a hard mask layer having an initial pattern to ensure the accuracy of the line width of the hard mask layer.

[0018] In a preferred embodiment, a protection layer is formed before forming the patterned hard mask layer to prevent the dry etching process from damaging the semiconductor layer.

[0019] In a preferred embodiment, before forming the film layer, the protection layer is patterned via the hard mask layer to prevent the protection layer from affecting the second portion of the formed film layer.

[0020] Furthermore, the hard mask layer and the protective layer have different etching selectivity ratios, and the patterned protective layer is etched by wet etching to prevent damage to the semiconductor layer.

[0021] In a preferred embodiment, an APCVD process is used to form a film layer, wherein the second portion of the semiconductor layer fills the window of the hard mask layer, and the second portion of the film layer has a target pattern, and the target pattern is complementary to the initial pattern of the hard mask layer. This embodiment utilizes the characteristics of the deposition process to form the second portion of the semiconductor layer. Compared with wet etching, this embodiment will not be affected by lateral etching, thereby ensuring the accuracy of the window size in the film layer.

[0022] In a preferred embodiment, utilizing the height difference between the first portion and the second portion of the film layer and the characteristics of the chemical mechanical polishing process, a chemical mechanical polishing process is adopted to remove the first portion of the film layer and the hard mask layer, while at least a portion of the second portion is retained, and the size of the second portion of the film layer is not affected.

[0023] In a preferred embodiment, a wet etching process is used to remove the protective layer to avoid damage to the semiconductor layer. Since there is a high etching selectivity ratio between the protective layer and the film layer, the problem of lateral etching during the wet etching process is greatly improved to ensure the opening size of the film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which: Figure 1a to Figure 1c A schematic diagram of a conventional film pattern transfer method is shown; wherein: Figure 1a A schematic diagram showing forming a film layer on a semiconductor layer; Figure 1b A schematic diagram showing forming a resist layer on a film layer and patterning the resist layer using a photolithography process; Figure 1c A schematic diagram showing a process of using a resist layer as a mask to remove an exposed portion of a film layer through an opening area of ​​the resist layer to form a window is shown; Figure 2 A flow chart showing a method for transferring a film layer pattern according to an embodiment of the present application is shown; Figure 3a to Figure 3f shows cross-sectional views of various stages in the transfer process of a film layer pattern according to an embodiment of the present application; Figure 3a A cross-sectional view showing a protective layer and a hard mask layer stacked in sequence formed on a semiconductor layer according to an embodiment of the present application; Figure 3b-1 A cross-sectional view showing a process of forming a patterned resist layer on a hard mask layer and patterning the hard mask layer through the resist layer in one embodiment of the present application; Figure 3b-2 A cross-sectional view showing a process of forming a patterned resist layer on a hard mask layer and patterning the hard mask layer through the resist layer in another embodiment of the present application; Figure 3c A cross-sectional view of patterning a protective layer through a hard mask layer according to an embodiment of the present application is shown; Figure 3d A cross-sectional view showing a film layer formed by a deposition process in an embodiment of the present application is shown; Figure 3e A cross-sectional view showing a first portion of a film layer and a mask layer removed in an embodiment of the present application is shown; Figure 3f A cross-sectional view of an embodiment of the present application with the protective layer removed is shown.

[0025] Explanation of the reference numerals: 10-first mask; 11-first light-shielding area; 12-first light-transmitting area; 110-first semiconductor layer; 120-first film layer; 121-first window; 121a-first recess; PR1-first resist layer; 20-second mask; 21-second light-shielding area; 22-second light-transmitting area; 210-second semiconductor layer; 220-protective layer; 220a-second recess; 230-hard mask layer; 231-second window; 240-second film layer; 241-first part; 242-second part; PR2-second resist layer; 30-third mask; 31-third light-shielding area; 32-third light-transmitting area. DETAILED DESCRIPTION

[0026] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0027] This application may be presented in a variety of forms, some examples of which are described below.

[0028] Figure 1a to Figure 1c A schematic diagram showing a conventional film layer pattern transfer method.

[0029] like Figure 1aAs shown, a first film layer 120 is formed on the first semiconductor layer 110 .

[0030] like Figure 1b As shown, a first resist layer PR1 is formed on the first film layer 120 , and the first resist layer PR1 is patterned by using a photolithography process.

[0031] In this step, a first resist layer PR1 is formed on the first film layer 120 , a first mask plate 10 is disposed above the first resist layer PR1 , and the first resist layer PR1 is photolithographically processed through the first mask plate 10 to form a target pattern on the first resist layer PR1 .

[0032] The first mask 10 includes a first light shielding region 11 and a first light transmitting region 12. In the photolithography step, the first resist layer PR1 is exposed through the first mask 10, and the exposed portion of the first resist layer PR1 is removed during development, thereby forming an opening region corresponding to the first light transmitting region 12 of the first mask 10 in the first resist layer PR1.

[0033] like Figure 1c As shown, the first resist layer PR1 is used as a mask, and the exposed portion of the first film layer 120 is removed through the opening area of ​​the resist layer PR to form a first window 121 .

[0034] When the first film layer 120 is etched by a wet etching process, the etchant etches the first film layer 120 isotropically, that is, while the etchant etches the first film layer 120 downward, it also etches the first film layer 120 laterally to form a lateral recess 121a, such as Figure 1c As shown, the lateral etching has a great influence on the etching accuracy, so that the area defined by the first window 121 is not accurate enough, thereby affecting the preparation of subsequent processes.

[0035] In other embodiments, dry etching may be used to form the first window 121 . Dry etching can ensure the size of the first window 121 , but dry etching is very likely to result in over-etching, which inevitably damages the surface of the first semiconductor layer 110 .

[0036] Figure 2 A flow chart of a method for transferring a film pattern according to an embodiment of the present application is shown. Figure 2 As shown, the film pattern transfer method includes: S10: forming a protective layer on the semiconductor layer and forming a hard mask layer having an initial pattern on the protective layer; S20: forming a film layer, wherein a first portion of the film layer is located on the hard mask layer, and a second portion of the film layer fills a window portion of the hard mask layer; S30: removing the first portion of the film layer and the hard mask layer, and retaining the second portion of the film layer; S40: removing the protective layer.

[0037] The remaining second portion of the film layer has a target pattern complementary to the initial pattern, and the line width of the hard mask layer having the initial pattern defines the opening size of the second portion of the film layer.

[0038] Figure 3a to Figure 3f The cross-sectional views of various stages in the process of forming the window of the film layer according to the embodiment of the present application are shown below. Figure 2 as well as Figures 3a to 3f The method for transferring the film layer pattern according to the embodiment of the present application is described.

[0039] like Figure 3a to Figure 3c As shown, in step S10 , a protection layer 220 is formed on the second semiconductor layer 210 and a hard mask layer 230 having an initial pattern is formed on the protection layer 220 , wherein the initial pattern is complementary to the target pattern.

[0040] Specifically, Figure 3a As shown, a stacked protective layer 220 and a hard mask layer 230 are sequentially formed on the second semiconductor layer 210. The second semiconductor layer 210 may include one or more structural layers, and a part or all of the structures of one or more semiconductor devices may be formed in the second semiconductor layer 210. The protective layer 220 and the hard mask layer 230 have different etching selectivities. In one embodiment, the protective layer 220 is, for example, an oxide layer, and the hard mask layer 230 is, for example, a nitride layer, but the present invention is not limited thereto.

[0041] Next, a patterned resist layer is formed on the hard mask layer 230 by a photolithography process, and the hard mask layer 230 is etched through the patterned resist layer to transfer the pattern of the resist layer to the hard mask layer 230. The resist layer and the hard mask layer 230 have initial patterns complementary to the target pattern.

[0042] In semiconductor processing, the photolithography step and etching step for patterning are independent of each other. Figure 3b-1 and Figure 3b-2 The sequential steps of photolithography and etching are combined together to clearly illustrate the principle of patterning the hard mask layer 230. According to the reaction mode of the resist layer, it can be divided into positive resist and negative resist. The exposed part of the positive resist is removed during development to form an opening area, and the exposed part of the negative resist is retained during development to form a shielding area. It can be understood that in the case of using a negative resist, the window pattern of the mask is a complementary pattern using a positive resist.

[0043] like Figure 3b-1 In the illustrated embodiment, the second resist layer PR2 is a positive resist. The step of patterning the hard mask layer 230 specifically includes: forming the second resist layer PR2 on the hard mask layer 230, arranging the second mask 20 above the second resist layer PR2, exposing the second resist layer PR2 via the second mask 20 to transfer the pattern of the second mask 20 to the second resist layer PR2, and etching the hard mask layer 230 via the second resist layer PR2 to transfer the pattern of the second resist layer PR2 to the hard mask layer 230. The second mask 20 includes a second light-shielding area 21 and a second light-transmitting area 22. In the photolithography step, the second resist layer PR2 is exposed via the second mask 20, and the exposed portion of the second resist layer PR2 is removed during development, thereby forming an opening area corresponding to the second light-transmitting area 22 of the second mask 20 in the second resist layer PR2. In the etching step, the second resist layer PR2 serves as a mask, and the exposed portion of the hard mask layer 230 is removed through the opening region of the second resist layer PR2 to form a second window 231 in the hard mask layer 230 .

[0044] The patterned hard mask layer 230 has an initial pattern complementary to the target pattern. In other words, the window portion of the hard mask layer 230 corresponds to the pattern portion of the target pattern, and the pattern portion of the hard mask layer 230 corresponds to the window portion of the target pattern. Figure 3b-1 In the embodiment shown, the pattern of the second mask 20 is Figure 1b The pattern of the first mask 10 is complementary.

[0045] In another embodiment, if Figure 3b-2 As shown, the second resist layer PR2 is a negative resist. In the photolithography step, the second resist layer PR2 is exposed via the third mask 30, and the light-shielding portion of the second resist layer PR2 is removed during development, thereby forming an opening area corresponding to the third light-shielding area 31 of the third mask 30 in the second resist layer PR2. In the etching step, the second resist layer PR2 is used as a mask, and the exposed portion of the hard mask layer 230 is removed via the opening area of ​​the second resist layer PR2 to form a second window 231.

[0046] Figure 3b-2 In the embodiment shown, the pattern of the third mask 30 is Figure 1b The pattern of the first mask 10 is the same, and the mask of the traditional technology can be used without re-making the mask.

[0047] Furthermore, since the pattern portion of the hard mask layer 230 corresponds to the window portion of the target pattern, the present application sets the line width of the pattern portion of the hard mask layer 230 to the size of the window of the target pattern, for example, the first size CD1, to limit the window size of the second film layer 240 in subsequent steps.

[0048] Furthermore, the hard mask layer 230 is patterned by dry etching to ensure the etching accuracy of the hard mask layer 230. In addition, since the hard mask layer 230 is protected by the protective layer 220, the second semiconductor layer 210 is prevented from being damaged by dry etching.

[0049] like Figure 3c As shown, the protection layer 220 is patterned via the hard mask layer 230 .

[0050] The protective layer 220 is patterned by a wet etching process to avoid damage to the second semiconductor layer 210. Since the protective layer 220 and the hard mask layer 230 have different etching selectivities, when one of the protective layer 220 and the hard mask layer 230 is removed by the etchant, the other is not affected by the etchant. In this embodiment, an etchant for wet etching is selected so that when the protective layer 220 is removed, the hard mask layer 230 is not affected by the etchant.

[0051] Further, the protective layer 220 has the same pattern as the hard mask layer 230. However, due to the influence of lateral etching during the wet etching process, a second recess 220a is generated on the sidewall of the pattern portion of the protective layer 220 relative to the hard mask layer 230, so that the line width of the pattern portion of the protective layer 220 is smaller than the line width of the pattern portion of the hard mask layer 230, and will not affect the subsequent deposition of the second film layer 240. For example, the line width of the pattern portion of the protective layer 220 has a second size CD2 that is smaller than the first size CD1.

[0052] like Figure 3d As shown, in step S20 , a second film layer 240 is formed, a first portion 241 of the second film layer 240 is located on the hard mask layer 230 , and a second portion 242 of the second film layer 240 fills the window portion of the hard mask layer 230 .

[0053] In this step, for example, a deposition process is used to form the second film layer 240. The second film layer 240 conformally covers the remaining hard mask layer 230 and the window of the hard mask layer 230, wherein the first portion 241 of the second film layer 240 is located on the hard mask layer 230. Further, since the second recess 220a is covered by the hard mask layer 230, the vertical coverage characteristic of the deposition process makes the second film layer 240 not laterally fill the second recess 220a of the protective layer 220, and the second portion 242 of the second film layer 240 fills the window portion of the hard mask layer 230. The sidewall of the second portion 242 of the second film layer 240 contacts the sidewall of the hard mask layer 230, and is spaced from the sidewall of the protective layer 220 via the second recess 220a.

[0054] Furthermore, in the present embodiment, for example, an APCVD (Atmospheric Pressure Chemical Vapor Deposition) process is used. Compared with LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma-Enhanced Chemical Vapor Deposition), MOCVD (Metal-Organic Chemical Vapor Deposition), etc., the APCVD process has a poor pore filling ability. The present application utilizes the poor lateral filling ability of the APCVD process to prevent the second film layer 240 formed by the deposition process from being laterally filled into the second recess 220a.

[0055] Furthermore, since the hard mask layer 230 has an initial pattern complementary to the target pattern, the second portion 242 filling the window portion of the hard mask layer 230 has the target pattern. Furthermore, the vertical coverage characteristic of the deposition process enables the window of the second portion 242 of the second film layer 240 to have an accurate first size CD1.

[0056] Since the protective layer 220 needs to be removed later, in this embodiment, the protective layer 220 and the second film layer 240 have a higher etching selectivity. In one embodiment, the protective layer 220 is, for example, an oxide layer, and the second film layer 240 is, for example, a nitride layer, but the present invention is not limited thereto.

[0057] like Figure 3e As shown, in step S30 , the first portion 241 of the second film layer 240 and the hard mask layer 230 are removed, and the second portion 242 of the second film layer 240 is retained.

[0058] In this step, since there is a height difference between the first part 241 and the second part 242 of the second film layer 240, the present embodiment can utilize the height difference between the first part 241 and the second part 242 to remove the first part 241 of the second film layer 240 by using a CMP (Chemical Mechanical Planarization) process, while retaining the second part 242 of the second film layer 240. Furthermore, since a protective layer 220 is also provided below the hard mask layer 230 in the present application, the hard mask layer 230 can be removed by using a CMP process, and the second part 242 of the second film layer 240 will not be completely removed when the hard mask layer 230 is removed. The CMP process stops when the protective layer 220 is exposed and the remaining second part 242 of the second film layer 240 is flush with the top of the protective layer 220.

[0059] like Figure 3f As shown, in step S40, the protection layer 220 is removed.

[0060] In this step, a wet etching process is used to remove the protective layer 220 to avoid damage to the second semiconductor layer 210. Furthermore, since the protective layer 220 and the second film layer 240 have different etching selectivities, when the protective layer 220 is removed, the second film layer 240 is not affected, and the window of the second film layer 240 maintains the first size CD1. The embodiment of the present application overcomes the problem of lateral etching in the traditional process and ensures the size of the window portion of the second film layer 240.

[0061] The unexpected technical effects of this application are:

[0062] In the film layer pattern transfer method of the embodiment of the present application, a hard mask layer with an initial pattern is formed, and a film layer with a target pattern is self-alignedly formed through the hard mask layer with the initial pattern to form a window in the film layer, wherein the initial pattern is complementary to the target pattern, and the size of the window in the film layer depends on the size of the hard mask layer that is retained. In this embodiment, a window is formed in the film layer by a self-alignment method, and the size of the window in the film layer depends on the size of the hard mask layer that is retained, which solves the influence of lateral etching in the wet etching process and ensures the size accuracy of the window in the film layer.

[0063] In a preferred embodiment, dry etching is used to form a hard mask layer having an initial pattern to ensure the size of the remaining hard mask layer.

[0064] In a preferred embodiment, a protection layer is formed before forming the patterned hard mask layer to prevent the dry etching process from damaging the semiconductor layer.

[0065] In a preferred embodiment, before forming a film layer having a target pattern in a self-aligned manner, the protection layer is patterned via a hard mask layer to prevent the protection layer from affecting the self-alignment process of the film layer.

[0066] Furthermore, the hard mask layer and the protective layer have different etching selectivity ratios, and the patterned protective layer is etched by wet etching to prevent damage to the semiconductor layer.

[0067] In a preferred embodiment, an APCVD process is used to form a film layer, wherein the second portion of the semiconductor layer self-aligns to fill the window of the hard mask layer, and the second portion of the film layer has a target pattern, and the target pattern is complementary to the initial pattern of the hard mask layer. This embodiment utilizes the characteristics of the deposition process to self-align the second portion of the semiconductor layer. Compared with wet etching, this embodiment will not be affected by lateral etching, thereby ensuring the accuracy of the window size in the film layer.

[0068] In a preferred embodiment, utilizing the height difference between the first portion and the second portion of the film layer and the characteristics of the chemical mechanical polishing process, a chemical mechanical polishing process is adopted to remove the first portion of the film layer and the hard mask layer, while at least a portion of the second portion is retained, and the size of the second portion of the film layer is not affected.

[0069] In a preferred embodiment, a wet etching process is used to remove the protective layer to avoid damage to the semiconductor layer. Since there is a high etching selectivity ratio between the protective layer and the film layer, the problem of lateral etching during the wet etching process is greatly improved to ensure the size of the window part of the film layer.

[0070] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for transferring a film pattern, comprising: forming a hard mask layer having an initial pattern on the semiconductor layer; forming a film layer, wherein a first portion of the film layer is located on the hard mask layer, and a second portion of the film layer fills a window portion of the hard mask layer; as well as removing the first portion of the film layer and the hard mask layer, and retaining the second portion of the film layer; The remaining second portion of the film layer has a target pattern complementary to the initial pattern, and the line width of the hard mask layer having the initial pattern defines the opening size of the second portion of the film layer.

2. The method for transferring a film pattern according to claim 1, wherein: The method of forming a hard mask layer having an initial pattern on a semiconductor layer includes: forming a protective layer and a hard mask layer in sequence on the semiconductor layer; forming a patterned resist layer on the hard mask layer; etching the hard mask layer through the patterned resist layer to form a hard mask layer having an initial pattern; and patterning the protective layer via the hard mask layer; Wherein, the hard mask layer is etched by a dry etching process, and during the dry etching process, the protective layer serves as a protective layer for the semiconductor layer.

3. The method for transferring a film pattern according to claim 2, wherein: The protection layer and the hard mask layer have different etching selectivity ratios, and the protection layer is patterned by a wet etching process.

4. The method for transferring a film pattern according to claim 3, wherein: During the process of patterning the protective layer, a depression is generated on the sidewall of the protective layer. The protective layer after patterning has the same pattern as the hard mask layer, and the line width of the patterned protective layer is smaller than the line width of the patterned hard mask layer.

5. The method for transferring a film pattern according to claim 4, wherein: The film layer is formed by adopting an APCVD process, the sidewall of the second portion of the film layer contacts the sidewall of the hard mask layer, and the sidewall of the second portion of the film layer is spaced from the sidewall of the protective layer via a recess.

6. The method for transferring a film pattern according to claim 2, wherein: There is a height difference between the first part and the second part of the film layer, and a chemical mechanical polishing process is adopted to remove the first part of the film layer and the hard mask layer.

7. The method for transferring a film pattern according to claim 6, wherein: The chemical mechanical polishing stops when the protective layer is exposed and the remaining second portion is flush with the top of the protective layer.

8. The method for transferring a film pattern according to claim 7, wherein: The method also includes a step of removing the protective layer, wherein the protective layer and the film layer have different etching selectivity ratios, and a wet etching process is used to remove the protective layer.

9. The method for transferring a film pattern according to claim 8, wherein: The protection layer is an oxide layer, the hard mask layer is a nitride layer, and the film layer is a nitride layer.

10. A semiconductor structure comprising: Semiconductor layer; as well as A film layer formed by the film layer pattern transfer method according to any one of claims 1 to 9, wherein the film layer is located on a semiconductor layer and has a target pattern.

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