Package-on-package structure and forming method thereof

Abstract

The invention discloses a stacked packaging structure and a forming method thereof, and the forming method comprises the steps: enabling a first active surface of a first chip to face downwards, and enabling the first active surface to be mounted on the upper surface of a substrate; a chip stacking structure is formed on the first back face of the first chip and comprises a plurality of second chips sequentially stacked in the vertical direction, each second chip comprises a second active face and a second back face which are opposite, the second active face is provided with micro protrusions, and the second back face is provided with second connecting terminals; the edge area of the second active surface of each second chip is provided with a plurality of discrete first diversion grooves, the second active surface of each second chip faces downwards, and the micro-bulges of the second active surface of the second chip on the upper layer in the chip stacking structure are welded with the second connecting terminals of the second back surface of the second chip on the adjacent lower layer; and forming a plastic package layer filled between the second chips on the upper layer and the lower layer, wherein the first diversion trench is beneficial to the flowing of a plastic package layer material when the plastic package layer is formed. And the filling difficulty of the plastic package layer material is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a stacked packaging structure and a method for forming the same. Background Art

[0002] HBM (High Bandwidth Memory) is a new type of CPU / GPU memory chip (ie "RAM"), which is actually a number of DDR chips stacked together and packaged together with the GPU to achieve a large-capacity, high-bit-width DDR combination array.

[0003] The existing 3D HBM (3D High Bandwidth Memory) packaging structure vertically stacks multiple memory chips (such as DRAM) through advanced packaging technology (such as TSV through silicon via technology and micro-bump technology) to increase storage capacity, and then interconnects them with the computing unit chip (GPU / CPU / SOC Die) based on the high-speed interface of the interposer.

[0004] The existing stacking processes for HBM production mainly include TC-NCF (Thermal Compression bonding, TC, Non-Conductive Film, NCF, thermal compression non-conductive adhesive film) process and MR-MUF (Mass Reflow bonding with Molded Underfill, batch reflow molding bottom filling) process.

[0005] The TC-NCF process requires placing a layer of non-conductive adhesive film (Non-Conductive Film) between each layer of memory chips during each stacking process to isolate the upper and lower layers of memory chips from each other and protect the soldering points from impact. This process has the problems of complex manufacturing process, low efficiency and high cost.

[0006] Compared with the TC-NCF process, the MR-MUF process reduces the chip stacking pressure to 6%, shortens the process time, increases production efficiency by 4 times, and improves the heat dissipation rate by 45%. However, after the MR-MUF process forms a memory chip stack, the memory chips need to be filled with plastic layer materials for isolation. However, when filling the plastic layer materials, the spacing between the upper and lower memory chips is very small, so there is a problem of difficulty in filling the plastic layer materials. Summary of the invention

[0007] The problem to be solved by the present application is to provide a stacked package structure and a method for forming the same, so as to reduce the difficulty in filling the plastic packaging layer material in the stacked chip structure.

[0008] In order to solve the above problems, the present application provides a method for forming a stacked package structure, comprising: providing a substrate, the substrate comprising opposing upper and lower surfaces; Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate; Providing a plurality of second chips, each of the second chips comprising a second active surface and a second back surface opposite to each other, the second active surface comprising a middle area and an edge area surrounding the middle area, the middle area of ​​the second active surface having a plurality of discrete micro protrusions, the edge area of ​​the second active surface having a plurality of discrete first guide grooves, and the second back surface having a plurality of discrete second connection terminals; forming a chip stacking structure on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, the second active side of each second chip facing downward, the micro-bumps on the second active side of the second chip in the upper layer of the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip in the adjacent lower layer, and the micro-bumps on the second active side of the second chip in the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A molding bottom filling process is performed to form a plastic layer that covers the chip stacking structure and the first chip, and fills between the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The first guide groove is conducive to the flow and filling of the plastic layer material when forming the plastic layer.

[0009] In an optional embodiment, the second chip further includes a side surface between the second active surface and the second back surface, the first guide groove penetrates part of the second active surface and part of the side surface of the second chip, and the bottom of the first guide groove is an inclined surface.

[0010] In an optional embodiment, the opening of the first guide groove facing the middle area is located on the extension line of the central axis of the gap between the two adjacent micro-protrusions; and the angle between the inclined surface and the second edged surface is 30 degrees to 60 degrees.

[0011] In an optional embodiment, in a direction from the side surface of the second chip to the middle area of ​​the second active surface, the size of the first guide groove remains unchanged or gradually decreases.

[0012] In an optional embodiment, the second back side of the second chip includes a middle area and an edge area surrounding the middle area, and a plurality of discrete second connection terminals are located in the middle area of ​​the second back side; a second guide groove is provided in the edge of the second back side of the second chip, and when the molding bottom filling process is performed to form the plastic encapsulation layer, the second guide groove is conducive to the flow and filling of the plastic encapsulation layer material.

[0013] In an optional embodiment, the second guide groove runs through part of the second back side and part of the side of the second chip, and the bottom of the second guide groove is an inclined surface; in the direction from the side of the second chip to the middle area of ​​the second back side, the size of the second guide groove remains unchanged or gradually decreases.

[0014] In an optional embodiment, the second guide groove in the second back side edge region of the second chip in the lower layer is located directly below the first guide groove in the second active side edge region of the second chip in the adjacent upper layer.

[0015] In an optional embodiment, a plurality of adjacent second guide grooves in the second back side edge region of the second chip of the lower layer serve as alignment marks when stacking the second chip of the upper layer on the second back side of the second chip of the lower layer.

[0016] In an optional embodiment, the first guide groove and the second guide groove are formed by an etching process.

[0017] In an optional embodiment, the process of forming a chip stacking structure on the first back side of the first chip includes a pre-fixing process and a batch reflow process; the pre-fixing process is first performed to stack and pre-fix a plurality of the second chips in sequence in a vertical direction; and a batch reflow process is performed to weld the micro-bumps on the second active surface of the second chip in the upper layer of the chip stacking structure to the second connecting terminal on the second back side of the adjacent second chip in the lower layer, and the micro-bumps on the second active surface of the second chip in the bottom layer to the first connecting terminal on the first back side of the first chip.

[0018] In an optional embodiment, when performing the pre-fixing process, the second chip of the upper layer and the adjacent second chip of the lower layer are pre-fixed by pre-soldering the flux in or on the surface of the micro-bumps with the corresponding second connecting terminals.

[0019] In an optional embodiment, when performing the pre-fixing process, the second chip of the upper layer and the adjacent second chip of the lower layer are bonded and fixed via a bonding layer located in an edge area between the second chip of the upper layer and the second chip of the lower layer to achieve the pre-fixing.

[0020] In an optional embodiment, the bonding layer is a temporary bonding layer or a mechanical bonding layer. The temporary bonding layer decomposes during a batch reflow process, and the mechanical bonding layer does not decompose during the mechanical bonding process and remains in the stacked packaging structure.

[0021] Another embodiment of the present application further provides a method for forming a stacked package structure, including: providing a substrate, the substrate comprising opposing upper and lower surfaces; Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate; Providing a plurality of second chips, each of the second chips comprising a second active surface and a second back surface opposite to each other, the second back surface comprising a middle area and an edge area surrounding the middle area, the second active surface having a plurality of discrete micro-protrusions, the edge area of ​​the second back surface having a plurality of discrete second guide grooves, and the middle area of ​​the second back surface having a plurality of discrete second connection terminals; forming a chip stacking structure on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, the second active side of each second chip facing downward, the micro-bumps on the second active side of the second chip in the upper layer of the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip in the adjacent lower layer, and the micro-bumps on the second active side of the second chip in the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A molding bottom filling process is performed to form a plastic layer that covers the chip stacking structure and the first chip, and fills between the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The second guide groove is conducive to the flow and filling of the plastic layer material when forming the plastic layer.

[0022] On the other hand, the present application also provides a stacked package structure, including: a substrate comprising opposing upper and lower surfaces; A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate; A chip stacking structure located on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface comprising a middle area and an edge area surrounding the middle area, the middle area of ​​the second active surface having a plurality of discrete micro-bumps, the edge area of ​​the second active surface having a plurality of discrete first guide grooves, the second back side having a plurality of discrete second connection terminals, the second active surface of each second chip facing downward, the micro-bumps on the second active surface of the second chip of the upper layer in the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip of the adjacent lower layer, and the micro-bumps on the second active surface of the second chip of the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A plastic encapsulation layer covers the chip stacking structure and the first chip, and fills the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The first guide groove is conducive to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer.

[0023] In an optional embodiment, it also includes: the second chip also includes a side surface located between the second active surface and the second back surface, the first guide groove penetrates part of the second active surface and part of the side surface of the second chip, and the bottom of the first guide groove is an inclined surface; the opening of the first guide groove facing the middle area is located on the extension line of the central axis of the gap between the two adjacent micro-protrusions.

[0024] In an optional embodiment, the second back side of the second chip includes a middle area and an edge area surrounding the middle area; a second guide groove is provided in the edge of the second back side of the second chip, and when the molding bottom filling process is performed to form the plastic encapsulation layer, the second guide groove is conducive to the flow and filling of the plastic encapsulation layer material.

[0025] In an optional embodiment, the second guide groove runs through part of the second back side and part of the side of the second chip, and the bottom of the second guide groove is an inclined surface; in the direction from the side of the second chip to the middle area of ​​the second back side, the size of the second guide groove remains unchanged or gradually decreases; the second guide groove in the edge area of ​​the second back side of the second chip in the lower layer is located directly below the first guide groove in the edge area of ​​the second edge surface of the second chip in the adjacent upper layer.

[0026] In an optional embodiment, a bonding layer is further provided between the edge regions of the second chip of the upper layer and the adjacent second chip of the lower layer, and the bonding layer is used for bonding and fixing the second chips of the upper and lower layers when the second chips are stacked.

[0027] Another embodiment of the present application further provides a stacked package structure, including: a substrate comprising opposing upper and lower surfaces; A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate; A chip stacking structure located on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second back side comprising a middle area and an edge area surrounding the middle area, the second active surface having a plurality of discrete micro-bumps, the edge area of ​​the second back side having a plurality of discrete second guide grooves, the middle area of ​​the second back side having a plurality of discrete second connection terminals, the second active surface of each second chip facing downward, the micro-bumps on the second active surface of the second chip of the upper layer in the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip of the adjacent lower layer, and the micro-bumps on the second active surface of the second chip of the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A plastic encapsulation layer covers the chip stacking structure and the first chip, and fills the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The second guide groove is conducive to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer.

[0028] The advantages of the technical solution of this application are: In the present application, the edge region of the second active surface of the second chip has a plurality of discrete first guide grooves. After stacking a plurality of the second chips in sequence on the first back side of the first chip in a vertical direction to form a chip stacking structure, a molding bottom filling process is performed to form a plastic layer covering the chip stacking structure and the first chip, and filling between the second chips of the upper and lower layers, between the second chip of the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The presence of the first guide groove increases the inflow channel of the plastic material at the edge of the chip stacking structure, so that the plastic layer material can easily flow to the middle region of the second chip through the first guide groove, and can be well filled between the second chips of the upper and lower layers, reducing the difficulty of filling the plastic layer material, and preventing defects such as gaps from being generated in the plastic layer formed between the second chips of the upper and lower layers. In addition, since the first guide groove is located at the edge region of the second active surface of the second chip, it will not affect the layout of the micro-protrusions in the middle region of the second active surface. Furthermore, after the plastic encapsulation layer is subsequently fixed, part of the plastic encapsulation layer is engaged in the first guide groove, that is, the first guide groove locks the plastic encapsulation layer, thereby improving the firmness of the plastic encapsulation layer. Furthermore, the first guide groove can be formed by an etching process, and the formation process is simple.

[0029] Furthermore, the edge region of the second back side of the second chip has a plurality of discrete second guide grooves. After the plurality of second chips are stacked in sequence on the first back side of the first chip in a vertical direction to form a chip stacking structure, a molding bottom filling process is performed to form a plastic layer covering the chip stacking structure and the first chip, and filling between the second chips of the upper and lower layers, between the second chip of the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The presence of the second guide groove increases the inflow channel of the plastic material at the edge of the chip stacking structure, so that the plastic layer material can easily flow to the middle region of the second chip through the second guide groove, and can be well filled between the second chips of the upper and lower layers, reducing the difficulty of filling the plastic layer material, and preventing defects such as gaps from being generated in the plastic layer formed between the second chips of the upper and lower layers. In addition, since the second guide groove is located at the edge region of the second back side of the second chip of the lower layer, it will not affect the layout of the micro-protrusions in the middle region of the second active surface of the second chip of the upper layer. Furthermore, after the plastic encapsulation layer is subsequently fixed, part of the plastic encapsulation layer is engaged in the second guide groove, that is, the second guide groove locks the plastic encapsulation layer, thereby improving the firmness of the plastic encapsulation layer. Furthermore, the second guide groove can be formed by an etching process, and the formation process is simple. Furthermore, the plurality of adjacent second guide grooves in the second back side edge region of the second chip of the lower layer serve as alignment marks when stacking the second chip of the upper layer on the second back side of the second chip of the lower layer, and there is no need to form alignment marks on the second back side of the second chip of the lower layer, thereby simplifying the manufacturing process. Furthermore, the second guide groove serving as the alignment mark is located in the second back side edge region of the second chip, and when the second chips of the upper layer are stacked, the alignment detection unit in the stacking device can more easily detect the alignment mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1-Figure 7 This is a structural schematic diagram of a stacked package structure forming process in one embodiment of the present application; Figure 8-Figure 13 This is a structural schematic diagram of a stacked package structure forming process in another embodiment of the present application; Figure 14-15 It is a structural schematic diagram of a stacked package structure forming process in yet another embodiment of the present application. DETAILED DESCRIPTION

[0031] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0032] On one hand, the present application provides a method for forming a stacked package structure. The formation process of the stacked package structure of the present application is described in detail below in some embodiments with reference to the accompanying drawings.

[0033] refer to Figure 1 , providing a substrate 101, wherein the substrate 101 includes a relative upper surface and a lower surface; providing a first chip 201, wherein the first chip 201 includes a relative first active surface and a first back surface, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connecting terminal 203, and the first active surface of the first chip 201 is mounted downward on the upper surface of the substrate 101, and the welding protrusion 202 is welded to the substrate 101.

[0034] The substrate 101 serves as a support carrier and a connection carrier in the packaging process. In one embodiment, the upper surface of the substrate 101 has a plurality of discrete first pads (not shown in the figure), the lower surface of the substrate 101 has a plurality of discrete second pads (not shown in the figure), and the substrate 101 has a connection circuit (not shown in the figure), and part of the connection circuit can be used for the electrical connection between the first pads on the upper surface of the substrate 101 and the corresponding second pads on the lower surface of the substrate 101, and part of the connection circuit can also be used for the electrical connection between some of the first pads on the upper surface of the substrate 101, and part of the connection circuit can also be used for the electrical connection between some of the second pads on the lower surface of the substrate 101. The first pads on the upper surface of the substrate 101 are electrically connected to the first chip 201 or other devices mounted on the substrate, and external protrusions can be formed on the second pads on the lower surface of the substrate later, and the external protrusions are used to connect with other devices or packaging structures. In one embodiment, the materials of the first pads, the second pads and the connection circuit are metals, which can be one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external protrusion is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium or tin-silver-antimony. In one embodiment, the substrate may be a silicon substrate, an RDL substrate (Re-distribution Layer), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate or a flexible circuit board (FPC). In one embodiment, the substrate may be a single-layer board or a multi-layer board. In one embodiment, the substrate 101 may be used as an interposer.

[0035] The first chip 201 includes a first active surface and a first back surface opposite to each other, the first active surface has a welding protrusion 202, the first back surface has a first connection terminal 203, the first connection terminal 203 includes a through silicon via interconnection structure (TSV, Through Silicon Via), or includes a through silicon via interconnection structure and a pad electrically connected to the through silicon via interconnection structure, an integrated circuit (with specific functions) (such as a logic control circuit, not shown in the figure) is formed in the first chip 201, and the welding protrusion 202 and the first connection terminal 203 are electrically connected to the integrated circuit. In one embodiment, the welding protrusion 202 can be a solder protrusion or include a metal bump and a solder layer located on the top surface of the metal bump. In a specific embodiment, the material of the first connecting terminal 203 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the metal bump is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the solder bump or solder layer is tin or a tin alloy; the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0036] The first chip 201 can function together with the subsequently stacked second chip 301 (refer to Figure 3 ) have the same or different functions. In one embodiment, the function of the first chip 201 may be different from the function of the second chip 301 stacked later. The first chip 201 is a logic chip, and the second chip 301 is a memory chip. The logic chip is used to control and manage the storage, reading (and deletion) of data in the memory chip. In other embodiments, the function of the first chip 201 may be different from the function of the second chip 301 stacked later (refer to Figure 3 ) have the same functions, and the first chip 201 and the second chip 301 are both storage chips.

[0037] In one embodiment, the memory chip includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), and resistive random access memory (RRAM). The logic chip includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), or other known electronic circuits used as processors.

[0038] In one embodiment, a third chip (not shown in the figure) is also mounted on the upper surface of the substrate 101 on one side of the first chip 201, and the third chip is electrically connected to the substrate 101. Specifically, the third chip can be electrically connected to the second chip 201 through some connecting lines in the substrate 101. The first chip 201 is a logic chip, the second chip 301 is a storage chip, and the third chip is a processing chip, which can be a CPU chip or a GPU chip.

[0039] Combined with reference Figure 2-Figure 5 ,in Figure 2 is a schematic diagram of the structure viewed from above from the second active surface of the second chip, Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 4 for Figure 2 Schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 5 for Figure 2 A schematic diagram of the cross-sectional structure along the cutting line CC1 direction provides a plurality of second chips 301, each of the second chips 301 includes a second active surface and a second back surface relative to each other, the second active surface includes a middle area 11 and an edge area 12 surrounding the middle area 11, the middle area of ​​the second active surface has a plurality of discrete micro-protrusions 302, the edge area of ​​the second active surface has a plurality of discrete first guide grooves 306, and the second back surface has a plurality of discrete second connection terminals 303.

[0040] The edge region of the second active surface of the second chip 301 has a plurality of discrete first guide grooves 306. Subsequently, a plurality of the second chips 301 are stacked in sequence on the first back surface of the first chip 201 in a vertical direction to form a chip stacking structure (refer to Figure 6 ), a molding bottom filling process is performed to form a plastic sealing layer 102 (reference Figure 7 ), the presence of the first guide groove 306 increases the inflow channel of the plastic encapsulation material at the edge of the chip stacking structure, so that the plastic encapsulation layer material can easily flow to the middle area of ​​the second chip 301 through the first guide groove 306, and can be well filled between the upper and lower second chips 301, reducing the difficulty of filling the plastic encapsulation layer material, and can prevent defects such as gaps from being generated in the plastic encapsulation layer formed between the upper and lower second chips. In addition, since the first guide groove 306 is located at the edge area of ​​the second active surface of the second chip 301, it will not affect the layout of the micro-protrusions 302 in the middle area of ​​the second active surface. In addition, after the plastic encapsulation layer 102 is subsequently fixed, part of the plastic encapsulation layer 102 is engaged in the first guide groove 306, that is, the first guide groove 306 locks the plastic encapsulation layer 102, thereby improving the firmness of the plastic encapsulation layer 102. In addition, the first guide groove 306 can be formed by an etching process, and the formation process is simple.

[0041] In one embodiment, in conjunction with reference Figure 1 and Figure 3 The second chip 301 also includes a side surface located between the second active surface and the second back surface. The first guide groove 306 runs through part of the second active surface and part of the side surface of the second chip 301. The bottom of the first guide groove 306 is an inclined surface. In a specific embodiment, the angle between the inclined surface and the second active surface is 30 degrees to 60 degrees, which is more conducive to the flow of the plastic encapsulation layer material from the first guide groove 306, reducing the resistance during the flow, and reducing the impact force of the inflowing plastic encapsulation layer material on the micro bump 302.

[0042] In one embodiment, continue to combine with reference Figure 1 and Figure 3In addition to the angle between the inclined surface and the second edged surface being 30 degrees to 60 degrees, the opening of the first guide groove 306 facing the middle area is located on the extension line of the central axis 21 of the gap between the two adjacent micro-protrusions 302, so that the plastic sealing layer material flowing in from the first guide groove 306 mainly flows into the middle area from the gap area between the adjacent micro-bumps 302, which is more conducive to the plastic sealing layer material flowing in from the first guide groove 306 and reducing the resistance during the inflow, while further reducing the impact force of the inflowing plastic sealing layer material on the micro-bumps 302, thereby preventing the micro-bumps 302 from loosening or falling off.

[0043] In one embodiment, in a direction from the side surface of the second chip 301 to the middle area of ​​the second active surface, the size of the first guiding groove 306 remains unchanged or gradually decreases.

[0044] The second active surface of the second chip 301 has a micro-bump 302, and the second back surface of the second chip 301 has a second connection terminal 303, the micro-bump 302 is a micro solder ball, and the second connection terminal 303 includes a through silicon via interconnection structure (TSV, Through Silicon Via), and an integrated circuit with a specific function (such as data storage, reading circuit, not shown in the figure) is formed in the second chip 301, and the second connection terminal 303 and the micro-bump 302 are electrically connected to the integrated circuit. In a specific embodiment, the material of the second connection terminal 303 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver, and the material of the micro-bump 302 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. It should be noted that, in some embodiments, the second chip 301 at the top layer in the chip stacking structure may have a second connection terminal 303 or a through silicon via (TSV) interconnection structure.

[0045] In one embodiment, the second active surface of the second chip 301 further has a pad and a passivation layer 305, and the micro-protrusion 302 is electrically connected to the pad and protrudes from the upper surface of the passivation layer 305. In one embodiment, the passivation layer 305 can be a single layer or a multi-layer stacked structure. The material of the passivation layer 305 can be an organic material and / or an inorganic material. The inorganic material is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, and the inorganic material is a high molecular polymer.

[0046] In one embodiment, the second chip 301 is a memory chip, and the memory chip includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), and resistive random access memory (RRAM).

[0047] refer to Figure 6 A chip stacking structure is formed on the first back side of the first chip 201, and the chip stacking structure includes a plurality of second chips 301 stacked in sequence along a vertical direction, with the second active side of each second chip 301 facing downward, and the micro-bumps 302 on the second active side of the second chip 301 in the upper layer of the chip stacking structure are welded together with the second connecting terminals 303 on the second back side of the adjacent second chip 301 in the lower layer, and the micro-bumps 302 on the second active side of the second chip 301 in the bottom layer are welded together with the first connecting terminals 203 on the first back side of the first chip 201.

[0048] In one embodiment, the process of forming a chip stacking structure on the first back side of the first chip 201 includes a pre-fixing process and a batch reflow process; the pre-fixing process is first performed to stack and pre-fix a plurality of second chips 301 in a vertical direction in sequence; the batch reflow process is performed to weld the micro-bumps 302 of the second active surface of the second chip 301 in the upper layer of the chip stacking structure to the second connection terminals 303 of the second back side of the adjacent lower layer of the second chip 301, and the micro-bumps 302 of the second active surface of the second chip 301 in the bottom layer are welded to the first connection terminals 203 of the first back side of the first chip 201. The pre-fixing is first performed to stack and fix a plurality of second chips 301, and then the batch reflow process is performed to achieve upper and lower layer welding of all chips in the stacking structure, thereby improving manufacturing efficiency.

[0049] In one embodiment, when the pre-fixing process is performed, the second chip 301 of the upper layer and the adjacent second chip 301 of the lower layer are pre-fixed by pre-soldering the corresponding second connecting terminal 203 with the flux in or on the surface of the micro-bump 302. When pre-fixed by flux, the micro-bump 302 and the corresponding second connecting terminal 203 are only preliminarily and weakly welded, and are not completely welded. When the batch reflow process is performed subsequently, the micro-bump 302 and the corresponding second connecting terminal 203 can be completely welded.

[0050] refer to Figure 7 , a molded underfill (MUF) process is performed to form a plastic encapsulation layer 102 that covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 on the bottom layer and the first chip 201, and between the first chip 201 and the upper surface of the substrate 101. The first guide groove 306 is conducive to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer 102.

[0051] In one embodiment, the material of the molding layer 102 is liquid epoxy molding compound (LMC). In other embodiments, the material of the molding layer 102 may also be other liquid resin molding compounds, such as liquid polyimide resin molding compounds, liquid benzocyclobutene resin molding compounds, or liquid polybenzoxazole resin molding compounds.

[0052] In one embodiment, the plastic encapsulation layer 102 may cover or expose the second back side of the second chip 301 of the top layer. In one embodiment, the plastic encapsulation layer 102 may also cover the first chip 201 and fill the space between the first chip 201 and the substrate 101 .

[0053] Another embodiment of the present application further provides a method for forming a stacked packaging structure (the main difference between this embodiment and the aforementioned embodiment is that: in this embodiment, the edge area of ​​the second back surface of the second chip has a plurality of discrete second guide grooves, and the edge area of ​​the second active surface of the second chip does not have the first guide groove, and the second guide groove is conducive to the flow of the plastic layer material when the plastic layer is formed. The parts in this embodiment that are the same or similar to those in the aforementioned embodiment are not repeated in this embodiment. For details, please refer to the definition or description of the corresponding parts in the aforementioned embodiment). For details, please refer to Figure 1 , Figure 8-Figure 13 ,in Figure 8 is a schematic diagram of the structure viewed from the bottom up from the second back side of the second chip, Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along the cutting line AA1. Fig.10 for Figure 8 Schematic diagram of the cross-sectional structure along the cutting line BB1. Fig.11 for Figure 8 A schematic diagram of a cross-sectional structure along a cutting line CC1, wherein the forming method comprises: refer to Figure 1, providing a substrate 101, the substrate 101 including an upper surface and a lower surface opposite to each other; providing a first chip 201, the first chip 201 including a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion 202, the first back surface having a first connecting terminal 203, the first active surface of the first chip 201 is mounted downward on the upper surface of the substrate 101, the welding protrusion 202 is welded to the substrate 101; refer to Figure 8-Figure 11 , providing a plurality of second chips 301, each of the second chips 301 comprises a second active surface and a second back surface opposite to each other, the second back surface comprises a middle area and an edge area surrounding the middle area, the second active surface has a plurality of discrete micro protrusions 302, the edge area of ​​the second back surface has a plurality of discrete second guide grooves 307, and the middle area of ​​the second back surface has a plurality of discrete second connection terminals 303; refer to Fig.12 , forming a chip stacking structure on the first back side of the first chip 201, the chip stacking structure comprising a plurality of second chips 301 stacked in sequence in a vertical direction, the second active side of each second chip 301 facing downward, the micro-bumps 302 on the second active side of the second chip 301 in the upper layer of the chip stacking structure being welded to the second connection terminals 303 on the second back side of the adjacent second chip 301 in the lower layer, and the micro-bumps 302 on the second active side of the second chip 301 in the bottom layer being welded to the first connection terminals 203 on the first back side of the first chip 201; refer to Fig.13 , a molded underfill (MUF) process is performed to form a plastic encapsulation layer 102 that covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 in the bottom layer and the first chip 201, and between the first chip 201 and the upper surface of the substrate 101. The second guide groove 307 is conducive to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer 102.

[0054] The edge region of the second back side of the second chip 301 has a plurality of discrete second guide grooves 307. Subsequently, a plurality of the second chips 301 are stacked in sequence on the first back side of the first chip 201 in a vertical direction to form a chip stacking structure (refer to Fig.12 ), a molding bottom filling process is performed to form a plastic sealing layer 102 (reference Fig.13 ), the presence of the second guide groove 307 increases the inflow channel of the plastic encapsulation material at the edge of the chip stacking structure, so that the plastic encapsulation layer material can easily flow to the middle area of ​​the second chip 301 through the second guide groove 307, and can be well filled between the upper and lower second chips 301, reducing the difficulty of filling the plastic encapsulation layer material, and can prevent defects such as gaps from being generated in the plastic encapsulation layer formed between the upper and lower second chips. In addition, since the second guide groove 307 is located at the edge area of ​​the second back side of the second chip 301 of the lower layer, it will not affect the layout of the micro-protrusions 302 in the middle area of ​​the second active surface of the upper second chip 301. In addition, after the plastic encapsulation layer 102 is subsequently fixed, part of the plastic encapsulation layer 102 is engaged in the second guide groove 307, that is, the second guide groove 307 locks the plastic encapsulation layer 102, thereby improving the firmness of the plastic encapsulation layer 102. In addition, the second guide groove 307 can be formed by an etching process, and the formation process is simple. Furthermore, the multiple adjacent second guide grooves 307 in the second back side edge region of the second chip 301 in the lower layer serve as alignment marks when stacking the second chip 301 in the upper layer on the second back side of the second chip 301 in the lower layer. There is no need to form alignment marks on the second back side of the second chip 301 in the lower layer, thereby simplifying the manufacturing process. Furthermore, the second guide grooves 307 serving as alignment marks are located in the second back side edge region of the second chip 301. When the second chips 301 in the upper layer are stacked, the alignment detection unit in the stacking device can more easily detect the alignment marks.

[0055] In one embodiment, the second guide groove 307 penetrates part of the second back surface and part of the side surface of the second chip 301, and the bottom of the second guide groove 307 is an inclined surface (refer to Figure 8 and Fig. 9 ), the angle between the inclined surface and the second back surface is 30 degrees to 60 degrees, which is more conducive to the plastic encapsulation layer material flowing into the first guide groove 306, reducing the resistance during the inflow, and reducing the impact force of the inflowing plastic encapsulation layer material on the micro bump 302.

[0056] In one embodiment, in a direction from the side surface of the second chip 301 to the middle area of ​​the second back surface, the size of the second guiding groove 307 remains unchanged or gradually decreases.

[0057] In one embodiment, continue to combine with reference Figure 1 and Figure 3In addition to the angle between the inclined surface of the second chip 301 and the second edged surface being 30 degrees to 60 degrees, the second guide groove 307 of the second back edge area of ​​the lower second chip 301 is located on the extension line of the central axis 21 of the gap between the two adjacent micro-bumps 302 of the upper second chip 301, so that the plastic encapsulation layer material flowing in from the second guide groove 307 mainly flows into the middle area from the gap area between the adjacent micro-bumps 302 of the upper second chip 301, which is more conducive to the plastic encapsulation layer material flowing in from the second guide groove 307 and reducing the resistance during the inflow, while further reducing the impact force of the inflow plastic encapsulation layer material on the micro-bumps 302 on the second active surface of the upper second chip 301, thereby preventing the micro-bumps 302 of the upper second chip 301 from loosening or falling off.

[0058] Another embodiment of the present application further provides a method for forming a stacked package structure, referring to Fig.14 and Fig.15 The main difference between this embodiment and the previous embodiment is that: the second chip 301 not only has a plurality of discrete first guide grooves 306 at the edge area of ​​the second active surface, but also has a plurality of discrete second guide grooves 307 at the edge area of ​​the second back surface of the second chip. When forming the plastic layer 102, the first guide grooves 306 and the second guide grooves 307 simultaneously guide the plastic layer material, which is beneficial to the flow of the plastic layer material when forming the plastic layer, so that the plastic layer material can flow more easily to the middle area of ​​the second chip 301, and can be better filled between the upper and lower second chips 301, further reducing the difficulty of filling the plastic layer material, and can better prevent the formation of defects such as gaps in the plastic layer formed between the upper and lower second chips. (It should be noted that the same or similar parts in this embodiment and the previous embodiment are not repeated in this embodiment. Please refer to the definition or description of the corresponding parts in the previous embodiment for details).

[0059] In one embodiment, the opening of the first guide groove 306 facing the middle area is located on the extension line of the central axis 21 of the gap between the two adjacent micro-bumps 302, and the second guide groove 307 in the second back edge area of ​​the second chip 301 of the lower layer is located directly below the first guide groove 306 in the second edge area of ​​the second edge surface of the adjacent upper second chip 301, so that the plastic encapsulation layer material flowing in from the first guide groove 306 mainly flows into the middle area from the gap area between the adjacent micro-bumps 302, which is more conducive to the plastic encapsulation layer material flowing in from the first guide groove 306 and the second guide groove 307, while reducing the resistance during the inflow, and further reducing the impact force of the inflowing plastic encapsulation layer material on the micro-bumps 302, thereby preventing the micro-bumps 302 from loosening or falling off.

[0060] In one embodiment, when stacking the second chips, the plurality of adjacent second guide grooves 307 in the second back side edge region of the lower second chip 301 serve as alignment marks when stacking the upper second chip 301 on the second back side of the lower second chip 301.

[0061] On the other hand, the present application also provides a stacked package structure. In one embodiment, Figure 7 , and combined with reference Figure 2-Figure 5 , the stacked package structure comprises: A substrate 101, wherein the substrate 101 includes an upper surface and a lower surface opposite to each other; A first chip 201, wherein the first chip 201 comprises a first active surface and a first back surface opposite to each other, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connection terminal 203, and the first active surface of the first chip 201 is mounted on the upper surface of the substrate 101 with the first active surface facing downward, and the welding protrusion 202 is welded to the substrate 101; A chip stacking structure located on the first back side of the first chip 201, the chip stacking structure comprising a plurality of second chips 301 stacked in sequence in a vertical direction, each of the second chips 301 comprising a second active surface and a second back side opposite to each other, the second active surface comprising a middle area and an edge area surrounding the middle area, the middle area of ​​the second active surface having a plurality of discrete micro-bumps 302, the edge area of ​​the second active surface having a plurality of discrete first guide grooves 306, the second back side having a plurality of discrete second connection terminals 303, the second active surface of each second chip 301 facing downward, the micro-bumps 302 on the second active surface of the second chip 301 of the upper layer in the chip stacking structure being welded together with the second connection terminals 303 on the second back side of the adjacent second chip 301 of the lower layer, and the micro-bumps 302 on the second active surface of the second chip 301 of the bottom layer being welded together with the first connection terminals 203 on the first back side of the first chip 201; The first guide channel 306 is a plastic encapsulation layer 102 that covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 in the bottom layer and the first chip 201, and between the first chip 201 and the upper surface of the substrate 101. When the plastic encapsulation layer 102 is formed, it is beneficial to the flow and filling of the plastic encapsulation layer material.

[0062] In one embodiment, the first guide groove 306 runs through part of the second active surface and part of the side surface of the second chip 301, and the bottom of the first guide groove 306 is an inclined surface. In a specific embodiment, the angle between the inclined surface and the second active surface is 30 degrees to 60 degrees. The opening of the first guide groove 306 facing the middle area is located on the extension line of the central axis 21 of the gap between the two adjacent micro-protrusions 302.

[0063] In one embodiment, in a direction from the side surface of the second chip 301 to the middle area of ​​the second active surface, the size of the first guide groove 301 remains unchanged or gradually decreases.

[0064] In one embodiment, the second chip 301 further includes a side surface between the second active surface and the second back surface, the first guide groove 306 runs through part of the second active surface and part of the side surface of the second chip 301, and the bottom of the first guide groove 306 is an inclined surface (refer to Figure 3 The opening of the first guide groove 306 facing the middle area is located at the extension line 21 of the central axis of the gap between the two adjacent micro-protrusions 302 (reference Figure 2 )superior.

[0065] In one embodiment, the second back side of the second chip 301 includes a middle area and an edge area surrounding the middle area; the edge of the second back side of the second chip 301 has a second guide groove 307 (refer to Fig.14 and Fig.15 ), when a molding bottom filling process is performed to form the plastic encapsulation layer, the second guide groove 307 is conducive to the flow and filling of the plastic encapsulation layer material.

[0066] In one embodiment, the second guide groove 307 runs through part of the second back side and part of the side of the second chip 301, and the bottom of the second guide groove 307 is an inclined surface; in the direction from the side of the second chip 301 to the middle area of ​​the second back side, the size of the second guide groove 307 remains unchanged or gradually decreases; the second guide groove 307 in the second back side edge area of ​​the second chip 301 in the lower layer is located directly below the first guide groove 306 in the second edge area of ​​the second edge surface of the second chip 301 in the adjacent upper layer.

[0067] Another embodiment of the present application further provides a stacked package structure. Fig.13 , and combined with reference Figure 8-Figure 11 ,include: A substrate 101, wherein the substrate 101 includes an upper surface and a lower surface opposite to each other; A first chip 201, wherein the first chip 201 comprises a first active surface and a first back surface opposite to each other, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connection terminal 203, and the first active surface of the first chip 201 is mounted on the upper surface of the substrate 101 with the first active surface facing downward, and the welding protrusion 202 is welded to the substrate 101; A chip stacking structure located on the first back side of the first chip 201, the chip stacking structure comprising a plurality of second chips 301 stacked in sequence in a vertical direction, each of the second chips 301 comprising a second active surface and a second back side opposite to each other, the second back side comprising a middle area and an edge area surrounding the middle area, the second active surface having a plurality of discrete micro-bumps 302, the edge area of ​​the second back side having a plurality of discrete second guide grooves 307, the middle area of ​​the second back side having a plurality of discrete second connection terminals 303, the second active surface of each second chip 301 facing downward, the micro-bumps 302 on the second active surface of the second chip 301 of the upper layer in the chip stacking structure being welded together with the second connection terminals 303 on the second back side of the adjacent second chip 301 of the lower layer, and the micro-bumps 302 on the second active surface of the second chip 301 of the bottom layer being welded together with the first connection terminals 203 on the first back side of the first chip; The plastic encapsulation layer 102 covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 in the bottom layer and the first chip 201, and between the first chip 201 and the upper surface of the substrate 101. The second guide groove 307 is beneficial to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer 102.

[0068] It should be noted that the parts in the embodiment of the aforementioned packaging structure that are the same or similar to those in the embodiment of the aforementioned method for forming the packaging structure will not be repeated in the embodiment of the packaging structure. Please refer to the limitations or descriptions of the corresponding parts in the embodiment of the method for forming the aforementioned packaging structure for details.

[0069] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a stacked package structure, characterized in that: include: providing a substrate, the substrate comprising opposing upper and lower surfaces; Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate; Providing a plurality of second chips, each of the second chips comprising a second active surface and a second back surface opposite to each other, the second active surface comprising a middle area and an edge area surrounding the middle area, the middle area of ​​the second active surface having a plurality of discrete micro protrusions, the edge area of ​​the second active surface having a plurality of discrete first guide grooves, and the second back surface having a plurality of discrete second connection terminals; forming a chip stacking structure on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, the second active side of each second chip facing downward, the micro-bumps on the second active side of the second chip in the upper layer of the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip in the adjacent lower layer, and the micro-bumps on the second active side of the second chip in the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A molding bottom filling process is performed to form a plastic layer that covers the chip stacking structure and the first chip, and fills between the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The first guide groove is conducive to the flow and filling of the plastic layer material when forming the plastic layer.

2. The method for forming a stacked package structure according to claim 1, wherein: The second chip further includes a side surface between the second active surface and the second back surface, the first guide groove runs through part of the second active surface and part of the side surface of the second chip, and the bottom of the first guide groove is an inclined surface.

3. The method for forming a stacked package structure according to claim 2, wherein: The opening of the first guide groove facing the middle area is located on the extension line of the central axis of the gap between the two adjacent micro-protrusions; the angle between the inclined surface and the second edged surface is 30 degrees to 60 degrees.

4. The method for forming a stacked package structure according to claim 2 or 3, wherein: In a direction from the side surface of the second chip to the middle area of ​​the second active surface, the size of the first guiding groove remains unchanged or gradually decreases.

5. The method for forming a stacked package structure according to claim 1 or 2, wherein: The second back side of the second chip includes a middle area and an edge area surrounding the middle area, and a plurality of discrete second connection terminals are located in the middle area of ​​the second back side; a second guide groove is provided in the edge of the second back side of the second chip, and when the molding bottom filling process is performed to form the plastic encapsulation layer, the second guide groove is conducive to the flow and filling of the plastic encapsulation layer material.

6. The method for forming a stacked package structure according to claim 5, wherein: The second guide groove runs through part of the second back side and part of the side of the second chip, and the bottom of the second guide groove is an inclined surface; in the direction from the side of the second chip to the middle area of ​​the second back side, the size of the second guide groove remains unchanged or gradually decreases.

7. The method for forming a stacked package structure according to claim 6, wherein: The second guide groove in the second back side edge region of the second chip in the lower layer is located directly below the first guide groove in the second active side edge region of the second chip in the adjacent upper layer.

8. The method for forming a package-on-package structure according to claim 6, wherein: The plurality of adjacent second guide grooves in the second back side edge region of the second chip of the lower layer serve as alignment marks when the second chip of the upper layer is stacked on the second back side of the second chip of the lower layer.

9. The method for forming a package-on-package structure according to claim 6, wherein: The first guide groove and the second guide groove are formed by an etching process.

10. The method for forming a package-on-package structure according to claim 1, wherein: The process of forming a chip stacking structure on the first back side of the first chip includes a pre-fixing process and a batch reflow process; the pre-fixing process is first performed to stack and pre-fix a plurality of the second chips in sequence in a vertical direction; and the batch reflow process is performed to weld the micro-bumps on the second active surface of the second chip in the upper layer of the chip stacking structure to the second connecting terminal on the second back side of the adjacent second chip in the lower layer, and the micro-bumps on the second active surface of the second chip in the bottom layer to the first connecting terminal on the first back side of the first chip.

11. The method for forming a package-on-package structure according to claim 10, wherein: When the pre-fixing process is performed, the second chip of the upper layer and the second chip of the adjacent lower layer are pre-fixed by pre-soldering the corresponding second connecting terminals through the soldering flux in or on the surface of the micro-bumps.

12. The method for forming a package-on-package structure according to claim 10, wherein: During the pre-fixing process, the upper second chip and the adjacent lower second chip are bonded and fixed via a bonding layer located in an edge region between the upper second chip and the lower second chip to achieve the pre-fixing.

13. The method for forming a package-on-package structure according to claim 12, wherein: The bonding layer is a temporary bonding layer or a mechanical bonding layer. The temporary bonding layer is decomposed during a batch reflow process, and the mechanical bonding layer is not decomposed during the mechanical bonding process and remains in the stacked package structure.

14. A method for forming a stacked package structure, characterized in that: include: providing a substrate, the substrate comprising opposing upper and lower surfaces; Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate; Providing a plurality of second chips, each of the second chips comprising a second active surface and a second back surface opposite to each other, the second back surface comprising a middle area and an edge area surrounding the middle area, the second active surface having a plurality of discrete micro-protrusions, the edge area of ​​the second back surface having a plurality of discrete second guide grooves, and the middle area of ​​the second back surface having a plurality of discrete second connection terminals; forming a chip stacking structure on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, the second active side of each second chip facing downward, the micro-bumps on the second active side of the second chip in the upper layer of the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip in the adjacent lower layer, and the micro-bumps on the second active side of the second chip in the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A molding bottom filling process is performed to form a plastic layer that covers the chip stacking structure and the first chip, and fills between the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The second guide groove is conducive to the flow and filling of the plastic layer material when forming the plastic layer.

15. A stacked package structure, characterized in that: include: a substrate comprising opposing upper and lower surfaces; A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate; A chip stacking structure located on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface comprising a middle area and an edge area surrounding the middle area, the middle area of ​​the second active surface having a plurality of discrete micro-bumps, the edge area of ​​the second active surface having a plurality of discrete first guide grooves, the second back side having a plurality of discrete second connection terminals, the second active surface of each second chip facing downward, the micro-bumps on the second active surface of the second chip of the upper layer in the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip of the adjacent lower layer, and the micro-bumps on the second active surface of the second chip of the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A plastic encapsulation layer covers the chip stacking structure and the first chip, and fills the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The first guide groove is conducive to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer.

16. The package-on-package structure according to claim 15, wherein: Also includes: The second chip further includes a side surface between the second active surface and the second back surface, the first guide groove runs through part of the second active surface and part of the side surface of the second chip, and the bottom of the first guide groove is an inclined surface; The opening of the first guide groove facing the middle area is located on the extension line of the central axis of the gap between the two adjacent micro-protrusions.

17. The package-on-package structure according to claim 15 or 16, wherein: The second back side of the second chip includes a middle area and an edge area surrounding the middle area; a second guide groove is provided in the edge of the second back side of the second chip, and when the molding bottom filling process is performed to form the plastic encapsulation layer, the second guide groove is conducive to the flow and filling of the plastic encapsulation layer material.

18. The package-on-package structure according to claim 17, wherein: The second guide groove runs through part of the second back side and part of the side of the second chip, and the bottom of the second guide groove is an inclined surface; in the direction from the side of the second chip to the middle area of ​​the second back side, the size of the second guide groove remains unchanged or gradually decreases; the second guide groove in the edge area of ​​the second back side of the second chip in the lower layer is located directly below the first guide groove in the edge area of ​​the second edge surface of the second chip in the adjacent upper layer.

19. The package-on-package structure according to claim 15, wherein: A bonding layer is also provided between the edge regions of the second chip of the upper layer and the adjacent second chip of the lower layer, and the bonding layer is used for bonding and fixing the second chips of the upper and lower layers when the second chips are stacked.

20. A stacked package structure, characterized in that: include: a substrate comprising opposing upper and lower surfaces; A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate; A chip stacking structure located on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second back side comprising a middle area and an edge area surrounding the middle area, the second active surface having a plurality of discrete micro-bumps, the edge area of ​​the second back side having a plurality of discrete second guide grooves, the middle area of ​​the second back side having a plurality of discrete second connection terminals, the second active surface of each second chip facing downward, the micro-bumps on the second active surface of the second chip of the upper layer in the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip of the adjacent lower layer, and the micro-bumps on the second active surface of the second chip of the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A plastic encapsulation layer covers the chip stacking structure and the first chip, and fills the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The second guide groove is conducive to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer.

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