Switched capacitor circuit and pipeline analog-to-digital converter including same

Abstract

The invention relates to a switched capacitor circuit and a pipeline type analog-to-digital converter comprising the same. A switched capacitor circuit includes a sampling capacitor array, a charge transfer circuit and a control circuit. The sampling capacitor array is used for sampling an input voltage in a sampling stage. The charge transfer circuit includes a first current source and a second current source having different current-voltage characteristics, and the first current source and the second current source are coupled to the output terminal. The control circuit is used for adjusting a sampling result of the sampling capacitor array according to the input voltage in a preset stage so as to generate an adjusted voltage. The control circuit is further used for starting one of the first current source and the second current source according to the input voltage in the charge transfer stage, so that the charge transfer circuit amplifies the adjusted voltage in the charge transfer stage to generate the output voltage at the output end.

Description

Technical Field

[0001] The present disclosure relates to a switched capacitor circuit and a pipelined analog-to-digital converter including the same, and more particularly to a switched capacitor circuit for reducing output current error and a pipelined analog-to-digital converter including the same. Background Art

[0002] The operation of the switched capacitor circuit can be roughly divided into the sampling stage and the charge transfer stage. In the sampling stage, the switched capacitor circuit uses a capacitor to store the difference between the input voltage and the common voltage. Then, in the charge transfer stage, the switched capacitor circuit uses a charge pump to generate a corresponding output voltage at the output end based on the sampling result. Before the charge transfer stage, a preset voltage is used to reset the output end to clear the output voltage of the previous operation. When the output voltage is low, the charge pump will operate at a higher cross-voltage accordingly. Conversely, when the output voltage is high, the cross-voltage of the charge pump is low. Due to the channel effect, the output current of the charge pump will vary under different cross-voltages, thereby reducing the accuracy of the switched capacitor circuit. Summary of the invention

[0003] The disclosed document provides a switching capacitor circuit, which includes a first sampling capacitor array, a charge transfer circuit and a control circuit. The first sampling capacitor array is used to sample a first input voltage in a sampling phase. The charge transfer circuit includes a first current source and a second current source having different current-voltage characteristics, and the first current source and the second current source are coupled to a first output terminal. The control circuit is used to adjust the sampling result of the first sampling capacitor array according to the first input voltage in a preset phase to generate a first adjusted voltage. The control circuit is also used to enable one of the first current source and the second current source according to the first input voltage in a charge transfer phase, so that the charge transfer circuit amplifies the first adjusted voltage in the charge transfer phase to generate a first output voltage at the first output terminal.

[0004] The disclosed document provides a switching capacitor circuit, which includes a first sampling capacitor array, a charge transfer circuit and a control circuit. The first sampling capacitor array is used to sample a first input voltage in a sampling phase. The charge transfer circuit also includes a first current source and a second current source having different current-voltage characteristics, and the first current source and the second current source are coupled to a first output terminal. The control circuit is used to couple a first reference voltage to a sampling result of the first sampling capacitor array in a preset phase to generate a first adjusted voltage. The control circuit is also used to determine the magnitude of the first reference voltage and select one of the first current source and the second current source to be enabled in the charge transfer phase according to the relationship between a plurality of voltage thresholds and the first input voltage, so that the charge transfer circuit amplifies the first adjusted voltage in the charge transfer phase to generate a first output voltage at the first output terminal.

[0005] The disclosure document provides a pipeline analog-to-digital converter, which includes a plurality of converter circuit systems. Each converter circuit system includes a first sampling capacitor array, a charge transfer circuit, and a control circuit. The first sampling capacitor array is used to sample a first input voltage in a sampling phase. The charge transfer circuit also includes a first current source and a second current source having different current-voltage characteristics, and the first current source and the second current source are coupled to a first output terminal. The control circuit is used to adjust the sampling result of the first sampling capacitor array according to the first input voltage in a preset phase to generate a first adjusted voltage. The control circuit is also used to enable one of the first current source and the second current source according to the first input voltage in a charge transfer phase, so that the charge transfer circuit amplifies the first adjusted voltage in the charge transfer phase to generate a first output voltage at a first output terminal.

[0006] One of the advantages of the above-mentioned switched capacitor circuit and pipeline analog-to-digital converter is that they have high linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a simplified functional block diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0008] Figure 2A FIG. 4 is a circuit diagram of a charge pump according to an embodiment of the present disclosure.

[0009] Figure 2B FIG. 4 is a circuit diagram of a charge pump according to an embodiment of the present disclosure.

[0010] Figure 3A FIG. 4 is a circuit diagram of a current source according to an embodiment of the present disclosure.

[0011] Figure 3B FIG. 4 is a circuit diagram of a current source according to an embodiment of the present disclosure.

[0012] Figure 4 FIG. 4 is a waveform diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0013] Figure 5 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit according to an embodiment of the present disclosure.

[0014] Figure 6 FIG. 4 is a schematic diagram of current-voltage characteristics of a current source according to an embodiment of the present disclosure.

[0015] Figure 7 FIG. 4 is a simplified functional block diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0016] Figure 8 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit according to an embodiment of the present disclosure.

[0017] Fig. 9 FIG. 4 is a simplified functional block diagram of a pipelined analog-to-digital converter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0019] Figure 1 The figure is a simplified functional block diagram of a switched capacitor circuit 100 according to an embodiment of the present disclosure. In some embodiments, the switched capacitor circuit 100 can be used as one of the multiple stages of a pipelined analog-to-digital converter (pipelined ADC). The switched capacitor circuit 100 includes a plurality of sampling capacitor arrays 110a-110b, a control circuit 120, and a charge transfer circuit 130. The switched capacitor circuit 100 is used to adjust the differential input voltages VIP and VIN to adjusted voltages VDP and VDN with smaller amplitudes, and to amplify the adjusted voltages VDP and VDN to differential output voltages VOP and VON to avoid dynamic distortion in the subsequent circuit (e.g., the next stage of the pipelined analog-to-digital converter).

[0020] The sampling capacitor array 110a is used to sample the input voltage VIP of the input terminal INP. In some embodiments, the sampling capacitor array 110a includes capacitors C1-C2, wherein the first ends of the capacitors C1-C2 are each coupled to the input terminal INP through a switch, and the second ends of the capacitors C1-C2 are coupled to the charge transfer circuit 130. The sampling capacitor array 110b is used to sample the input voltage VIN of the input terminal INN. In some embodiments, the sampling capacitor array 110b includes capacitors C3-C4, wherein the first ends of the capacitors C3-C4 are each coupled to the input terminal INN through a switch, and the second ends of the capacitors C3-C4 are coupled to the charge transfer circuit 130.

[0021] In some embodiments, the control circuit 120 includes an analog-to-digital converter 122 and a decoder 124. The analog-to-digital converter 122 is coupled to the input terminals INP and INN, and is used to generate a digital code Bi according to the input voltages VIP and VIN. The decoder 124 is coupled to the analog-to-digital converter 122, and is used to generate reference voltages VREP and VREN according to the digital code Bi. The reference voltages VREP and VREN are used to couple to the sampling capacitor arrays 110a and 110b, respectively, to adjust the input voltages VIP and VIN sampled by the sampling capacitor arrays 110a and 110b, thereby generating adjusted voltages VDP and VDN. In some embodiments, the decoder 124 includes a digital-to-analog converter.

[0022] The charge transfer circuit 130 includes a comparator 132, charge pumps 134a-134b, and feedback paths 136a-136b. A first input terminal (e.g., a non-inverting input terminal) of the comparator 132 is coupled to the second terminals of the capacitors C1-C2 to receive the adjusted voltage VDP. A second input terminal (e.g., an inverting input terminal) of the comparator 132 is coupled to the second terminals of the capacitors C3-C4 to receive the adjusted voltage VDN. The comparator 132 is used to generate control signals E1 and E2 according to the adjusted voltages VDP and VDN, so as to control the charge pumps 134a-134b respectively using the control signals E1 and E2. For example, when the adjusted voltages VDP and VDN are different, the comparator 132 uses the control signals E1 and E2 to enable the charge pumps 134a-134b. For another example, when the adjusted voltages VDP and VDN are the same, the comparator 132 uses the control signals E1 and E2 to disable the charge pumps 134a-134b.

[0023] The enabled charge pumps 134a-134b are used to charge the output terminal OUP and discharge the output terminal OUN, respectively, to generate output voltages VOP and VON at the output terminals OUP and OUN, respectively. In addition, the decoder 124 is also used to generate selection signals S1 and S2 according to the digital code Bi, to control the current-voltage characteristics of the charge pumps 134a-134b, respectively.

[0024] Figure 2A 1 is a circuit diagram of a charge pump 134a according to an embodiment of the present disclosure. The charge pump 134a includes a plurality of current sources I1 and I2 and a plurality of switches SW1 to SW4. The current source I1, the switch SW1, and the switch SW3 are coupled in series between the high operating voltage VDD and the output terminal OUP. The current source I2, the switch SW2, and the switch SW4 are coupled in series between the high operating voltage VDD and the output terminal OUP. The selection signal S1 includes sub-selection signals S11 and S12, and the sub-selection signals S11 and S12 are used to control the switches SW1 and SW2, respectively. The switches SW3 and SW4 are controlled by the control signal E1.

[0025] Figure 2B 1 is a circuit diagram of a charge pump 134b according to an embodiment of the present disclosure. The charge pump 134b includes a plurality of current sources I3 and I4 and a plurality of switches SW5 to SW8. The current source I3, the switch SW5, and the switch SW7 are coupled in series between the low operating voltage VSS and the output terminal OUN. The current source I4, the switch SW6, and the switch SW8 are coupled in series between the low operating voltage VSS and the output terminal OUN. The selection signal S2 includes sub-selection signals S21 and S22, and the sub-selection signals S21 and S22 are used to control the switches SW5 and SW6, respectively. The switches SW7 and SW8 are controlled by the control signal E2.

[0026] In some embodiments, the current sources I1 and I2 have different current-voltage characteristics and / or different structures, and the current sources I3 and I4 have different current-voltage characteristics and / or different structures. In some embodiments, the output currents of the current sources I1 to I4 are approximately the same, that is, the error of the output currents of the current sources I1 to I4 can be within 20%, preferably within 10%, and more preferably within 5%. In some embodiments, the current source I3 is Figure 3A The N-type transistor basic current mirror shown, and the current source I4 is Figure 3B The current sources I1 and I2 are also a basic current mirror and a cascade current mirror respectively, the difference is that the current sources I1 and I2 are implemented by P-type transistors, which are not repeated here for the sake of brevity.

[0027] Figure 4 Schematic diagram of waveforms of a switching capacitor circuit 100 according to an embodiment of the present disclosure document. In the present disclosure document, the enable level and the disable level of the signal are used to turn on and off the corresponding switch, respectively. First, in the sampling stage, the switching signal Φ1 is the enable level, and the switching signal Φ2, the preset signal P and the control signal E1~E2 are the disable levels. The first end of the capacitor C1~C2 is connected to the input terminal INP to receive (sample) the input voltage VIP. The first end of the capacitor C3~C4 is connected to the input terminal INN to receive (sample) the input voltage VIN. In addition, the second end of the capacitor C1~C4, the first input terminal of the comparator 132 and the second input terminal of the comparator 132 all receive a common voltage Vcm.

[0028] In the conversion phase, the switching signals Φ1-Φ2, the preset signal P, and the control signals E1-E2 are all at the disabled level. The decoder 124 will (1) determine the magnitude of the reference voltages VREP and VREN, (2) select one of the current sources I1 and I2 to be enabled in the charge transfer phase described later, and (3) select one of the current sources I3 and I4 to be enabled in the charge transfer phase described later, according to the input voltages VIN and VIP.

[0029] Please refer to Figure 5 ,in Figure 5 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit 100 according to an embodiment of the present disclosure. Figure 5 The vertical axis is the difference between the output voltage VOP and the output voltage VON, and the horizontal axis is the difference between the input voltage VIP and the input voltage VIN (hereinafter referred to as “input voltage difference Vdif”). In some embodiments, the analog-to-digital converter 122 includes a plurality of comparators (not shown), which correspond to Figure 5The voltage thresholds T1 to T13 are arranged in order from small to large. The voltage thresholds T1 to T13 define a plurality of voltage ranges A1 to A14. The number of the voltage thresholds T1 to T13 is only an example, and the disclosure document is not limited thereto.

[0030] The analog-to-digital converter 122 is used to use a plurality of comparators to compare the input voltage difference Vdif with the voltage thresholds T1 to T13. Therefore, the analog-to-digital converter 122 can determine the voltage range including the input voltage difference Vdif from the voltage ranges A1 to A14, and output a digital code Bi representing the voltage range. For example, when the input voltage difference Vdif is within the voltage range A1, the digital code Bi output by the analog-to-digital converter 122 is 0001; when the input voltage difference Vdif is within the voltage range A2, the digital code Bi output by the analog-to-digital converter 122 is 0010, and so on.

[0031] When the input voltage difference Vdif is in a voltage range indicated by an odd number (e.g., voltage range A1, A3, etc.), it means that after the charge transfer stage described later is over, the output voltage VOP is less than the output voltage VON. For example, the output voltage VOP is less than the common voltage Vcm (e.g., 0.5V), and the output voltage VON is greater than or equal to the common voltage Vcm. In this case, the decoder 124 determines that the current sources I1 and I3 need to be enabled in the charge transfer stage (i.e., the switches SW1 and SW5 need to be turned on), and the current sources I2 and I4 need to be disabled in the charge transfer stage (i.e., the switches SW2 and SW6 need to be turned off) according to the digital code Bi.

[0032] On the other hand, when the input voltage difference Vdif is in a voltage range indicated by an even number (e.g., voltage range A2, A4, etc.), it means that after the charge transfer stage described later is over, the output voltage VOP is greater than the output voltage VON. For example, the output voltage VOP is greater than or equal to the common voltage Vcm, and the output voltage VON is less than the common voltage Vcm. In this case, the decoder 124 determines that the current sources I2 and I4 need to be enabled in the charge transfer stage (i.e., the switches SW2 and SW6 need to be turned on), and the current sources I1 and I3 need to be disabled in the charge transfer stage (i.e., the switches SW1 and SW5 need to be turned off) according to the digital code Bi.

[0033] In other words, when the input voltage difference Vdif is in the Mth voltage range of the voltage range A1-A14 and the output voltage VOP is less than the output voltage VON, the decoder 124 enables the current sources I1 and I3 in the charge transfer stage. When the input voltage difference Vdif is in the M+1th voltage range of the voltage range A1-A14 and the output voltage VOP is greater than the output voltage VON, the decoder 124 enables the current sources I2 and I4 in the charge transfer stage, where M is a positive integer.

[0034] In other words, when the input voltage difference Vdif is adjacent to the Jth voltage threshold (e.g., the first voltage threshold T1) among the voltage thresholds T1 to T13 and is less than the Jth voltage threshold, it means that after the charge transfer stage described later ends, the output voltage VOP is less than the output voltage VON. In this case, the decoder 124 enables the current sources I1 and I3 in the charge transfer stage, where J is an odd number. When the input voltage difference Vdif is adjacent to the Jth voltage threshold and is greater than or equal to the Jth voltage threshold, it means that after the charge transfer stage described later ends, the output voltage VOP is greater than the output voltage VON. In this case, the decoder 124 enables the current sources I2 and I4 in the charge transfer stage.

[0035] In summary, the decoder 124 is used to determine whether the input voltage difference Vdif is within the voltage range A1-A14 according to the digital code Bi, and determine the working state (ie, enabled or disabled) of each of the current sources I1-I4 in the charge transfer phase according to the determination result.

[0036] In addition, the decoder 124 is used to determine which of the voltage ranges B1 to B7 the input voltage difference Vdif is located in according to the digital code Bi, and determine the magnitudes of the reference voltages VREP and VREN according to the determination result. The voltage range B1 is composed of the voltage ranges A1 and A2; the voltage range B2 is composed of the voltage ranges A3 and A4, and so on.

[0037] In some embodiments, the relationship between the reference voltages VREP and VREN, the input voltage difference Vdif, and the voltage ranges B1 to B7 is shown in Table 1 below.

[0038] Table 1

[0039] Voltage range Reference voltage VREP Reference voltage VREN B1 0V 1V B2 0V (2 / 3)V B3 0V (1 / 3)V B4 0V 0V B5 (1 / 3)V 0V B6 (2 / 3)V 0V B7 1V 0V

[0040] Next, in the preset stage, the switch signal Φ2, the preset signal P and the control signals E1-E2 are at the enable level, and the switch signal Φ1 is at the disable level. In this stage, the control circuit 120 is used to output a reference voltage VREP related to the magnitude of the input voltage VIP to the sampling capacitor array 110a, so as to adjust the input voltage VIP sampled by the sampling capacitor array 110a according to the magnitude of the input voltage VIP, thereby generating an adjusted voltage VDP. The control circuit 120 is also used to output a reference voltage VREN related to the magnitude of the input voltage VIN to the sampling capacitor array 110b, so as to adjust the input voltage VIN sampled by the sampling capacitor array 110b according to the magnitude of the input voltage VIN, thereby generating an adjusted voltage VDN.

[0041] In detail, in the preset stage, the comparator 132 forms a closed loop with the output terminals OUP and OUN, and the control circuit 120 couples the reference voltages VREP and VREN to the first terminal of the capacitor C2 and the first terminal of the capacitor C4 (i.e., coupled to the input voltage VIP sampled by the sampling capacitor array 110a, and coupled to the input voltage VIN sampled by the sampling capacitor array 110b) via the switch. Thereby, the input voltage VIP sampled by the capacitors C1 and C2 is adjusted to the adjusted voltage VDP, and the input voltage VIN sampled by the capacitors C3 and C4 is adjusted to the adjusted voltage VDN. In addition, the charge transfer circuit 130 is used to reset the output terminal OUP to the low working voltage VSS in the preset stage, and to reset the output terminal OUN to the high working voltage VDD.

[0042] In the charge transfer stage, the switching signal Φ2 and the control signals E1-E2 are at the enable level, and the switching signal Φ1 and the preset signal P are at the disable level. By the cooperation of the comparator 132, the charge pump 134a and the charge pump 134b, the charge transfer circuit 130 is used to amplify the adjusted voltages VDP and VDN in the charge transfer stage to generate output voltages VOP and VON at the output terminals OUP and OUN. In detail, the comparator 132 is used to compare the adjusted voltages VDP and VDN, and control the charge pumps 134a-134b according to the comparison result. As mentioned above, when the reference voltages VREP and VREN are different, the comparator 132 will enable the charge pumps 134a-134b (that is, turn on the switches SW3-SW4 and SW7-SW8). At this time, the decoder 124 will enable the selected current source combination (for example, by turning on the switches SW1 and SW5 to enable the combination of current sources I1 and I3, or by turning on the switches SW2 and SW6 to enable the combination of current sources I2 and I4), so that the charge pumps 134a-134b start to charge and discharge the output terminals OUP and OUN to generate the output voltages VOP and VON. On the other hand, when the reference voltages VREP and VREN become the same, the comparator 132 will switch the control signals E1-E2 to the disable level to disable the charge pumps 134a-134b (that is, turn off the switches SW3-SW4 and SW7-SW8).

[0043] In summary, when the decoder 124 determines that the output voltage VOP will eventually be less than the output voltage VON, the current sources I1 and I3 with simpler structures will be used to charge and discharge the output terminals OUP and OUN, respectively. On the other hand, when the decoder 124 determines that the output voltage VOP will eventually be greater than the output voltage VON, the current sources I2 and I4 with more complex structures will be used to charge and discharge the output terminals OUP and OUN, respectively.

[0044] In summary, in the sampling phase, the sampling capacitor arrays 110a-110b are used to sample the input voltages VIP and VIN respectively. In the conversion phase, the control circuit 120 is used to convert the input voltages VIN and VIP into Figure 5 The invention relates to a plurality of voltage thresholds T1 to T13 (for example, comparing the input voltage difference Vdif between the input voltage VIN and the input voltage VIP with the plurality of voltage thresholds T1 to T13), and executes (1) determining the magnitude of the reference voltages VREP and VREN, (2) selecting one of the current sources I1 and I2 (for example, the current source I1) to be enabled in the next charge transfer stage, and (3) selecting one of the current sources I3 and I4 (for example, the current source I3) to be enabled in the next charge transfer stage.

[0045] In the preset stage, the control circuit 120 is used to adjust the input voltage VIP sampled by the sampling capacitor array 110a according to the size of the input voltage VIP to generate the adjusted voltage VDP, and is used to adjust the input voltage VIN sampled by the sampling capacitor array 110b according to the size of the input voltage VIN to generate the adjusted voltage VDN. In detail, the control circuit 120 is used to couple the reference voltage VREP to the input voltage VIP sampled by the sampling capacitor array 110a to generate the adjusted voltage VDP, and the control circuit 120 is used to couple the reference voltage VREN to the input voltage VIN sampled by the sampling capacitor array 110b to generate the adjusted voltage VDN. In addition, the charge transfer circuit 130 provides the low working voltage VSS and the high working voltage VDD to the output terminals OUP and OUN, respectively, in the preset stage.

[0046] In the charge transfer stage, the control circuit 120 enables one of the current sources I1 and I2 (for example, current source I1) and one of the current sources I3 and I4 (for example, current source I3) according to the input voltage VIN and VIP (that is, the selection result in the conversion stage), so that the charge transfer circuit 130 amplifies the adjusted voltages VDP and VDN in the charge transfer stage to generate output voltages VOP and VON at the output terminals OUP and OUN.

[0047] Figure 6 FIG. 1 is a schematic diagram of current-voltage characteristics of current sources I1 and I2 according to an embodiment of the present disclosure. Figure 6 , the vertical axis is the output current of the current source (e.g., the current output to the output terminal OUP), and the horizontal axis is the voltage across the current source (e.g., the difference between the high operating voltage VDD and the output voltage VOP). The characteristic curves of the current sources I1 and I2 are curves 610 and 620, respectively.

[0048] The current sources I1 and I2 enter their respective saturation regions from the linear region at the cross voltages VF1 and VF2, respectively, wherein the cross voltage VF1 is higher than the cross voltage VF2. Affected by the channel effect, the output currents of the current sources I1 and I2 in the saturation region will change with the cross voltage. When the current source I1 operates in the first saturation region (i.e., the section of the horizontal axis after the cross voltage VF1) and receives a first cross voltage change, the output current change generated will be smaller than the output current change generated when the current source I2 operates in the second saturation region (i.e., the section of the horizontal axis after the cross voltage VF2) and receives the first cross voltage change. The current source I3 and the current source I4 may also have the above-mentioned output current characteristics, that is, when a second cross voltage change is applied to the current source I3 operating in the third saturation region and the current source I4 operating in the fourth saturation region, the output current change of the current source I3 will be smaller than the output current change of the current source I4. In other words, the slope of the curve 610 in its saturation region is smaller than the slope of the curve 620 in its saturation region. In some embodiments, the aforementioned “current-voltage characteristics” include but are not limited to (1) the voltage across the current source required to move from the linear region to the saturation region and (2) the output current change when the current source operates in the saturation region under a fixed voltage across the current source.

[0049] As mentioned above, when the decoder 124 determines that the output voltage VOP is less than the output voltage VON, the current source I1 will be enabled, and the current source I1 will mainly work in the region R1 with a larger cross-voltage. On the other hand, when the decoder 124 determines that the output voltage VOP is greater than the output voltage VON, the current source I2 will be enabled, and the current source I2 will mainly work in the region R2 with a smaller cross-voltage. Therefore, by comparing the output current of the charge pump 134a when the output voltage VOP is at the maximum value and the minimum value, it can be obtained that the current variation of the charge pump 134a is only ΔI1+ΔI2. In contrast, in the example where the charge pump 134a only includes the current source I1, the charge pump 134a will have a larger current variation ΔI1'. In the example where the charge pump 134a only includes the current source I2, the charge pump 134a will also have a larger current variation ΔI2'.

[0050] As can be seen from the above, by adaptively enabling the current source I1 or I2 according to the output voltage VOP, the current variation of the charge pump 134a can be reduced. The current-voltage characteristics of the current sources I3 and I4 are similar to those of the current sources I1 and I2, respectively. Therefore, the current variation of the charge pump 134b can also be reduced by similar operations, which are not repeated here for the sake of brevity. By reducing the current variation of the charge pumps 134a and 134b, the switched capacitor circuit 100 has the advantage of high linearity.

[0051] Figure 7FIG. 7 is a simplified functional block diagram of a switched capacitor circuit 700 according to an embodiment of the present disclosure. The switched capacitor circuit 700 includes a sampling capacitor array 710, a control circuit 720, and a charge transfer circuit 730. The sampling capacitor array 710 is similar to Figure 1 For the sake of brevity, the sampling capacitor array 110a is not repeated here. The control circuit 720 includes an analog-to-digital converter 722 and a decoder 724. The analog-to-digital converter 722 is coupled to the input terminal INP, and is used to generate a digital code Bi according to the input voltage VIP. The decoder 724 is coupled to the analog-to-digital converter 722, and is used to generate a reference voltage VREP according to the digital code Bi. The reference voltage VREP is used to couple to the sampling capacitor array 710, thereby generating an adjusted voltage VDP.

[0052] The charge transfer circuit 730 includes a comparator 732, a charge pump 734, and a feedback path 736. A first input terminal (e.g., a non-inverting input terminal) of the comparator 732 is coupled to the second terminals of the capacitors C1-C2 to receive the adjusted voltage VDP. A second input terminal (e.g., an inverting input terminal) of the comparator 732 is used to receive the common voltage Vcm. The comparator 732 is used to generate a control signal E1 according to the adjusted voltage VDP and the common voltage Vcm to control the charge pump 734 using the control signal E1. For example, when the adjusted voltage VDP and the common voltage Vcm are different, the comparator 732 uses the control signal E1 to enable the charge pump 734. For another example, when the adjusted voltage VDP and the common voltage Vcm are the same, the comparator 732 uses the control signal E1 to disable the charge pump 734. The charge pump 734 and the feedback path 736 are similar to Figure 1 For the sake of brevity, the charge pump 134a and the feedback path 136a are not repeated here.

[0053] Please refer to Figure 8, where Figure 8 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit 700 according to an embodiment of the present disclosure. Figure 8 Similar to Figure 5 , the difference is Figure 8 The vertical axis and horizontal axis of are the output voltage VOP and the input voltage VIP, respectively. The analog-to-digital converter 722 is used to use multiple comparators to compare the input voltage VIP with multiple voltage thresholds T1-T13. Thus, the analog-to-digital converter 722 can determine the voltage range including the input voltage VIP from the multiple voltage ranges A1-A14, and output a digital code Bi representing the voltage range.

[0054] The decoder 724 is used to determine which of the voltage ranges A1 to A14 the input voltage VIP is located in according to the digital code Bi, and determine the working state (i.e., enable or disable) of each of the current sources I1 to I2 in the charge transfer phase according to the determination result. When the input voltage VIP is located in a voltage range indicated by an odd number (e.g., voltage ranges A1, A3, etc.), the decoder 724 determines that the current source I1 needs to be enabled in the charge transfer phase according to the digital code Bi, and determines that the current source I2 needs to be disabled in the charge transfer phase. On the other hand, when the input voltage VIP is located in a voltage range indicated by an even number (e.g., voltage ranges A2, A4, etc.), the decoder 724 determines that the current source I1 needs to be disabled in the charge transfer phase according to the digital code Bi, and determines that the current source I2 needs to be enabled in the charge transfer phase.

[0055] In other words, when the input voltage VIP is in the Mth voltage range of the voltage range A1 to A14 and the output voltage VOP is less than the common voltage Vcm, the decoder 724 enables the current source I1, and when the input voltage VIP is in the M+1th voltage range of the voltage range A1 to A14 and the output voltage VOP is greater than or equal to the common voltage Vcm, the decoder 724 enables the current source I2, where M is a positive integer.

[0056] In other words, when the input voltage VIP is adjacent to the Jth voltage threshold (e.g., the first voltage threshold T1) among the voltage thresholds T1 to T13, and is less than the Jth voltage threshold, it means that after the charge transfer stage described later ends, the output voltage VOP is less than the common voltage Vcm. In this case, the decoder 724 enables the current source I1 and disables the current source I2, where J is an odd number. When the input voltage VIP is adjacent to the Jth voltage threshold, and is greater than or equal to the Jth voltage threshold, it means that after the charge transfer stage described later ends, the output voltage VOP is greater than or equal to the common voltage Vcm. In this case, the decoder 724 disables the current source I1 and enables the current source I2.

[0057] The remaining operation modes and advantages of the control circuit 720 and the charge transfer circuit 730 are similar to those of Figure 1 For the sake of brevity, the control circuit 120 and the charge transfer circuit 130 are not repeated here.

[0058] In summary, in the sampling phase, the sampling capacitor array 710 is used to sample the input voltage VIP. In the conversion phase, the control circuit 720 is used to convert the input voltage VIP into a voltage. Figure 8The relationship between multiple voltage thresholds T1~T13 (for example, comparing the input voltage VIP with the multiple voltage thresholds T1~T13) is used to perform (1) determine the size of the reference voltage VREP and (2) select one of the current sources I1 and I2 (for example, the current source I1) to be enabled in the next charge transfer stage.

[0059] In the preset stage, the control circuit 720 is used to adjust the input voltage VIP sampled by the sampling capacitor array 710 to generate the adjusted voltage VDP according to the size of the input voltage VIP. In detail, the control circuit 720 is used to couple the reference voltage VREP to the input voltage VIP sampled by the sampling capacitor array 710 to generate the adjusted voltage VDP. In addition, the charge transfer circuit 730 provides the low working voltage VSS to the output terminal OUP in the preset stage.

[0060] In the charge transfer phase, the control circuit 720 enables one of the current sources I1 and I2 (for example, the current source I1) according to the input voltage VIP (i.e., the selection result in the conversion phase) so that the charge transfer circuit 730 amplifies the adjusted voltage VDP in the charge transfer phase to generate an output voltage VOP at the output terminal OUP.

[0061] Fig. 9 FIG. 1 is a simplified functional block diagram of a pipelined analog-to-digital converter 900 according to an embodiment of the present disclosure. The pipelined analog-to-digital converter 900 includes a sample-and-hold circuit 910, a plurality of converter circuit systems 920[1] to 920[3], a clock generator 930, and a digital correction circuit 940. The sample-and-hold circuit 910 is used to sample an input signal Vinput.

[0062] The converter circuit systems 920[1]-920[3] are used to sequentially convert the output of the previous stage into a plurality of digital codes Bi[1]-Bi[3], wherein the converter circuit system 920[1] is used to convert the sampling result of the input signal Vinput by the sample and hold circuit 910. The number of converter circuit systems 920[1]-920[3] is only an example, and the present disclosure is not limited thereto.

[0063] The clock generator 930 is used to generate a plurality of clock signals to the sampling and holding circuit 910 and the converter circuit system 920[1]-920[3], so that the sampling and holding circuit 910 and the converter circuit system 920[1]-920[3] perform the above operations according to the clock signals. The digital correction circuit 940 is used to combine the digital codes Bi[1]-Bi[3] to generate the digital code DOUT. In some implementations, the digital correction circuit 940 is also used to correct the offset error and / or gain error of the converter circuit system 920[1]-920[3].

[0064] In some embodiments, each of the converter circuit systems 920[1]-920[3] may be composed of Figure 1 For example, the output voltage of the switched capacitor circuit 100 can be used as the input voltage of the next stage converter circuit system, and the digital code Bi generated by the switched capacitor circuit 100 can be used as a corresponding one of the digital codes Bi[1] to Bi[3]. In other embodiments, each of the converter circuit systems 920[1] to 920[3] can be Figure 7 The pipelined analog-to-digital converter 900 also has the advantage of high linearity.

[0065] Certain words are used in the specification and the scope of the patent application to refer to specific components. However, those with ordinary knowledge in the relevant technical field should understand that the same component may be referred to by different terms. The specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second element through other elements or connection means.

[0066] The description method of "and / or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes the meaning of the plural term.

[0067] The above are only preferred embodiments of the present disclosure, and various modifications and equivalent changes may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.

[0068]

Explanation of symbols

[0069] 100,700: Switched capacitor circuit

[0070] 110a, 110b, 710: sampling capacitor array

[0071] 120,720: Control circuit

[0072] 122,722:Analog-to-digital converter

[0073] 124,724:Decoder

[0074] 130,730: Charge transfer circuit

[0075] 132,732: Comparator

[0076] 134a,134b,734: Charge pump

[0077] 136a,136b,736: Feedback path

[0078] 610,620: Curve

[0079] 900: Pipeline Analog-to-Digital Converter

[0080] 910: Sample and hold circuit

[0081] 920[1]~920[3]: Converter circuit system

[0082] 930: Clock generator

[0083] 940: Digital correction circuit

[0084] Bi,Bi[1]~Bi[3],DOUT: digital code

[0085] C1~C4: Capacitor

[0086] INN, INP: Input terminal

[0087] OUP, OUN: output end

[0088] VIP,VIN: Input voltage

[0089] VOP,VON: output voltage

[0090] VREP, VREN: reference voltage

[0091] VDP, VDN: adjusted voltage

[0092] Vcm: common voltage

[0093] VDD: High operating voltage

[0094] VSS: Low operating voltage

[0095] Φ1,Φ2: switching signal

[0096] P: Preset signal

[0097] E1, E2: control signal

[0098] S1, S2: Select signal

[0099] S11, S12, S21, S22: sub-selection signal

[0100] SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8: switches

[0101] I1, I2, I3, I4: current source

[0102] R1, R2: Area

[0103] ΔI1, ΔI2, ΔI1', ΔI2': Current variation

[0104] VF1, VF2: cross pressure.

Claims

1. A switched capacitor circuit, comprising: a first sampling capacitor array, used for sampling a first input voltage in a sampling phase; A charge transfer circuit comprises a first current source and a second current source having different current-voltage characteristics, wherein the first current source and the second current source are coupled to a first output terminal; and A control circuit is used to adjust a sampling result of the first sampling capacitor array according to the first input voltage in a preset stage to generate a first adjusted voltage, and is used to enable one of the first current source and the second current source according to the first input voltage in a charge transfer stage so that the charge transfer circuit amplifies the first adjusted voltage in the charge transfer stage to generate a first output voltage at the first output end.

2. The switched capacitor circuit of claim 1 , further comprising: a second sampling capacitor array, used for sampling a second input voltage during the sampling phase, The charge transfer circuit further comprises a third current source and a fourth current source having different current-voltage characteristics, wherein the third current source and the fourth current source are coupled to a second output terminal. The control circuit is further used to adjust a sampling result of the second sampling capacitor array according to the second input voltage in the preset stage to generate a second adjusted voltage, and to enable one of the first current source and the second current source and one of the third current source and the fourth current source in the charge transfer stage according to an input voltage difference between the first input voltage and the second input voltage, so that the charge transfer circuit amplifies the second adjusted voltage in the charge transfer stage to generate a second output voltage at the second output end.

3. The switched capacitor circuit according to claim 2, wherein: The control circuit includes: an analog-to-digital converter, for comparing the input voltage difference with a plurality of voltage thresholds to determine a first voltage range including the input voltage difference from a plurality of voltage ranges, and for outputting a first digital code corresponding to the first voltage range, wherein the plurality of voltage ranges are defined by the plurality of voltage thresholds arranged in ascending order; as well as A decoder is used for determining whether the first current source, the second current source, the third current source and the fourth current source are enabled or disabled according to the first digital code.

4. The switched capacitor circuit according to claim 2, wherein: When the input voltage difference is in an Mth voltage range of the multiple voltage ranges, the control circuit enables the first current source and the third current source, where M is a positive integer; and when the input voltage difference is in an M+1th voltage range of the multiple voltage ranges, the control circuit enables the second current source and the fourth current source.

5. The switched capacitor circuit according to claim 4, wherein: When the input voltage difference is within the Mth voltage range, the first output voltage is less than the second output voltage; and When the input voltage difference is within the (M+1)th voltage range, the first output voltage is greater than the second output voltage.

6. The switched capacitor circuit according to claim 4, wherein: In the preset stage, the first output terminal is reset to a low voltage, and the second output terminal is reset to a high voltage. When a first voltage variation is applied to the first current source operating in a first saturation region and the second current source operating in a second saturation region, the output current variation of the first current source is smaller than the output current variation of the second current source, When a second voltage variation is applied to the third current source operating in a third saturation region and the fourth current source operating in a fourth saturation region, the output current variation of the third current source is smaller than the output current variation of the fourth current source.

7. A switched capacitor circuit, comprising: a first sampling capacitor array, used for sampling a first input voltage in a sampling phase; A charge transfer circuit comprises a first current source and a second current source having different current-voltage characteristics, wherein the first current source and the second current source are coupled to a first output terminal; and A control circuit is used to couple a first reference voltage to the sampling result of the first sampling capacitor array in a preset stage to generate a first adjusted voltage, and is used to determine the size of the first reference voltage according to the relationship between multiple voltage thresholds and the first input voltage and select one of the first current source and the second current source to be enabled in a charge transfer stage, so that the charge transfer circuit amplifies the first adjusted voltage in the charge transfer stage to generate a first output voltage at the first output terminal.

8. The switched capacitor circuit of claim 7, further comprising: a second sampling capacitor array, used for sampling a second input voltage during the sampling phase, The charge transfer circuit further comprises a third current source and a fourth current source having different current-voltage characteristics, wherein the third current source and the fourth current source are coupled to a second output terminal. The control circuit is further used for coupling a second reference voltage to the sampling result of the second sampling capacitor array in the preset stage to generate a second adjusted voltage, and for determining the first reference voltage and a second reference voltage according to a comparison result of an input voltage difference between the first input voltage and the second input voltage and the plurality of voltage thresholds. The control circuit is also used to select one of the first current source and the second current source and one of the third current source and the fourth current source to be enabled in the charge transfer stage according to the comparison result, so that the charge transfer circuit amplifies the second adjusted voltage in the charge transfer stage to generate a second output voltage at the second output end.

9. A pipeline analog-to-digital converter, comprising a plurality of converter circuit systems, wherein each converter circuit system comprises: a first sampling capacitor array, used for sampling a first input voltage in a sampling phase; A charge transfer circuit comprises a first current source and a second current source having different current-voltage characteristics, wherein the first current source and the second current source are coupled to a first output terminal; and A control circuit is used to adjust the sampling result of the first sampling capacitor array according to the first input voltage in a preset stage to generate a first adjusted voltage, and is used to enable one of the first current source and the second current source according to the first input voltage in a charge transfer stage so that the charge transfer circuit amplifies the first adjusted voltage in the charge transfer stage to generate a first output voltage at the first output end.

10. The pipelined analog-to-digital converter of claim 9, wherein: The converter circuit system also includes: a second sampling capacitor array, used for sampling a second input voltage during the sampling phase, The charge transfer circuit further comprises a third current source and a fourth current source having different current-voltage characteristics, wherein the third current source and the fourth current source are coupled to a second output terminal. The control circuit is further used to adjust the sampling result of the second sampling capacitor array according to the second input voltage in the preset stage to generate a second adjusted voltage, and to enable one of the first current source and the second current source and one of the third current source and the fourth current source in the charge transfer stage according to an input voltage difference between the first input voltage and the second input voltage, so that the charge transfer circuit amplifies the second adjusted voltage in the charge transfer stage to generate a second output voltage at the second output end.

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