High-linearity high-order prediction type SAR ADC and switch switching method thereof

Abstract

The invention discloses a high-linearity high-order prediction type SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) and a switch switching method thereof. A capacitor array, a coarse comparator, a low-noise comparator, a signal prediction module and an SAR logic module which are arranged in a mirror image manner at a P end and an N end are integrated. The P-end capacitor array and the N-end capacitor array are connected with the signal prediction module through respective input switches, and the output of the prediction module is connected with the coarse comparator for preliminarily determining the high-order value of the SAR logic module. The SAR logic module introduces a redundancy by controlling the connection mode of the switch S5 and the switch S6 according to the result of the coarse comparator. And the output of the SAR logic module is also connected with a decoding module so as to realize final digital signal output. According to the invention, the number of capacitors required for realizing the high-precision SAR ADC is greatly reduced, the technical problem of design complexity caused by capacitor mismatch is relieved, and the linearity and conversion precision of the ADC are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits and relates to a high-linearity high-bit prediction type SAR ADC and a switch switching method thereof. Background Art

[0002] Analog-to-Digital Converter (ADC) is a key component in electronic systems. It is responsible for converting continuous analog signals into discrete digital signals. Its performance directly affects the accuracy and efficiency of the entire system. Among the many types of ADCs, Successive Approximation Register (SAR) ADC has become a hot spot in research and application in recent years due to its simple structure, low power consumption, high energy efficiency and good adaptability to advanced processes. SAR ADC is widely used in the fields of Internet of Things, automotive electronics, industrial electronics, medical electronics and advanced instrumentation, which have put forward higher and higher requirements on the accuracy of ADC.

[0003] However, SAR ADC faces many challenges in achieving high precision, among which the design of capacitor array is one of the key problems. The design of capacitor array is mainly limited by two factors: thermal noise and capacitor mismatch. In actual design, the existing switching timing is often more limited by the influence of capacitor mismatch. In order to overcome the problems caused by capacitor mismatch, the industry has proposed a variety of calibration techniques, such as digital background calibration and analog foreground calibration. However, these technologies usually involve complex digital logic, which not only increases the complexity of the design, but also significantly increases the area and power consumption overhead, which is not conducive to the practical application of high-precision SAR ADC. Summary of the invention

[0004] The purpose of the present invention is to solve the technical problems in the prior art of overcoming the design complexity caused by capacitor mismatch and the excessively large number of capacitors required when realizing a high-precision SAR ADC, and to provide a high-linearity high-bit prediction SAR ADC and a switch switching method thereof.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: A first aspect of the present invention provides a high-linearity high-bit prediction type SAR ADC, comprising: a P-terminal capacitor array, an N-terminal capacitor array, a coarse comparator, a low-noise comparator, a signal prediction module and a SAR logic module; The output end of the P-terminal capacitor array is connected to the positive end of the low-noise comparator input end; the N-terminal capacitor array is connected to the negative end of the low-noise comparator input end; the output end of the low-noise comparator is connected to the input end of the SAR logic module; the output end of the SAR logic module is connected to a decoding module; The P-end capacitor array and the N-end capacitor array are mirror images; the input end of the P-end capacitor array is provided with a switch S1; the input end of the N-end capacitor array is provided with a switch S2; the output ends of the switches S1 and S2 are both connected to the input end of the signal prediction module; the output end of the signal prediction module is connected to the input end of the coarse comparator; the output end of the coarse comparator is connected to the input end of the SAR logic module; The SAR logic module controls the connection mode of one end of the switch S5 and the switch S6 respectively according to the output of the coarse comparator; the other end of the switch S5 is connected to a redundant capacitor and then connected to the switch S3; the switch S3 is connected to the positive end of the input end of the low noise comparator; The other end of the switch S6 is connected to a redundant capacitor and then connected to the switch S4; the switch S4 is connected to the negative end of the input end of the low noise comparator.

[0006] Furthermore, the switch S1 and the switch S2 are both gate voltage bootstrap switches.

[0007] Furthermore, the switch S3 , the switch S4 , the switch S5 and the switch S6 are all CMOS complementary switches.

[0008] Furthermore, symmetrical redundant capacitors are respectively arranged at the middle positions of the P-end capacitor array and the N-end capacitor array.

[0009] Furthermore, the P-end capacitor array and the N-end capacitor array both include a capacitor group and a switch group, the capacitor group includes a plurality of capacitors; the switch group includes a plurality of switches; and the bottom plate of each capacitor is connected to a switch.

[0010] Furthermore, the coarse comparator is a StrongArm structure comparator.

[0011] Furthermore, the signal at the output end of the signal prediction module is one sampling time ahead of the signal at the input end of the signal prediction module.

[0012] A second aspect of the present invention provides a high-linearity high-bit predictive SAR ADC switch switching method, comprising the following steps: By sampling the input signal, a sampling signal is obtained; The sampled signal is predicted by a signal prediction module to obtain a predicted signal; The prediction signal is compared by a coarse comparator, and the value of the highest bit output by the SAR logic module is output; the SAR logic module controls the connection mode of the switch S5 and the switch S6 according to the value of the highest bit output by the SAR logic module; Different redundancy amounts are obtained according to different connection modes of switch S5 and switch S6; Disconnect switch S3 and switch S4; connect the bottom plates of all capacitors of the P-terminal capacitor array and the N-terminal capacitor array to VCM; Input the sampling signal into the P-terminal capacitor array and the N-terminal capacitor array, and then compare them with the low-noise comparator to obtain the value of the next high bit output by the SAR logic module; change the connection mode of the bottom plate of the capacitor in the P-terminal capacitor array or the N-terminal capacitor array based on the difference in the value of the next high bit output by the SAR logic module; repeat this step until the value of the lowest bit of the SAR logic module is determined; and obtain the output of the SAR logic module; According to the different values ​​of the highest bit output by the SAR logic module, the decoding module decodes the output of the SAR logic module using different decoding methods.

[0013] Furthermore, the SAR logic module controls the connection mode of switch S5 and switch S6 according to the value of the highest bit, specifically: When the highest bit value output by the SAR logic module is 1, switch S5 is connected to GND and switch S6 is connected to VREF; When the value of the highest bit output by the SAR logic module is 0, the switch S5 is connected to VREF, and the switch S6 is connected to GND.

[0014] Furthermore, according to the different values ​​of the highest bit of the SAR logic module, the decoding module uses different decoding methods to decode the output of the SAR logic module, specifically: When the value of the highest bit of the SAR logic module output is 1, the decoding module decodes the output of the SAR logic module by subtracting the redundancy; When the value of the highest bit output by the SAR logic module is 0, the decoding module performs decoding by adding redundancy to the output of the SAR logic module.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a high-linearity high-bit prediction SAR ADC, which reduces the error caused during sampling by introducing a signal prediction module, thereby reducing the required redundancy, and further reducing the use of capacitors, power consumption and chip area; the highest bit (MSB) of the output code is directly obtained by the predicted signal through the output of a coarse comparator, avoiding the use of a capacitor array in the traditional technology, thereby improving the ADC linearity; the bottom plate of the capacitor is preset by controlling switches S5 and S6 during the sampling phase according to the result of the MSB, so that after the sampling is completed, the two comparison conditions of the second highest bit can be realized by connecting all the bottom plates of the capacitor array to the VCM level. Similarly, because it is a level change of the overall capacitor, the generation of the second highest bit is not affected by the capacitor mismatch, thereby further improving the linearity of the ADC.

[0016] The present invention discloses a high-linearity high-bit prediction SAR ADC switch switching method. By introducing a signal prediction module, the signal is preprocessed after the sampling stage, and the change trend of the signal is effectively predicted, so that the quantization level of the signal can be more accurately located during the SAR (successive approximation) conversion process. This method reduces the error caused by direct quantization and significantly improves the conversion accuracy and linearity of the ADC (analog-to-digital converter), especially in high-resolution applications. The coarse comparator is used to quickly determine the highest bit value of the SAR logic module, and the connection mode of switches S5 and S6 is dynamically adjusted accordingly. This strategy not only accelerates the high-bit decision-making process, but also realizes the effective use of redundancy by flexibly configuring the capacitor array (including the P terminal and the N terminal), further improving the conversion efficiency and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a schematic diagram of the overall architecture of a 14-bit SAR ADC in an embodiment of the present invention; Figure 2 4 is a working principle diagram of a 4-bit SAR ADC switch switching method in an embodiment of the present invention; Figure 3 This is a structural diagram of a first-order approximate signal prediction module in an embodiment of the present invention; Figure 4 This is a schematic diagram of the key control timing of a 14-bit SAR ADC in an embodiment of the present invention; Figure 5 A schematic diagram of a transmission curve of a switch timing in an embodiment of the present invention; Figure 6 The figure is a flowchart of the high-linearity and high-bit predictive SAR ADC switch switching method of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention described and marked in the drawings here can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0022] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0023] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] The present invention is further described in detail below in conjunction with the accompanying drawings: See also Figure 1 , the present invention proposes a high-linearity high-bit prediction type SAR ADC, including a P-terminal capacitor array, an N-terminal capacitor array, a coarse comparator, a low-noise comparator, a signal prediction module and a SAR logic module (SAR Logic); The output end of the P-terminal capacitor array is connected to the positive end of the low-noise comparator input end; the N-terminal capacitor array is connected to the negative end of the low-noise comparator input end; the output end of the low-noise comparator is connected to the input end of the SAR logic module; the output end of the SAR logic module is connected to a decoding module (Decoder); The P-end capacitor array and the N-end capacitor array are mirror-imaged; the input end of the P-end capacitor array is provided with a switch S1; the input end of the N-end capacitor array is provided with a switch S2; the output ends of the switch S1 and the switch S2 are both connected to the input end of the signal prediction module; the output end of the signal prediction module is connected to the input end of the coarse comparator; the output end of the coarse comparator is connected to the input end of the SAR logic module; the switch S1 and the switch S2 are both gate voltage bootstrap switches.

[0025] The SAR logic module controls the connection mode of one end of switch S5 and switch S6 according to the output of the coarse comparator; the other end of the switch S5 is connected to a 16C capacitor and then connected to switch S3; the switch S3 is connected to the positive end of the low noise comparator input; the other end of the switch S6 is connected to a 16C capacitor and then connected to switch S4; the switch S4 is connected to the negative end of the low noise comparator input. Switch S3, switch S4, switch S5 and switch S6 are all CMOS complementary switches.

[0026] The P-end capacitor array and the N-end capacitor array both include a capacitor group and a switch group, the capacitor group includes 12 capacitors and 1 16C redundant capacitor; the switch group includes 13 switches; the bottom plate of each capacitor is connected to 1 switch; the redundant capacitor is arranged in the middle position of the capacitor group.

[0027] The coarse comparator adopts a traditional StrongArm structure comparator. The noise of the low noise comparator should be at least less than the quantization noise; the signal at the output end of the signal prediction module is one sampling time ahead of the signal at the input end of the signal prediction module.

[0028] See also Figure 6 The present invention discloses a high-linearity high-bit prediction SAR ADC switch switching method, comprising the following steps: Step 1, sampling the input signal to obtain a sampling signal; Step 2, predict the sampled signal through the signal prediction module to obtain the predicted signal; Step 3, compare the predicted signal through the coarse comparator and output the value of the highest bit of the SAR logic module; the SAR logic module controls the connection mode of the switch S5 and the switch S6 according to the value of the highest bit; Step 4, different redundancy amounts are obtained according to different connection modes of switch S5 and switch S6; Step 5, disconnect switch S3 and switch S4; connect the bottom plates of all capacitors of the P-end capacitor array and the N-end capacitor array to VCM; Step 6, input the sampling signal into the P-terminal capacitor array and the N-terminal capacitor array, and then compare them with the low-noise comparator to obtain the value of the second highest bit of the SAR logic module; change the connection method of the bottom plate of the capacitor in the P-terminal capacitor array or the N-terminal capacitor array based on the difference in the value of the second highest bit; repeat this step until the value of the lowest bit of the SAR logic module is determined; and obtain the output of the SAR logic module; Step 7, according to the different values ​​of the highest bit of the SAR logic module, the decoding module uses different decoding methods to decode the output of the SAR logic module.

[0029] See also Figure 1 and 2 The present invention discloses a high-linearity high-bit prediction SAR ADC switch switching method, comprising the following steps: Step 1, sampling the input signal to obtain a sampling signal; the input signal VIP and the input signal VIN are sampled through the gate voltage bootstrap switch S1 and the switch S2.

[0030] Step 2, predict the sampled signal through the signal prediction module to obtain the predicted signal; the sampled VIP and VIN signals pass through the signal prediction module and then output the predicted signals VIP_P and VIN_N. Figure 3 , the signal prediction module is a first-order approximate prediction structure, and the transfer function of the predictor implemented by this structure is:

[0031] Where A0 = R F / R IN is the DC gain, τ = R IN C IN is the time constant, G (s) is the transfer function of the operational amplifier, and by adjusting R IN With C IN The phase delay of the predictor input and output signals can be adjusted. In the embodiment of the present invention, the time constant is adjusted so that its size is equal to the sampling time (TS, see Figure 4 ) are equal, so that the signal at the output of the signal prediction module is one sampling time ahead of the signal at the input of the signal prediction module.

[0032] Step 3, compare the prediction signal through the coarse comparator and output the value of the highest bit of the SAR logic module; the coarse comparator compares the prediction signal VIP_P and VIN_N, and the output of the coarse comparator is the value of the highest bit of the SAR logic module. The SAR logic module controls the connection mode of switch S5 and switch S6 according to the value of the highest bit.

[0033] Step4. Different redundancy amounts are obtained according to different connection modes of switch S5 and switch S6. Exemplarily, as Figure 1 shown, when the output of the coarse comparator is 1, that is, the most significant bit value MSB = 1 output by the SAR logic module, then at the initial stage of sampling, S5 is connected to GND and S6 is connected to VREF. After sampling ends, S5 is connected to VREF and S6 is connected to GND. This will introduce a redundant voltage amount VT of . Step5. Disconnect switches S3 and S4; connect the bottom plates of all capacitors in the P-terminal capacitor array and the N-terminal capacitor array to VCM; Step6. After the sampling signal is input into the P-terminal capacitor array and the N-terminal capacitor array, it is compared by a low-noise comparator to obtain the value of the second most significant bit (i.e., the MSB - 1 bit) output by the SAR logic module; Step601. Sample the input signal; since the MSB is obtained from the predicted signal and is one sampling time ahead of the input signal, the value obtained after sampling the input signal corresponds to the value of the predicted signal; after sampling ends, the sampling signal is input into the P-terminal capacitor array and the N-terminal capacitor array and then compared by a low-noise comparator: when the voltage VP at the input terminal of the low-noise comparator > VN, the output of the low-noise comparator is 1, that is, the value of the second most significant bit (i.e., the MSB - 1 bit) of the SAR logic module is 1; when the voltage VP at the input terminal of the low-noise comparator < VN, the output of the low-noise comparator is 0, that is, the value of the second most significant bit (i.e., the MSB - 1 bit) of the SAR logic module is 0; the VP is the voltage at the positive terminal of the input terminal of the low-noise comparator, and the VN is the voltage at the negative terminal of the input terminal of the low-noise comparator.

[0034] Step602. Based on the different values of the MSB - 1 bit, change the connection mode of the bottom plates of the capacitors in the P-terminal capacitor array or the N-terminal capacitor array; When the value of the MSB - 1 bit is 1, the bottom plates of the capacitors in the N-terminal capacitor array are all connected to VREF; when the value of the MSB - 1 bit is 0, the bottom plates of the capacitors in the P-terminal capacitor array are all connected to VREF; Step603. Based on the connection mode of S602, readjust the connection mode of the bottom plates of the capacitors in the P-terminal capacitor array or the N-terminal capacitor array according to the output of the low-noise comparator.

[0035] When the value of the MSB - 1 bit is 1: when the voltage VP at the input terminal of the low-noise comparator > VN, the output of the low-noise comparator is 1, that is, the value of the MSB - 2 bit is 1. At this time, change the connection mode of the bottom plate of the highest-bit capacitor in the P-terminal capacitor array to GND; When the voltage VP < VN at the input terminal of the low-noise comparator, the output of the low-noise comparator is 0, that is, the value of the MSB-2 bit is 0. At this time, change the connection mode of the bottom plate of the capacitor of the highest bit of the N-terminal capacitor array to VCM.

[0036] When the value of the MSB-1 bit is 0: When the voltage VP > VN at the input terminal of the low-noise comparator, the output of the low-noise comparator is 1, that is, the value of the MSB-2 bit is 1. At this time, change the connection mode of the bottom plate of the capacitor of the highest bit of the P-terminal capacitor array to VCM; When the voltage VP < VN at the input terminal of the low-noise comparator, the output of the low-noise comparator is 0, that is, the value of the MSB-2 bit is 0. At this time, change the connection mode of the bottom plate of the capacitor of the highest bit of the N-terminal capacitor array to GND.

[0037] Step604, based on the connection mode of Step603, continuously adjust the connection mode of the bottom plate of the capacitor in the P-terminal capacitor array or the N-terminal capacitor array according to the output of the low-noise comparator using the switching method of Step603 until the value of the lowest bit of the SAR logic module is determined.

[0038] Step7, according to the different values of the highest bit of the SAR logic module, the decoding module uses different decoding methods to decode the output of the SAR logic module.

[0039] When the value of the highest bit of the SAR logic module is 1, the decoding module decodes by subtracting the redundancy from the output of the SAR logic module; when the value of the highest bit of the SAR logic module is 0, the decoding module decodes by adding the redundancy to the output of the SAR logic module; that is:

[0040] X is the redundancy corresponding to VT in the digital domain (see Figure 5 ) is the 15-bit output of the SAR logic module; Dout is the 14-bit standard binary output.

[0041] The present invention determines the most significant bit (MSB) by utilizing the output result of the coarse comparator. This revolutionary design abandons the dependence on the capacitor array in the traditional architecture and significantly improves the linearity of the ADC. At the same time, the present invention reduces the error caused during the sampling period by introducing a signal prediction module, thereby reducing the required redundancy, thereby reducing the use of capacitors, reducing power consumption and chip area. By controlling switches S5 and S6 according to the value of the MSB bit, a redundant voltage is introduced into the sampled signal, and the bottom plate of the capacitor is preset, so that after the sampling is completed, the two comparison conditions of the second highest bit can be realized by connecting all the bottom plates of the P-terminal capacitor array and the N-terminal capacitor array to VCM. Similarly, because it is a level change of the overall capacitor, the generation of the second highest bit is not affected by the capacitor mismatch, thereby further improving the linearity of the ADC. Further, the present invention determines the connection mode of the bottom plate of the positive or negative end capacitor of the low-noise comparator according to the result of the second highest bit, thereby realizing four comparison conditions of the third bit. Similarly, because it is a level change of the entire capacitor at one end, the generation of the third bit is not affected by the capacitor mismatch, thereby further improving the linearity of the ADC.

[0042] In order to further illustrate the superiority of the high-linearity high-bit predictive SAR ADC switching method of the present invention, the superiority of the present invention is illustrated by comparing it with the existing switching method. The following is a description of the switching timing linearity and the number of capacitors required by different methods: Implementing N-bit SAR ADC, linearity of different switching timings:

[0043] The number of capacitors required for a 14-bit SAR ADC using different switching methods:

[0044] The present invention adopts high-bit prediction technology, and the acquisition of the upper three bits will not be affected by the capacitor mismatch. Therefore, the present invention has better linearity and is more suitable for the design of high-precision SAR ADC. Compared with the best existing technology (VCM-based monotonic switching timing), when realizing a SAR ADC with the same accuracy, it requires at least unit capacitor, and the present invention only needs The present invention can save half of the capacitance, so the high-linearity high-bit prediction SAR ADC of the present invention will have a smaller chip area and lower power consumption and cost.

[0045] The working process / working principle of the present invention is as follows: See also Figure 4, is a schematic diagram of the key control timing of the 14-bit SAR ADC in an embodiment of the present invention, wherein CLK is the sampling clock, which controls the switch S1 and the switch S2 to sample, the high level is sampled, the low level is held, and the sampling time is TS. The timing corresponding to the coarse comparator controls the operation of the coarse comparator, the high level is compared, and the low level is reset. LS is the level shift control signal that controls the switch S3 and the switch S4, the high level is turned on, and the low level is turned off. The timing corresponding to the low noise comparator controls the operation of the low noise comparator, the high level is compared, and the low level is reset. It can be understood that at the beginning of sampling, the sampling signal is predicted by the signal prediction module and compared by the coarse comparator to determine the value of the highest bit of the SAR logic module. Then, by controlling the switch S5 and the switch S6, a redundant voltage is introduced into the sampling signal. After the sampling is completed, the sampling signal is compared by the low noise comparator to output the 15-bit output of the SAR logic module.

[0046] The present invention solves the problem of deviation between the actual predictor and the ideal predictor when the signal prediction module predicts by adding redundancy at the initial sampling stage. Figure 5 As shown, the SAR ADC transmission curve after the ideal predictor introduces the redundant voltage VT is shown. The horizontal axis represents the input analog signal. It can be seen that the quantization range of the switching timing proposed by the present invention is VT-2VREF to 2VREF-VT, and the total voltage redundancy is 2VT, corresponding to the redundancy introduced in the digital domain is X. However, in actual design, the redundancy VT is generally less than one twentieth of VREF, so the quantization range of the timing can be approximated to 4VREF. The vertical axis is the digital signal, F…F represents the maximum code value in the digital domain, and 7…F represents the median of all code values ​​in the digital domain. The blue curve represents the transmission curve when MSB=0, and the red curve represents the transmission curve when MSB=1.

[0047] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A high-linearity high-bit prediction SAR ADC, characterized in that: include: P-terminal capacitor array, N-terminal capacitor array, coarse comparator, low noise comparator, signal prediction module and SAR logic module; The output end of the P-terminal capacitor array is connected to the positive end of the low-noise comparator input end; the N-terminal capacitor array is connected to the negative end of the low-noise comparator input end; the output end of the low-noise comparator is connected to the input end of the SAR logic module; the output end of the SAR logic module is connected to a decoding module; The P-end capacitor array and the N-end capacitor array are mirror images; the input end of the P-end capacitor array is provided with a switch S1; the input end of the N-end capacitor array is provided with a switch S2; the output ends of the switches S1 and S2 are both connected to the input end of the signal prediction module; the output end of the signal prediction module is connected to the input end of the coarse comparator; the output end of the coarse comparator is connected to the input end of the SAR logic module; The SAR logic module controls the connection mode of one end of the switch S5 and the switch S6 respectively according to the output of the coarse comparator; the other end of the switch S5 is connected to a redundant capacitor and then connected to the switch S3; the switch S3 is connected to the positive end of the input end of the low noise comparator; The other end of the switch S6 is connected to a redundant capacitor and then connected to the switch S4; the switch S4 is connected to the negative end of the input end of the low noise comparator.

2. The high-linearity high-bit prediction SAR ADC according to claim 1, characterized in that: The switch S1 and the switch S2 are both gate voltage bootstrap switches.

3. The high-linearity high-bit prediction SAR ADC according to claim 1, characterized in that: The switch S3 , the switch S4 , the switch S5 and the switch S6 are all CMOS complementary switches.

4. The high-linearity high-bit predictive SAR ADC according to claim 1, characterized in that: Symmetrical redundant capacitors are respectively arranged at the middle positions of the P-end capacitor array and the N-end capacitor array.

5. The high-linearity high-bit predictive SAR ADC according to claim 1, characterized in that: The P-terminal capacitor array and the N-terminal capacitor array both include a capacitor group and a switch group. The capacitor group includes a plurality of capacitors; the switch group includes a plurality of switches; and the bottom plate of each capacitor is connected to a switch.

6. The high-linearity high-bit predictive SAR ADC according to claim 1, characterized in that: The coarse comparator is a StrongArm structure comparator.

7. The high-linearity high-bit prediction SAR ADC according to claim 1, characterized in that: The signal at the output end of the signal prediction module is one sampling time ahead of the signal at the input end of the signal prediction module.

8. A high linearity high bit predictive SAR ADC switching method, based on the high linearity high bit predictive SAR ADC according to any one of claims 1, characterized in that: The following steps are involved: By sampling the input signal, a sampling signal is obtained; The sampled signal is predicted by a signal prediction module to obtain a predicted signal; The prediction signal is compared by a coarse comparator, and the value of the highest bit output by the SAR logic module is output; the SAR logic module controls the connection mode of the switch S5 and the switch S6 according to the value of the highest bit output by the SAR logic module; Different redundancy amounts are obtained according to different connection modes of switch S5 and switch S6; Disconnect switch S3 and switch S4; connect the bottom plates of all capacitors of the P-terminal capacitor array and the N-terminal capacitor array to VCM; The sampling signal is input into the P-terminal capacitor array and the N-terminal capacitor array and then compared by a low-noise comparator to obtain the next high-bit value output by the SAR logic module; Changing the connection mode of the bottom plate of the capacitor in the P-terminal capacitor array or the N-terminal capacitor array based on the different values ​​of the next high bit output by the SAR logic module; repeating this step until the value of the lowest bit of the SAR logic module is determined; Get the output of the SAR logic module; According to the different values ​​of the highest bit output by the SAR logic module, the decoding module decodes the output of the SAR logic module using different decoding methods.

9. The high-linearity high-bit prediction SAR ADC switching method according to claim 8, characterized in that: The SAR logic module controls the connection mode of switch S5 and switch S6 according to the value of the highest bit, specifically: When the highest bit value output by the SAR logic module is 1, switch S5 is connected to GND and switch S6 is connected to VREF; When the value of the highest bit output by the SAR logic module is 0, the switch S5 is connected to VREF, and the switch S6 is connected to GND.

10. The high-linearity high-bit predictive SAR ADC switch switching method according to claim 8, characterized in that: According to the different values ​​of the highest bit of the SAR logic module, the decoding module uses different decoding methods to decode the output of the SAR logic module, specifically: When the value of the highest bit of the SAR logic module output is 1, the decoding module decodes the output of the SAR logic module by subtracting the redundancy; When the value of the highest bit output by the SAR logic module is 0, the decoding module performs decoding by adding redundancy to the output of the SAR logic module.

Images