Switched capacitor circuit and pipeline analog-to-digital converter including same

Abstract

The invention relates to a switched capacitor circuit and a pipeline type analog-to-digital converter comprising the same. A switched capacitor circuit includes a sampling capacitor array, a control circuit and a charge transfer circuit. The sampling capacitor array is used for sampling an input voltage in a sampling stage. The control circuit is used for determining the magnitude of the preset voltage according to the input voltage and is used for adjusting the input voltage sampled by the sampling capacitor array according to the magnitude of the input voltage in the preset stage so as to generate the adjusted voltage. The charge transfer circuit is also configured to amplify the adjusted voltage during a charge transfer phase to generate an output voltage at an output terminal. The charge transfer circuit is also used for providing the preset voltage to the output end in the preset stage.

Description

Technical Field

[0001] The present disclosure relates to a switched capacitor circuit and a pipelined analog-to-digital converter including the same, and more particularly to a switched capacitor circuit capable of adjusting a preset voltage and a pipelined analog-to-digital converter including the same. Background Art

[0002] The operation of the switched capacitor circuit can be roughly divided into a sampling stage and a charge transfer stage. In the sampling stage, the switched capacitor circuit uses a capacitor to store the difference between the input voltage and the common voltage. Then, in the charge transfer stage, the switched capacitor circuit uses a charge pump to generate a corresponding output voltage at the output end based on the sampling result. Before the charge transfer stage, a preset voltage is used to reset the output end to clear the output voltage of the previous operation. In the existing practice, the preset voltage has a fixed size. However, there may be a large gap between the fixed preset voltage and the target value of the output voltage, so that the charge pump needs to use a longer time to adjust the output voltage to the target value, thereby limiting the operating speed of the switched capacitor circuit. Summary of the invention

[0003] The disclosed document provides a switched capacitor circuit, which includes a first sampling capacitor array, a control circuit, and a charge transfer circuit. The first sampling capacitor array is used to sample a first input voltage in a sampling phase. The control circuit is used to determine the size of a first preset voltage according to the first input voltage, and is used to adjust the first input voltage sampled by the first sampling capacitor array according to the size of the first input voltage in the preset phase to generate a first adjusted voltage. The charge transfer circuit is used to amplify the first adjusted voltage in the charge transfer phase to generate a first output voltage at a first output terminal. The charge transfer circuit is also used to provide the first preset voltage to the first output terminal in the preset phase.

[0004] The disclosed document provides a switching capacitor circuit, which includes a first sampling capacitor array, a control circuit and a charge transfer circuit. The first sampling capacitor array is used to sample a first input voltage in a sampling phase. The control circuit is used to determine the magnitude of a first reference voltage and a first preset voltage according to the relationship between the first input voltage and a plurality of voltage thresholds, and is used to couple the first reference voltage to the first input voltage sampled by the first sampling capacitor array in the preset phase to generate a first adjusted voltage. The charge transfer circuit is used to amplify the first adjusted voltage in the charge transfer phase to generate a first output voltage at a first output terminal. The charge transfer circuit is also used to provide the first preset voltage to the first output terminal in the preset phase.

[0005] The present disclosure document provides a pipeline analog-to-digital converter, which includes a plurality of converter circuit systems. Each converter circuit system includes a first sampling capacitor array, a control circuit, and a charge transfer circuit. The first sampling capacitor array is used to sample a first input voltage in a sampling phase. The control circuit is used to determine the magnitude of a first preset voltage according to the first input voltage, and is used to adjust the first input voltage sampled by the first sampling capacitor array according to the magnitude of the first input voltage in the preset phase to generate a first adjusted voltage. The charge transfer circuit is used to amplify the first adjusted voltage in the charge transfer phase to generate a first output voltage at a first output terminal. The charge transfer circuit is also used to provide the first preset voltage to the first output terminal in the preset phase.

[0006] One of the advantages of the above-mentioned switched capacitor circuit and pipelined analog-to-digital converter is that they have a high operating speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a simplified functional block diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0008] Figure 2 FIG. 4 is a waveform diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0009] Figure 3 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit according to an embodiment of the present disclosure.

[0010] Figure 4 FIG. 4 is a waveform diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0011] Figure 5 FIG. 4 is a waveform diagram of a switched capacitor circuit according to another embodiment of the present disclosure.

[0012] Figure 6 FIG. 4 is a simplified functional block diagram of a switched capacitor circuit according to an embodiment of the present disclosure.

[0013] Figure 7 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit according to an embodiment of the present disclosure.

[0014] Figure 8 FIG. 4 is a simplified functional block diagram of a pipelined analog-to-digital converter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0016] Figure 1The figure is a simplified functional block diagram of a switched capacitor circuit 100 according to an embodiment of the present disclosure. In some embodiments, the switched capacitor circuit 100 can be used as one of the multiple stages of a pipelined analog-to-digital converter (pipelined ADC). The switched capacitor circuit 100 includes a plurality of sampling capacitor arrays 110a-110b, a control circuit 120, and a charge transfer circuit 130. The switched capacitor circuit 100 is used to adjust the differential input voltages VIP and VIN to adjusted voltages VDP and VDN with smaller amplitudes, and to amplify the adjusted voltages VDP and VDN to differential output voltages VOP and VON to avoid dynamic distortion in the subsequent circuit (e.g., the next stage of the pipelined analog-to-digital converter).

[0017] The sampling capacitor array 110a is used to sample the input voltage VIP of the input terminal INP during the sampling phase. In some embodiments, the sampling capacitor array 110a includes capacitors C1-C2, wherein the first ends of the capacitors C1-C2 are each coupled to the input terminal INP through a switch, and the second ends of the capacitors C1-C2 are coupled to the charge transfer circuit 130. The sampling capacitor array 110b is used to sample the input voltage VIN of the input terminal INN during the sampling phase. In some embodiments, the sampling capacitor array 110b includes capacitors C3-C4, wherein the first ends of the capacitors C3-C4 are each coupled to the input terminal INN through a switch, and the second ends of the capacitors C3-C4 are coupled to the charge transfer circuit 130.

[0018] In some embodiments, the control circuit 120 includes an analog-to-digital converter 122 and a decoder 124. The analog-to-digital converter 122 is coupled to the input terminals INP and INN, and is used to generate a digital code Bi according to the input voltages VIP and VIN. The decoder 124 is coupled to the analog-to-digital converter 122, and is used to generate reference voltages VREP and VREN according to the digital code Bi. The reference voltages VREP and VREN are used to couple to the sampling capacitor arrays 110a and 110b, respectively, to adjust the input voltages VIP and VIN sampled by the sampling capacitor arrays 110a and 110b, thereby generating adjusted voltages VDP and VDN. In some embodiments, the decoder 124 includes a digital-to-analog converter.

[0019] The charge transfer circuit 130 includes a comparator 132, charge pumps 134a-134b, and feedback paths 136a-136b. The comparator 132 is used to compare the adjusted voltages VDP and VDN to generate control signals E1 and E2. The charge pump 134a is controlled by the control signal E1 and is used to generate an output voltage VOP at the output terminal OUP. The charge pump 134b is controlled by the control signal E2 and is used to generate an output voltage VON at the output terminal OUN. Specifically, a first input terminal (e.g., a non-inverting input terminal) of the comparator 132 is coupled to the second terminals of the capacitors C1-C2 to receive the adjusted voltage VDP. A second input terminal (e.g., an inverting input terminal) of the comparator 132 is coupled to the second terminals of the capacitors C3-C4 to receive the adjusted voltage VDN. The comparator 132 is used to generate control signals E1 and E2 according to (comparing) the adjusted voltages VDP and VDN, so as to control the charge pumps 134a-134b respectively using the control signals E1 and E2. For example, when the regulated voltages VDP and VDN are different, the comparator 132 uses the control signals E1 and E2 to enable the charge pumps 134a-134b. For another example, when the regulated voltages VDP and VDN are the same, the comparator 132 uses the control signals E1 and E2 to disable the charge pumps 134a-134b.

[0020] The enabled charge pumps 134 a ˜ 134 b are used to charge or discharge the output terminals OUP and OUN, respectively, to generate output voltages VOP and VON at the output terminals OUP and OUN, respectively.

[0021] Figure 2 Schematic diagram of waveforms of a switching capacitor circuit 100 according to an embodiment of the present disclosure document. In the present disclosure document, the enable level and the disable level of the signal are used to turn on and off the corresponding switch, respectively. First, in the sampling stage, the switching signal Φ1 is the enable level, and the switching signal Φ2, the preset signal P and the control signal E1~E2 are the disable levels. The first end of the capacitor C1~C2 is connected to the input terminal INP to receive (sample) the input voltage VIP. The first end of the capacitor C3~C4 is connected to the input terminal INN to receive (sample) the input voltage VIN. In addition, the second end of the capacitor C1~C4, the first input terminal of the comparator 132 and the second input terminal of the comparator 132 all receive a common voltage Vcm.

[0022] In the conversion phase, the switching signals Φ1-Φ2, the preset signal P and the control signals E1-E2 are all at the disabled level. The decoder 124 of the control circuit 120 determines the magnitudes of the reference voltages VREP and VREN and the magnitudes of the preset voltages VN and VP according to the input voltages VIN and VIP, wherein the preset voltages VN and VP are used to reset the output terminals OUP and OUN in subsequent operations.

[0023] Please refer to Figure 3,in Figure 3 FIG. 1 is a schematic diagram of input-output characteristics of a switched capacitor circuit 100 according to an embodiment of the present disclosure. Figure 3 The vertical axis is the difference between the output voltage VOP and the output voltage VON, and the horizontal axis is the difference between the input voltage VIP and the input voltage VIN (hereinafter referred to as “input voltage difference Vdif”). In some embodiments, the analog-to-digital converter 122 includes a plurality of comparators (not shown), which correspond to Figure 3 The voltage thresholds T1 to T13 are arranged in order from small to large. The voltage thresholds T1 to T13 define a plurality of voltage ranges A1 to A14. The number of the voltage thresholds T1 to T13 is only an example, and the disclosure document is not limited thereto.

[0024] The analog-to-digital converter 122 is used to use a plurality of comparators to compare the input voltage difference Vdif with the voltage thresholds T1 to T13. Therefore, the analog-to-digital converter 122 can determine the voltage range including the input voltage difference Vdif from the voltage ranges A1 to A14, and output a digital code Bi representing the voltage range. For example, when the input voltage difference Vdif is within the voltage range A1, the digital code Bi output by the analog-to-digital converter 122 is 0001; when the input voltage difference Vdif is within the voltage range A2, the digital code Bi output by the analog-to-digital converter 122 is 0010, and so on.

[0025] When the input voltage difference Vdif is in a voltage range indicated by an odd number (e.g., voltage range A1, A3, etc.), it means that after the charge transfer phase described later is over, the output voltage VOP is less than the output voltage VON. For example, the output voltage VOP is less than the common voltage Vcm (e.g., 0.5V), and the output voltage VON is greater than or equal to the common voltage Vcm. In this case, the decoder 124 sets the preset voltage VP to be less than the preset voltage VN according to the digital code Bi.

[0026] On the other hand, when the input voltage difference Vdif is in a voltage range indicated by an even number (e.g., voltage range A2, A4, etc.), it means that after the charge transfer phase described later is completed, the output voltage VOP is greater than the output voltage VON. For example, the output voltage VOP is greater than or equal to the common voltage Vcm, and the output voltage VON is less than the common voltage Vcm. In this case, the decoder 124 sets the preset voltage VP to be greater than the preset voltage VN according to the digital code Bi.

[0027] In other words, when the input voltage difference Vdif is in the Mth voltage range of the voltage range A1-A14, the decoder 124 sets the preset voltage VP to be less than (or greater than) the preset voltage VN. When the input voltage difference Vdif is in the M+1th voltage range of the voltage range A1-A14, the decoder 124 sets the preset voltage VP to be greater than (or less than) the preset voltage VN, where M is a positive integer.

[0028] In other words, when the input voltage difference Vdif is adjacent to the Jth voltage threshold (e.g., the first voltage threshold T1) of the voltage thresholds T1-T13 and is less than the Jth voltage threshold, the decoder 124 sets the preset voltage VP to be less than the preset voltage VN, where J is an odd number. When the input voltage difference Vdif is adjacent to the Jth voltage threshold and is greater than or equal to the Jth voltage threshold, the decoder 124 sets the preset voltage VP to be greater than the preset voltage VN.

[0029] In summary, the decoder 124 is used to determine which voltage range A1-A14 the input voltage difference Vdif is in according to the digital code Bi, and determine the magnitudes of the preset voltages VN and VP according to the determination result. Moreover, the preset voltage VN is inverse to the preset voltage VP, that is, when one is a high voltage, the other is a low voltage.

[0030] In addition, the decoder 124 is used to determine which of the voltage ranges B1 to B7 the input voltage difference Vdif is located in according to the digital code Bi, and determine the magnitudes of the reference voltages VREP and VREN according to the determination result. The voltage range B1 is composed of the voltage ranges A1 and A2; the voltage range B2 is composed of the voltage ranges A3 and A4, and so on.

[0031] In some embodiments, the relationship between the reference voltages VREP and VREN, the input voltage difference Vdif, and the voltage ranges B1 to B7 is shown in Table 1 below.

[0032] Table 1

[0033] Voltage range Reference voltage VREP Reference voltage VREN B1 0V 1V B2 0V (2 / 3)V B3 0V (1 / 3)V B4 0V 0V B5 (1 / 3)V 0V B6 (2 / 3)V 0V B7 1V 0V

[0034] Next, in the preset stage, the switch signal Φ2, the preset signal P and the control signals E1-E2 are at the enable level, and the switch signal Φ1 is at the disable level. The control circuit 120 is used to output a reference voltage VREP related to the magnitude of the input voltage VIP to the sampling capacitor array 110a, so as to adjust the input voltage VIP sampled by the sampling capacitor array 110a according to the magnitude of the input voltage VIP, thereby generating an adjusted voltage VDP. The control circuit 120 is also used to output a reference voltage VREN related to the magnitude of the input voltage VIN to the sampling capacitor array 110b, so as to adjust the input voltage VIN sampled by the sampling capacitor array 110b according to the magnitude of the input voltage VIN, thereby generating an adjusted voltage VDN.

[0035] In detail, in the preset stage, the comparator 132 forms a closed loop with the output terminals OUP and OUN, and the control circuit 120 couples the reference voltages VREP and VREN to the first terminal of the capacitor C2 and the first terminal of the capacitor C4 (i.e., coupled to the input voltage VIP sampled by the sampling capacitor array 110a, and coupled to the input voltage VIN sampled by the sampling capacitor array 110b) via the switch. In this way, the input voltage VIP sampled by the capacitors C1 and C2 is adjusted to the adjusted voltage VDP, and the input voltage VIN sampled by the capacitors C3 and C4 is adjusted to the adjusted voltage VDN. In addition, the charge transfer circuit 130 is used to transfer the preset voltages VP and VN to the output terminals OUP and OUN, respectively, in the preset stage.

[0036] In the charge transfer stage, the switching signal Φ2 and the control signals E1-E2 are at the enable level, and the switching signal Φ1 and the preset signal P are at the disable level. The comparator 132 is used to compare the adjusted voltage VDP with VDN, and control the charge pumps 134a-134b according to the comparison result. As mentioned above, when the reference voltages VREP and VREN are different, the comparator 132 enables the charge pumps 134a-134b. When the reference voltages VREP and VREN are the same, the comparator 132 disables the charge pumps 134a-134b.

[0037] It is worth mentioning that the decoder 124 is used to set one of the charge pumps 134a-134b as a current source and the other as a current sink according to the digital code Bi (i.e., according to the input voltages VIP and VIN, or according to the input voltage difference Vdif between the input voltages VIP and VIN). In the embodiment of the present disclosure document, the current source can charge the output terminal to increase the voltage of the output terminal, and the current sink can discharge the output terminal to reduce the voltage of the output terminal. When the preset voltage VP is greater than the preset voltage VN (i.e., when the output voltage VOP is greater than the output voltage VON), the charge pump 134a is a current sink and the charge pump 134b is a current source. On the other hand, when the preset voltage VP is less than the preset voltage VN (i.e., when the output voltage VOP is less than the output voltage VON), the charge pump 134a is a current source and the charge pump 134b is a current sink. Therefore, in the charge transfer stage, the charge transfer circuit 130 is used to amplify the adjusted voltages VDP and VDN to generate output voltages VOP and VON at the output terminals OUP and OUN through the cooperation of the comparator 132, the charge pump 134a and the charge pump 134b.

[0038] In summary, in the sampling phase, the sampling capacitor arrays 110a-110b are used to sample the input voltages VIP and VIN respectively. In the conversion phase, the control circuit 120 is used to determine the magnitudes of the reference voltage VREP, the reference voltage VREN, the preset voltage VP, and the preset voltage VN according to the input voltages VIN and VIP (for example, according to the input voltage difference Vdif between the input voltages VIN and VIP). In detail, in the conversion phase, the control circuit 120 is used to determine the magnitudes of the reference voltage VREP, the reference voltage VREN, the preset voltage VP, and the preset voltage VN according to the input voltages VIP and VIN. Figure 3 The relationship between the voltage thresholds T1 to T13 (for example, comparing the input voltage difference Vdif between the input voltage VIN and VIP with the voltage thresholds T1 to T13) determines the sizes of the reference voltage VREP, the reference voltage VREN, the preset voltage VP and the preset voltage VN.

[0039] In the preset stage, the control circuit 120 is used to adjust the input voltage VIP sampled by the sampling capacitor array 110a according to the size of the input voltage VIP to generate the adjusted voltage VDP, and is used to adjust the input voltage VIN sampled by the sampling capacitor array 110b according to the size of the input voltage VIN to generate the adjusted voltage VDN. In detail, the control circuit 120 is used to couple the reference voltage VREP to the input voltage VIP sampled by the sampling capacitor array 110a to generate the adjusted voltage VDP, and the control circuit 120 is used to couple the reference voltage VREN to the input voltage VIN sampled by the sampling capacitor array 110b to generate the adjusted voltage VDN.

[0040] In addition, the charge transfer circuit 130 provides preset voltages VP and VN to the output terminals OUP and OUN respectively in the preset phase, wherein the preset voltage VP is inverse to the preset voltage VN. The charge transfer circuit 130 also amplifies the adjusted voltages VDP and VDN in the charge transfer phase to generate output voltages VOP and VON at the output terminals OUP and OUN.

[0041] The following will be Figure 4 An operation example of the switched capacitor circuit 100 is described. Figure 4 FIG. 1 is a waveform diagram of a switched capacitor circuit 100 according to an embodiment of the present disclosure. Figure 4 In the embodiment of FIG. 1 , after the charge transfer phase ends, the output voltage VOP is smaller than the output voltage VON.

[0042] In the preset stage, the output terminal OUP (i.e., the output voltage VOP) is set to a lower preset voltage VP (e.g., 0V), and the output terminal OUN (i.e., the output voltage VON) is set to a higher preset voltage VN (e.g., 1V), wherein the output voltages VOP and VON are coupled to the adjusted voltages VDP and VDN through capacitors C1 and C3, respectively. Next, in the charge transfer stage, the charge pump 134a charges the output terminal OUP, and the charge pump 134b discharges the output terminal OUN to increase the output voltage VOP and reduce the output voltage VON until the adjusted voltages VDP and VDN are equal.

[0043] As can be seen from the above, the switched capacitor circuit 100 can determine the voltage range of the output voltages VOP and VON according to its input-output characteristics, and adjust the magnitudes of the preset voltages VP and VN accordingly. Therefore, the output voltages VOP and VON can quickly reach the target values ​​during the charge transfer phase, thereby enabling the switched capacitor circuit 100 to have a high operating speed.

[0044] Please refer to Figure 5 , Figure 5 FIG. 1 is a waveform diagram of a switched capacitor circuit according to another embodiment of the present disclosure. Figure 4 In the embodiment of Figure 5 In the embodiment, after the charge transfer stage is completed, the output voltage VOP is also lower than the output voltage VON, but the preset voltages VP and VN are respectively a fixed high voltage (e.g., 1V) and a low voltage (e.g., 0V). Therefore, the output voltages VOP and VON take a longer time to reach the target value, which will reduce the operating speed of the switched capacitor circuit.

[0045] Figure 6 FIG. 6 is a simplified functional block diagram of a switched capacitor circuit 600 according to an embodiment of the present disclosure. The switched capacitor circuit 600 includes a sampling capacitor array 610, a control circuit 620, and a charge transfer circuit 630. The sampling capacitor array 610 is similar to Figure 1 For the sake of brevity, the sampling capacitor array 110a is not repeated here. The control circuit 620 includes an analog-to-digital converter 622 and a decoder 624. The analog-to-digital converter 622 is coupled to the input terminal INP, and is used to generate a digital code Bi according to the input voltage VIP. The decoder 624 is coupled to the analog-to-digital converter 122, and is used to generate a reference voltage VREP according to the digital code Bi. The reference voltage VREP is used to couple to the sampling capacitor array 610, thereby generating an adjusted voltage VDP.

[0046] The charge transfer circuit 630 includes a comparator 632, a charge pump 634, and a feedback path 636. A first input terminal (e.g., a non-inverting input terminal) of the comparator 632 is coupled to the second terminals of the capacitors C1-C2 to receive the adjusted voltage VDP. A second input terminal (e.g., an inverting input terminal) of the comparator 632 is used to receive the common voltage Vcm. The comparator 632 is used to generate a control signal E1 according to the adjusted voltage VDP and the common voltage Vcm to control the charge pump 634 using the control signal E1. For example, when the adjusted voltage VDP and the common voltage Vcm are different, the comparator 632 uses the control signal E1 to enable the charge pump 634. For another example, when the adjusted voltage VDP and the common voltage Vcm are the same, the comparator 632 uses the control signal E1 to disable the charge pump 634. The feedback path 636 is similar to Figure 1 The feedback path 136a is not repeated here for the sake of brevity.

[0047] Please refer to Figure 7 ,in Figure 7 FIG. 6 is a schematic diagram of input-output characteristics of a switched capacitor circuit 600 according to an embodiment of the present disclosure. Figure 7 Similar to Figure 3 , the difference is Figure 7 The vertical axis and horizontal axis of are the output voltage VOP and the input voltage VIP, respectively. The analog-to-digital converter 622 is used to use multiple comparators to compare the input voltage VIP with multiple voltage thresholds T1-T13. Thus, the analog-to-digital converter 622 can determine the voltage range including the input voltage VIP from the voltage range A1-A14, and output a digital code Bi representing the voltage range.

[0048] The decoder 624 is used to determine which of the voltage ranges A1 to A14 the input voltage VIP is located in according to the digital code Bi, and determine the size of the preset voltage VP according to the determination result. When the input voltage VIP is located in a voltage range indicated by an odd number (e.g., voltage ranges A1, A3, etc.), the decoder 624 sets the preset voltage VP to be less than the common voltage Vcm according to the digital code Bi. On the other hand, when the input voltage VIP is located in a voltage range indicated by an even number (e.g., voltage ranges A2, A4, etc.), the decoder 624 sets the preset voltage VP to be greater than the common voltage Vcm according to the digital code Bi.

[0049] In other words, when the input voltage VIP is in the Mth voltage range of the voltage range A1 to A14, the decoder 624 will set the preset voltage VP to be less than (or greater than) the common voltage Vcm; when the input voltage VIP is in the M+1th voltage range of the voltage range A1 to A14, the decoder 624 will set the preset voltage VP to be greater than (or less than) the common voltage Vcm, where M is a positive integer.

[0050] In other words, when the input voltage VIP is adjacent to the Jth voltage threshold (e.g., the first voltage threshold T1) of the voltage thresholds T1-T13 and is less than the Jth voltage threshold, the decoder 624 sets the preset voltage VP to be less than the common voltage Vcm, where J is an odd number. When the input voltage VIP is adjacent to the Jth voltage threshold and is greater than or equal to the Jth voltage threshold, the decoder 624 sets the preset voltage VP to be greater than the common voltage Vcm.

[0051] The remaining operation modes and advantages of the control circuit 620 and the charge transfer circuit 630 are similar to those of Figure 1 For the sake of brevity, the control circuit 120 and the charge transfer circuit 130 are not repeated here.

[0052] In summary, in the sampling phase, the sampling capacitor array 610 is used to sample the input voltage VIP in the sampling phase. In the conversion phase, the control circuit 620 is used to determine the size of the preset voltage VP according to the input voltage VIP. For example, in the conversion phase, the control circuit 620 is used to determine the size of the preset voltage VP according to the input voltage VIP. Figure 7 The relationship between the voltage thresholds T1 to T13 (for example, comparing the input voltage VIP with the voltage thresholds T1 to T13) determines the magnitudes of the reference voltage VREP and the preset voltage VP.

[0053] In the preset stage, the control circuit 620 is used to adjust the input voltage VIP sampled by the sampling capacitor array 610 according to the magnitude of the input voltage VIP to generate the adjusted voltage VDP. For example, the control circuit 620 is used to couple the reference voltage VREP to the input voltage VIP sampled by the sampling capacitor array 610 to generate the adjusted voltage VDP.

[0054] In addition, the charge transfer circuit 630 provides the preset voltage VP to the output terminal OUP in the preset phase. The charge transfer circuit 130 also amplifies the adjusted voltage VDP in the charge transfer phase to generate an output voltage VOP at the output terminal OUP.

[0055] Figure 8 FIG. 8 is a simplified functional block diagram of a pipelined analog-to-digital converter 800 according to an embodiment of the present disclosure. The pipelined analog-to-digital converter 800 includes a sample-and-hold circuit 810, a plurality of converter circuit systems 820[1] to 820[3], a clock generator 830, and a digital correction circuit 840. The sample-and-hold circuit 810 is used to sample an input signal Vinput.

[0056] The converter circuit systems 820[1]-820[3] are used to sequentially convert the output of the previous stage into a plurality of digital codes Bi[1]-Bi[3], wherein the converter circuit system 820[1] is used to convert the sampling result of the sample-and-hold circuit 810 for the input signal Vinput. The number of converter circuit systems 820[1]-820[3] is only an example, and the present disclosure is not limited thereto.

[0057] The clock generator 830 is used to generate a plurality of clock signals to the sampling and holding circuit 810 and the converter circuit system 820[1]-820[3], so that the sampling and holding circuit 810 and the converter circuit system 820[1]-820[3] perform the above operations according to the clock signals. The digital correction circuit 840 is used to combine the digital codes Bi[1]-Bi[3] to generate the digital code DOUT. In some implementations, the digital correction circuit 840 is also used to correct the offset error and / or gain error of the converter circuit system 820[1]-820[3].

[0058] In some embodiments, each of the converter circuit systems 820[1]-820[3] may be composed of Figure 1 For example, the output voltage of the switched capacitor circuit 100 can be used as the input voltage of the next stage converter circuit system, and the digital code Bi generated by the switched capacitor circuit 100 can be used as a corresponding one of the digital codes Bi[1] to Bi[3]. In other embodiments, each of the converter circuit systems 820[1] to 820[3] can be Figure 6Therefore, the pipelined analog-to-digital converter 800 also has the advantage of fast operation speed.

[0059] Certain words are used in the specification and the scope of the patent application to refer to specific components. However, those with ordinary knowledge in the relevant technical field should understand that the same component may be referred to by different terms. The specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second element through other elements or connection means.

[0060] The description method of "and / or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes the meaning of the plural term.

[0061] The above are only preferred embodiments of the present disclosure, and various modifications and equivalent changes may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.

[0062]

Explanation of symbols

[0063] 100,600: Switched capacitor circuit

[0064] 110a, 110b, 610: sampling capacitor array

[0065] 120,620: Control circuit

[0066] 122,622:Analog-to-digital converter

[0067] 124,624:Decoder

[0068] 130,630: Charge transfer circuit

[0069] 132,632: Comparator

[0070] 134a,134b,634: Charge pump

[0071] 136a,136b,636: Feedback path

[0072] 800: Pipeline Analog-to-Digital Converter

[0073] 810: Sample and hold circuit

[0074] 820[1]~820[3]: Converter circuit system

[0075] 830: Clock generator

[0076] 840: Digital correction circuit

[0077] Bi,Bi[1]~Bi[3],DOUT: digital code

[0078] C1~C4: Capacitor

[0079] INN, INP: Input terminal

[0080] OUP, OUN: output end

[0081] T1~T13: voltage threshold

[0082] A1~A14: Voltage range

[0083] B1~B7: Voltage range

[0084] Vinput: input signal

[0085] VIP,VIN: Input voltage

[0086] VOP,VON: output voltage

[0087] VREP, VREN: reference voltage

[0088] VDP, VDN: adjusted voltage

[0089] Vcm: common voltage

[0090] VP,VN:Preset voltage

[0091] Vdif: Input voltage difference

[0092] Φ1,Φ2: switching signal

[0093] P: Preset signal

[0094] E1, E2: control signal.

Claims

1. A switched capacitor circuit, comprising: a first sampling capacitor array, used for sampling a first input voltage in a sampling phase; a control circuit for determining a magnitude of a first preset voltage according to the first input voltage, and for adjusting the first input voltage sampled by the first sampling capacitor array according to the magnitude of the first input voltage in a preset phase to generate a first adjusted voltage; and A charge transfer circuit is used for amplifying the first adjusted voltage in a charge transfer phase to generate a first output voltage at a first output terminal, and for providing the first preset voltage to the first output terminal in the preset phase.

2. The switched capacitor circuit of claim 1 , further comprising: a second sampling capacitor array, used for sampling a second input voltage during the sampling phase, The control circuit is used to determine the magnitude of the first preset voltage and the magnitude of a second preset voltage according to an input voltage difference between the first input voltage and the second input voltage, and is used to adjust the second input voltage sampled by the second sampling capacitor array according to the magnitude of the second input voltage in the preset stage to generate a second adjusted voltage. wherein the charge transfer circuit is used to amplify the second adjusted voltage in the charge transfer phase to generate a second output voltage at a second output terminal, and is used to provide the second preset voltage to the second output terminal in the preset phase, The first preset voltage is inverse to the second preset voltage.

3. The switched capacitor circuit according to claim 2, wherein: The control circuit includes: an analog-to-digital converter, configured to compare the input voltage difference with a plurality of voltage thresholds to determine a first voltage range including the input voltage difference from a plurality of voltage ranges, and to output a first digital code corresponding to the first voltage range, wherein the plurality of voltage ranges are defined by the plurality of voltage thresholds arranged in ascending order; and A decoder is used for determining the magnitude of the first preset voltage and the second preset voltage according to the first digital code.

4. The switched capacitor circuit according to claim 3, wherein: When the input voltage difference is in an Mth voltage range of the plurality of voltage ranges, the decoder is used to set the first preset voltage to be smaller than the second preset voltage, wherein M is a positive integer; as well as When the input voltage difference is located in an M+1th voltage range of the plurality of voltage ranges, the decoder is used for setting the first preset voltage to be greater than the second preset voltage.

5. The switched capacitor circuit according to claim 2, wherein: The charge transfer circuit comprises: a comparator for comparing the first adjusted voltage with the second adjusted voltage to generate a first control signal and a second control signal; a first charge pump, controlled by the first control signal and configured to generate the first output voltage at the first output terminal; as well as a second charge pump, controlled by the second control signal and configured to generate the second output voltage at the second output terminal, The control circuit is used for setting the first charge pump as one of a current source and a current sink according to the input voltage difference, and setting the second charge pump as the other of the current source and the current sink.

6. A switched capacitor circuit comprising: a first sampling capacitor array, used for sampling a first input voltage in a sampling phase; a control circuit for determining the magnitude of a first reference voltage and a first preset voltage according to the relationship between the first input voltage and a plurality of voltage thresholds, and for coupling the first reference voltage to the first input voltage sampled by the first sampling capacitor array in a preset phase to generate a first adjusted voltage; and A charge transfer circuit is used for amplifying the first adjusted voltage in a charge transfer phase to generate a first output voltage at a first output terminal, and for providing the first preset voltage to the first output terminal in the preset phase.

7. The switched capacitor circuit of claim 6, further comprising: a second sampling capacitor array, used for sampling a second input voltage during the sampling phase, The control circuit is used to compare an input voltage difference between the first input voltage and the second input voltage with the plurality of voltage thresholds to determine the magnitudes of the first reference voltage, the first preset voltage, a second reference voltage, and a second preset voltage, and is used to couple the second reference voltage to the second input voltage sampled by the second sampling capacitor array in the preset stage to generate a second adjusted voltage. wherein the charge transfer circuit is used to amplify the second adjusted voltage in the charge transfer phase to generate a second output voltage at a second output terminal, and is used to provide the second preset voltage to the second output terminal in the preset phase, The first preset voltage is inverse to the second preset voltage.

8. The switched capacitor circuit of claim 7 , wherein when the plurality of voltage thresholds are arranged in order from small to large, when the input voltage difference is adjacent to a J-th voltage threshold of the plurality of voltage thresholds and is smaller than the J-th voltage threshold, the control circuit is configured to set the first preset voltage to be smaller than the second preset voltage, wherein J is an odd number, When the multiple voltage thresholds are arranged in order from small to large, when the input voltage difference is adjacent to the Jth voltage threshold and is greater than or equal to the Jth voltage threshold, the control circuit is used to set the first preset voltage to be greater than the second preset voltage.

9. The switched capacitor circuit according to claim 7, wherein: The charge transfer circuit comprises: a comparator for comparing the first adjusted voltage with the second adjusted voltage to generate a first control signal and a second control signal; a first charge pump, controlled by the first control signal and configured to generate the first output voltage at the first output terminal; as well as a second charge pump, controlled by the second control signal and configured to generate the second output voltage at the second output terminal, The control circuit is used for setting the first charge pump as one of a current source and a current sink, and setting the second charge pump as the other of the current source and the current sink according to the first input voltage and the second input voltage.

10. A pipeline analog-to-digital converter, comprising a plurality of converter circuit systems, wherein each converter circuit system comprises: a first sampling capacitor array, used for sampling a first input voltage in a sampling phase; a control circuit for determining a magnitude of a first preset voltage according to the first input voltage, and for adjusting the first input voltage sampled by the first sampling capacitor array according to the magnitude of the first input voltage in a preset phase to generate a first adjusted voltage; and A charge transfer circuit is used for amplifying the first adjusted voltage in a charge transfer phase to generate a first output voltage at a first output terminal, and for providing the first preset voltage to the first output terminal in the preset phase.

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