Floating point multiplier based on FPGA (Field Programmable Gate Array), calculation method and equipment

Abstract

The invention relates to the field of floating-point multiplication, and particularly discloses a floating-point multiplier based on an FPGA, a calculation method and equipment, and the floating-point multiplier comprises a symbol calculation module which is used for determining the symbol of a target output floating-point number through an exclusive-OR gate and the symbol bits of a first input floating-point number and a second input floating-point number; the index addition module is used for adding the indexes of the first input floating-point number and the second input floating-point number and subtracting the deviation value of the corresponding format to obtain the index output of the target output floating-point number; the binary multiplier module is used for carrying out multiplication operation by using a Karatsuba algorithm and a Urdhva-Tiryagbhyam algorithm based on the mantissa bit widths of the first input floating-point number and the second input floating-point number so as to obtain a mantissa product of the target output floating-point number; and the result normalization module is used for performing normalization operation based on the mantissa product. The calculation delay can be reduced, and the percentage increase of the hardware area is also reduced.

Description

Technical Field

[0001] The present application relates to the field of floating-point multiplication, and in particular to a floating-point multiplier, a calculation method and a device based on FPGA. Background Art

[0002] In recent years, with the development and iteration of smart products, electronic devices are currently rapidly updating in the direction of small size, low power consumption and high speed. For electronic products, their speed depends on arithmetic operations. At the same time, in the current intelligent era, the application of technologies such as multimedia, artificial intelligence, machine learning, deep learning, and the Internet of Things also involves huge basic arithmetic calculations. Floating-point multiplication is a key operation in high-performance computing applications. However, floating-point operations are not only complex, but also require more hardware area and power consumption than fixed-point multipliers. With the improvement of precision, the area, delay and power consumption of floating-point multipliers will increase dramatically. In the past few decades, people have been working hard to improve the performance of floating-point calculations.

[0003] The traditional floating-point multiplier design method has certain limitations when facing the above problems, and often cannot meet the requirements of high speed, low power consumption and high precision. Although the IEEE 754 standard supports different floating-point formats, such as single-precision format, double-precision format, etc., the multiplier design of each format faces similar challenges. Therefore, it is necessary to propose a new floating-point multiplier to overcome the shortcomings of the existing technology. Summary of the invention

[0004] In order to solve the above problems, the present application proposes a floating-point multiplier, a calculation method and a device based on FPGA, wherein the floating-point multiplier is applied to floating-point multiplication in IEEE-754 format, including: a sign calculation module, used to determine the sign of the target output floating-point number through an XOR gate and the sign bits of the first input floating-point number and the second input floating-point number; an exponent addition module, used to add the exponents of the first input floating-point number and the second input floating-point number, and subtract a deviation value of the corresponding format to obtain the exponent output of the target output floating-point number; a binary multiplier module, based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, uses the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm to multiply the first mantissa of the first input floating-point number and the second mantissa of the second input floating-point number to obtain the mantissa product of the target output floating-point number; a result normalization module, used to perform a normalization operation based on the mantissa product, and the normalization operation includes at least one of shifting the mantissa and adjusting the exponent value.

[0005] In one example, based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm are used to perform a multiplication operation on the first mantissa of the first input floating-point number and the second mantissa of the second input floating-point number, specifically including: determining that the mantissa bit width satisfies a first preset condition, using an improved Karatsuba algorithm, and performing a divide-and-conquer multiplication operation on the first mantissa and the second mantissa until the mantissa product of the target output floating-point number is obtained, or the intermediate product result satisfies a second preset condition; when the intermediate product result satisfies the second preset condition, using the intermediate product result as an input to the improved Urdhva-Tiryagbhyam algorithm, and continuing the multiplication operation until the mantissa product of the target output floating-point number is obtained.

[0006] In one example, the use of the improved Karatsuba algorithm to perform a divide-and-conquer multiplication operation on the first mantissa and the second mantissa specifically includes: determining a length ratio between the first mantissa and the second mantissa; determining a numerical distribution of the first mantissa and the second mantissa, wherein the numerical distribution is the number of digits with a value of zero and the digit position in adjacent preset digits; based on the length ratio and the numerical distribution, determining a split point between the first mantissa and the second mantissa, and splitting the first mantissa and the second mantissa according to the split point.

[0007] In one example, an improved Karatsuba algorithm is used to perform a divide-and-conquer multiplication operation on the first mantissa and the second mantissa, specifically including: setting a parallel computing unit, a register, and a control logic module in the FPGA-based floating-point multiplier; the parallel computing unit is used to concurrently execute computing tasks within the same clock cycle; the computing tasks include multiplication calculations, addition calculations, and result merging; the registers are used to temporarily store intermediate results and transfer data between different computing tasks; the control logic module is used to manage the startup, completion, and error handling of each computing task.

[0008] In one example, the intermediate product result is used as an input to the improved Urdhva-Tiryagbhyam algorithm. Before continuing the multiplication operation, the binary multiplier module is also used to: when using the Urdhva-Tiryagbhyam algorithm, determine the number of calculations corresponding to different preset calculation tasks, wherein the preset calculation tasks include the same numerical pairs appearing at different time points or different positions and fixed digit combinations appearing in the multiplication tasks; and store the input item group of the preset calculation task, the type of adder used, and the calculation result after hash mapping in a preset calculation table.

[0009] In one example, the intermediate product result is used as an input of the improved Urdhva-Tiryagbhyam algorithm to continue the multiplication operation, specifically including: determining the local correlation between the intermediate product result and each input item group in the preset calculation table; if there is a local correlation between an input item group and the intermediate product result that is higher than a first preset threshold and lower than a second preset threshold, reading the adder model corresponding to the input item group in the preset calculation table, and using the adder model as the adder of the intermediate product result; if the local correlation is higher than the second preset threshold, reading the corresponding calculation result in the preset calculation table as the calculation result of the partial calculation task of the first mantissa and the second mantissa.

[0010] In one example, the binary multiplier module is provided with multiple types of adders, and the types of the adders include at least one of a carry propagate adder, a carry save adder, a carry select adder, and a carry look-ahead adder.

[0011] In one example, the binary multiplier module is also used to dynamically select the type of adder according to the bit width and data characteristics of the intermediate product result; the dynamic selection of the type of adder according to the bit width and data characteristics of the intermediate product result specifically includes: determining the addition carry probability of the intermediate product result based on a vector machine model to determine the first adder expectation of the intermediate product result; determining the second adder expectation of the intermediate product result based on the bit width of the intermediate product result; determining the time limit of the addition operation based on the delay requirement set by the user, and determining the third adder expectation of the intermediate product result based on the time limit; determining the fourth adder expectation of the intermediate product result based on the number and type of available hardware resources; determining the adder type corresponding to the intermediate product result based on the first adder expectation, the second adder expectation, the third adder expectation, and the fourth adder expectation.

[0012] The present application also provides a calculation method of a floating-point multiplier based on FPGA, including: determining the sign of a target output floating-point number through an XOR gate and the sign bits of a first input floating-point number and a second input floating-point number; adding the exponents of the first input floating-point number and the second input floating-point number, and subtracting a deviation value in a corresponding format to obtain the exponent output of the target output floating-point number; based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, using the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm, multiplying a first mantissa of the first input floating-point number and a second mantissa of the second input floating-point number to obtain the mantissa product of the target output floating-point number; performing a normalization operation based on the mantissa product, the normalization operation including at least one of shifting the mantissa and adjusting the exponent value.

[0013] The present application also provides a computing device based on an FPGA floating-point multiplier, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: determining the sign of a target output floating-point number through an XOR gate and the sign bits of a first input floating-point number and a second input floating-point number; adding the exponents of the first input floating-point number and the second input floating-point number, and subtracting a deviation value of a corresponding format to obtain the exponent output of the target output floating-point number; based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, multiplying a first mantissa of the first input floating-point number and a second mantissa of the second input floating-point number using a Karatsuba algorithm and an Urdhva-Tiryagbhyam algorithm to obtain a mantissa product of the target output floating-point number; performing a normalization operation based on the mantissa product, the normalization operation including at least one of shifting the mantissa and adjusting the exponent value.

[0014] The method proposed in this application can bring the following beneficial effects: 1. By combining the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm, the time for mantissa multiplication can be significantly reduced, thereby improving the speed of the entire floating-point multiplier. Especially in high-speed application scenarios such as real-time signal processing and graphics rendering, this fast floating-point multiplication capability can greatly improve the performance and response speed of the system.

[0015] 2. Compared with the traditional floating-point multiplier design method, the algorithm combination adopted in this application reduces the number of multipliers and the hardware complexity. In particular, when processing high-precision floating-point operations, a large number of complex hardware circuits are not required to implement multiplication operations, thereby reducing the chip area requirements. For hardware platforms such as FPGAs, this can more effectively utilize limited resources and reduce manufacturing costs.

[0016] 3. Due to the reduction of hardware complexity and the increase of operation speed, the power consumption of the floating-point multiplier proposed in this application is also reduced accordingly during operation. In power-sensitive applications, such as mobile devices and embedded systems, this low power consumption feature can extend the battery life of the device and improve the practicality of the device.

[0017] 4. The floating-point multiplier design proposed in this application is based on the IEEE-754 standard format and has good compatibility with existing computer systems and software. It can be easily integrated into various computer hardware platforms and applications without large-scale modifications to existing systems, thereby reducing application costs and promotion difficulties. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 This is a schematic diagram of the structure of a floating-point multiplier based on FPGA in an embodiment of the present application; Figure 2 A schematic diagram of a calculation process in a floating-point multiplier based on FPGA in an embodiment of the present application; Figure 3 A schematic diagram of a calculation process in a binary multiplier module in an embodiment of the present application; Figure 4 A schematic diagram of a calculation process of a Karatsuba multiplier in an embodiment of the present application; Figure 5 This is a schematic diagram of the hardware structure of a 4x4 Urdhva-Tiryagbhyam multiplier in an embodiment of the present application; Figure 6 The figure is a flowchart of a calculation method of a floating-point multiplier based on FPGA in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0020] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0021] like Figure 1 and Figure 2 As shown, the present application provides a floating-point multiplier based on FPGA, which is applied to floating-point multiplication in IEEE-754 format. At this time, a floating-point number consists of a sign, an exponent, a mantissa and an exponential base. For the multiplication operation of two floating-point numbers, the final result is obtained by calculating the product of the sign, the exponent and the mantissa respectively. The floating-point multiplier includes: The sign calculation module is used to determine the sign of the target output floating-point number through the XOR gate and the sign bits of the first input floating-point number and the second input floating-point number. Specifically, the sign calculation module determines the sign of the product according to the most significant bit (MSB) of the input floating-point number. For example, a simple XOR gate can be used as a sign calculator. If the sign bits of the two floating-point numbers are the same, the sign of the product is positive; if the sign bits are different, the sign of the product is negative. This XOR gate-based sign calculation method is simple and efficient, does not require a complex circuit structure, can quickly determine the sign of the product, and saves time for the entire floating-point multiplication operation.

[0022] The exponential addition module is used to add the exponents of the first input floating point number and the second input floating point number, and subtract the deviation value of the corresponding format to obtain the exponential output of the target output floating point number. Specifically, the exponential addition module is used to add the input exponents and subtract the deviation value of the corresponding format to obtain the actual product exponent. In the IEEE-754 standard, the exponent of the single-precision format is 8 bits wide and the deviation value is 127; the exponent of the double-precision format is 11 bits wide and the deviation value is 1023. Since the calculation time of the mantissa multiplication operation is much longer than that of the exponential addition, a simple ripple carry adder and ripple borrow subtractor can be used to perform the addition and subtraction operations of the exponent, which occupies less resources and can reduce the hardware complexity and cost.

[0023] The binary multiplier module uses the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm to perform multiplication operation on the first mantissa of the first input floating point number and the second mantissa of the second input floating point number based on the mantissa bit width of the first input floating point number and the second input floating point number, so as to obtain the mantissa product of the target output floating point number. In floating point multiplication, the most important and complicated part is the mantissa multiplication. The multiplication operation requires more time than the addition operation. And as the number of bits increases, it consumes more area and time. In order to reduce the area of ​​the multiplication operation and improve the efficiency of the multiplication operation, the present invention adopts a method combining the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm.

[0024] The result normalization module is used to perform a normalization operation based on the mantissa product, and the normalization operation includes at least one of shifting the mantissa and adjusting the exponent value. In the IEEE-754 floating point representation, there is a hidden bit in the mantissa, which is usually 1. This hidden bit has a special processing method during storage and operation. When the highest bit of the multiplication result is not the first bit to the left of the hidden bit, the result needs to be normalized to meet the requirements of the IEEE-754 standard format. The operation of the result normalization module includes shifting the mantissa and adjusting the exponent value accordingly. If the highest bit of the multiplication result is not the first bit to the left of the hidden bit, the result is shifted to the left until the highest bit is 1 (non-zero is 1 under base 2). The exponent value increases by 1 each time a left shift operation is performed.

[0025] This application combines the advantages of the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm, which not only reduces the delay, but also reduces the percentage increase of the hardware area, which has significant advantages over the traditional method.

[0026] Specifically, Figure 3As shown, when the binary multiplier module performs floating-point multiplication calculation, since the Karatsuba algorithm is a divide-and-conquer algorithm, it is suitable for processing multiplication operations of high digits. When the input bit width is large, the algorithm is more efficient. However, when the bit width is low, the efficiency of the Karatsuba algorithm is not high. In order to solve this problem, the present invention uses the Urdhva-Tiryagbhyam algorithm suitable for low bit width when the bit width is low. Specifically, it is determined that the mantissa bit width meets the first preset condition (such as when the bit width of the operands is greater than eight bits), and the improved Karatsuba algorithm is used to perform a divide-and-conquer multiplication operation on the first mantissa and the second mantissa until the mantissa product of the target output floating-point number is obtained, or the intermediate product result meets the second preset condition (such as when the bit width of the operands is eight bits). When the intermediate product result meets the second preset condition, the intermediate product result is used as the improved Urdhva-Tiryagbhyam algorithm input, and the multiplication operation is continued until the mantissa product of the target output floating-point number is obtained.

[0027] The difference between the improved Karatsuba algorithm in this application and the existing Karatsuba algorithm is described here: The traditional Karatsuba algorithm uses a fixed splitting method to divide two large integers into two parts each, and then recursively calculates the results of each group of subproblems. This method is suitable for most cases, but it may not be the best choice in some special cases. For example, when one operand is much larger than the other, directly applying Karatsuba may lead to unnecessary complexity.

[0028] Therefore, the present application introduces a dynamic segmentation strategy to adaptively adjust the segmentation point according to the characteristics of the input data. For unbalanced operands, larger numbers can be segmented asymmetrically so that each recursive call can maximize the speed advantage of the addition operation. This approach reduces unnecessary recursive levels and reduces overall delay. When performing asymmetric segmentation, the length ratio between the first mantissa (or the first operand in the calculation process) and the second mantissa (the second operand in the calculation process) can be determined, and the numerical distribution of the first mantissa and the second mantissa can be determined. The numerical distribution is the number of digits with zero values ​​in adjacent preset digits and the digit position. Then, based on the length ratio and the numerical distribution, the segmentation point of the first mantissa and the second mantissa is determined, and the first mantissa and the second mantissa are segmented according to the segmentation point. When determining the segmentation point, the corresponding segmentation expectation when the segmentation point is set at different positions can be calculated by preset weights, and the appropriate segmentation point can be selected by segmentation expectation. In hardware implementation, the segmentation point can be determined according to the performance indicators of the hardware (such as the delay of the adder, the delay of the multiplier, etc.). If the performance overhead of multiplication and addition operations of operands of different lengths on the hardware is known, the split point can be selected based on this information to minimize the total computational overhead. The asymmetric splitting proposed in this application can reduce the recursive level, thereby simplifying the calculation process. For unbalanced operands, asymmetric splitting can split larger numbers into parts that are closer to smaller numbers, thereby reducing the number of recursive calls. At the same time, the addition load is balanced and the parallel processing capability is improved. Through asymmetric splitting, the addition tasks generated by each recursion can be more evenly distributed to avoid too many or too few addition requirements in certain stages. It also adapts to operands of different sizes and avoids waste of resources. For operands with large length differences, symmetric splitting may cause part of the computing resources to be wasted on processing redundant data. Asymmetric splitting can be flexibly adjusted according to the actual input to ensure that each part can be processed most effectively.

[0029] At the same time, the traditional Karatsuba algorithm is executed serially, that is, the next step must be started after the previous step is completed. This will lead to a long delay time in hardware implementation, especially when processing high-precision numerical values. Therefore, the present application adopts a multi-stage pipeline structure to decompose the tasks of each stage into smaller subtasks and execute these subtasks in parallel. Specifically, multiple parallel units can be set in the hardware, each responsible for different sub-multiplication and addition operations. This can not only reduce the overall delay, but also improve the throughput, because multiple multiplications can be performed at the same time. Specifically, a parallel computing unit, a register, and a control logic module are set in the binary multiplier module of the floating-point multiplier provided by the present application. The parallel computing unit here is used to concurrently execute computing tasks in the same clock cycle, and the computing tasks include multiplication calculations, addition calculations, and result merging. The registers here are used to temporarily store intermediate results and transfer data between different computing tasks, and the control logic module is used to manage the startup, completion, and error handling of each computing task.

[0030] In one embodiment, the existing Urdhva-Tiryagbhyam algorithm is essentially a vertical and cross multiplication method, which quickly generates partial products through a series of rules. However, for some common patterns or repeated data combinations, recalculating each time will cause a waste of resources.

[0031] Therefore, in the improved Urdhva-Tiryagbhyam algorithm in the present application, when generating partial products, the local correlation of the data can be used for pre-calculation and caching. At the same time, a pre-calculation table mechanism is added to pre-calculate partial multiplication results and store them in a small lookup table. Whenever the same pattern of data is encountered, the result can be read directly from the lookup table to avoid repeated calculations. The lookup table can be customized according to the expected application scenario to cover the most frequently occurring data patterns. In addition, the size of the lookup table can be reduced in combination with compression technology to save memory space. Specifically, when using the Urdhva-Tiryagbhyam algorithm, the number of calculations corresponding to different preset calculation tasks can be determined, where the preset calculation tasks include the same numerical pairs that appear at different time points or different positions and fixed digit combinations that appear in multiplication tasks; then the input item group of the preset calculation task, the type of adder used, and the calculation result after hash mapping are stored in the preset calculation table.

[0032] Further, when the improved Urdhva-Tiryagbhyam algorithm is used for calculation, it is necessary to determine the local correlation between the intermediate product result and each input item group in the preset calculation table. If there is a local correlation between the input item group and the intermediate product result that is higher than the first preset threshold and lower than the second preset threshold, the adder model corresponding to the input item group is read in the preset calculation table, and the adder model is used as the adder of the intermediate product result. If the local correlation is higher than the second preset threshold, the corresponding calculation result is read in the preset calculation table as the calculation result of the partial calculation task of the first mantissa and the second mantissa. The calculation process of the local correlation is explained here: by traversing the two input operands, it can be determined whether there are repeated values, the same bit-level patterns, or local digits with mathematical characteristics in the two operands. The bit-level pattern here refers to certain bit combinations that frequently appear in multiplication operations, for example, the lower or upper bits are always fixed. The mathematical characteristics here refer to patterns formed based on mathematical laws, such as input operands being powers of another input operand or historical operands, multiples, etc.

[0033] In one embodiment, in order to speed up the calculation process of the floating-point multiplier, the floating-point multiplier provided in the present application is provided with multiple types of adders. When performing addition calculations, the adder can be selected based on the characteristics of the input operand. In one embodiment, the adder types provided in the present application include a carry propagate adder, a carry save adder, a carry select adder, and a carry look-ahead adder.

[0034] Each adder corresponds to different characteristics of the input operands. Specifically, the carry-propagation adder is suitable for small-scale or low-latency addition operations. The carry-save adder is suitable for accumulating the results of multiple addition operations and reducing the carry-propagation delay. The carry-select adder is suitable for large bit-width data and can quickly generate the final result. The carry-lookahead adder is suitable for delay-sensitive applications, such as high-speed operations. When selecting an adder, a set of selection criteria can be defined to determine the type of adder that best suits the current situation. Here is an example of the criteria: the type of adder is dynamically selected based on the bit width and data characteristics of the intermediate product result, specifically including: Determine the probability of addition carry of the intermediate product result based on the vector machine model to determine the first adder expectation of the intermediate product result; determine the second adder expectation of the intermediate product result based on the bit width of the intermediate product result; determine the time limit of the addition operation based on the delay requirement set by the user, and determine the third adder expectation of the intermediate product result based on the time limit; determine the fourth adder expectation of the intermediate product result based on the number and type of available hardware resources; finally, determine the adder type corresponding to the intermediate product result based on the first adder expectation, the second adder expectation, the third adder expectation, and the fourth adder expectation. Finally, the dynamic selection process of the adder type can be managed by using a decision tree or a finite state machine, in which each node or state in the decision tree or finite state machine represents a possible selection condition, and the edge or conversion represents the transition from one condition to another.

[0035] Figure 6 A flowchart of a calculation method of a floating-point multiplier based on FPGA provided in one or more embodiments of this specification. The process can be executed by a computing device in the corresponding field, and some input parameters or intermediate results in the process allow manual intervention and adjustment to help improve accuracy.

[0036] The analysis method involved in the embodiments of the present application can be implemented by a terminal device or a server, and the present application does not impose any special restrictions on this. For the convenience of understanding and description, the following embodiments are described in detail by taking a server as an example.

[0037] It should be noted that the server can be a single device or a system composed of multiple devices, that is, a distributed server, and this application does not make any specific limitations on this.

[0038] like Figure 6 As shown, the embodiment of the present application provides a calculation method of a floating-point multiplier based on FPGA, including: S601: Determine the sign of a target output floating-point number through an XOR gate and the sign bits of a first input floating-point number and a second input floating-point number.

[0039] S602: Add the exponents of the first input floating-point number and the second input floating-point number, and subtract a deviation value in a corresponding format to obtain an exponential output of the target output floating-point number.

[0040] S603: Based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, use the Karatsuba algorithm and the Urdhva-Tiryagbhyam algorithm to multiply the first mantissa of the first input floating-point number and the second mantissa of the second input floating-point number to obtain the mantissa product of the target output floating-point number.

[0041] S604: Perform a normalization operation based on the mantissa product, where the normalization operation includes at least one of shifting the mantissa and adjusting the exponent value.

[0042] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0043] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0044] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0045] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0046] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0047] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0048] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0049] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0050] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0051] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0052] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A floating-point multiplier based on FPGA, characterized in that: Applies to floating-point multiplication in IEEE-754 format, including: A sign calculation module, used for determining the sign of the target output floating point number through an XOR gate and the sign bits of the first input floating point number and the second input floating point number; An exponential addition module, used for adding the exponents of the first input floating point number and the second input floating point number, and subtracting a deviation value of a corresponding format to obtain an exponential output of the target output floating point number; A binary multiplier module, based on the mantissa bit widths of the first input floating point number and the second input floating point number, uses a Karatsuba algorithm and an Urdhva-Tiryagbhyam algorithm to perform a multiplication operation on a first mantissa of the first input floating point number and a second mantissa of the second input floating point number to obtain a mantissa product of the target output floating point number; The result normalization module is used to perform a normalization operation based on the mantissa product, wherein the normalization operation includes at least one of shifting the mantissa and adjusting the exponent value.

2. The FPGA-based floating-point multiplier according to claim 1, wherein: The method of performing a multiplication operation on a first mantissa of the first input floating point number and a second mantissa of the second input floating point number by using a Karatsuba algorithm and an Urdhva-Tiryagbhyam algorithm based on the mantissa bit widths of the first input floating point number and the second input floating point number specifically includes: Determine that the mantissa bit width satisfies a first preset condition, and use an improved Karatsuba algorithm to perform a divide-and-conquer multiplication operation on the first mantissa and the second mantissa until the mantissa product of the target output floating-point number is obtained, or an intermediate product result satisfies a second preset condition; When the intermediate product result satisfies the second preset condition, the intermediate product result is used as an input of the improved Urdhva-Tiryagbhyam algorithm, and the multiplication operation is continued until the mantissa product of the target output floating-point number is obtained.

3. The FPGA-based floating-point multiplier according to claim 2, characterized in that: The step of using the improved Karatsuba algorithm to perform a divide-and-conquer multiplication operation on the first mantissa and the second mantissa specifically includes: determining a length ratio between the first mantissa and the second mantissa; Determine the numerical distribution of the first mantissa and the second mantissa, wherein the numerical distribution is the number of digits with zero values ​​and the digit positions in adjacent preset digits; Based on the length ratio and the numerical distribution, a segmentation point between the first mantissa and the second mantissa is determined, and the first mantissa and the second mantissa are segmented according to the segmentation point.

4. The FPGA-based floating-point multiplier according to claim 2, characterized in that: Using the improved Karatsuba algorithm, a divide-and-conquer multiplication operation is performed on the first mantissa and the second mantissa, specifically including: A parallel computing unit, a register, and a control logic module are provided in the FPGA-based floating-point multiplier; The parallel computing unit is used to concurrently execute computing tasks in the same clock cycle; the computing tasks include multiplication calculation, addition calculation and result merging; The registers are used to temporarily store intermediate results and transfer data between different computing tasks; The control logic module is used to manage the initiation, completion and error handling of each computing task.

5. The FPGA-based floating-point multiplier according to claim 2, characterized in that: The intermediate product result is used as an input of the improved Urdhva-Tiryagbhyam algorithm, and before continuing the multiplication operation, the binary multiplier module is further used for: When using the Urdhva-Tiryagbhyam algorithm, determining the number of calculations corresponding to different preset calculation tasks, wherein the preset calculation tasks include the same value pairs appearing at different time points or different positions and the fixed digit combination appearing in the multiplication task; The input item group of the preset calculation task, the type of adder used, and the calculation result after hash mapping are stored in a preset calculation table.

6. The FPGA-based floating-point multiplier according to claim 5, characterized in that: The step of using the intermediate product result as an input of the improved Urdhva-Tiryagbhyam algorithm and continuing the multiplication operation specifically includes: Determine the local correlation between the intermediate product result and each input item group in the preset calculation table; If there is a local correlation between an input item group and the intermediate product result that is higher than a first preset threshold and lower than a second preset threshold, reading an adder model corresponding to the input item group in the preset calculation table, and using the adder model as an adder for the intermediate product result; If the local correlation is higher than a second preset threshold, the corresponding calculation result is read from the preset calculation table as the calculation result of the partial calculation task of the first mantissa and the second mantissa.

7. The FPGA-based floating-point multiplier according to claim 1, characterized in that: The binary multiplier module is provided with multiple types of adders, and the types of the adders include at least one of a carry propagate adder, a carry save adder, a carry select adder, and a carry lookahead adder.

8. The FPGA-based floating-point multiplier according to claim 7, characterized in that: The binary multiplier module is also used to dynamically select the type of adder according to the bit width and data characteristics of the intermediate product result; The method of dynamically selecting the type of adder according to the bit width and data characteristics of the intermediate product result specifically includes: Determine the addition carry probability of the intermediate product result based on the vector machine model to determine the first adder expectation of the intermediate product result; determining a second adder expectation of the intermediate product result based on a bit width of the intermediate product result; determining a time limit for the addition operation based on a latency requirement set by a user, and determining a third adder expectation of the intermediate product result based on the time limit; determining a fourth adder expectation of the intermediate product result based on the amount and type of available hardware resources; Based on the first adder expectation, the second adder expectation, the third adder expectation, and the fourth adder expectation, the adder type corresponding to the intermediate product result is determined.

9. A calculation method of a floating-point multiplier based on FPGA, characterized in that: include: Determine the sign of the target output floating point number through an XOR gate and the sign bits of the first input floating point number and the second input floating point number; Adding the exponents of the first input floating point number and the second input floating point number, and subtracting a deviation value of a corresponding format, to obtain an exponential output of the target output floating point number; Based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, a first mantissa of the first input floating-point number and a second mantissa of the second input floating-point number are multiplied by a Karatsuba algorithm and an Urdhva-Tiryagbhyam algorithm to obtain a mantissa product of the target output floating-point number; A normalization operation is performed based on the mantissa product, wherein the normalization operation includes at least one of a shift operation on the mantissa and an adjustment of an exponent value.

10. A computing device based on an FPGA floating-point multiplier, characterized in that: include: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute: Determine the sign of the target output floating point number through an XOR gate and the sign bits of the first input floating point number and the second input floating point number; Adding the exponents of the first input floating point number and the second input floating point number, and subtracting a deviation value of a corresponding format, to obtain an exponential output of the target output floating point number; Based on the mantissa bit widths of the first input floating-point number and the second input floating-point number, a first mantissa of the first input floating-point number and a second mantissa of the second input floating-point number are multiplied by a Karatsuba algorithm and an Urdhva-Tiryagbhyam algorithm to obtain a mantissa product of the target output floating-point number; A normalization operation is performed based on the mantissa product, wherein the normalization operation includes at least one of a shift operation on the mantissa and an adjustment of an exponent value.

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