Memory element with tapered bit line contact

Abstract

The present disclosure provides a memory device, including: a semiconductor substrate having an active region; and a word line crossing the active region. The memory element also includes a first source / drain region and a second source / drain region disposed in the active region and on opposite sides of the word line. The memory element also includes a bit line contact disposed on the first source / drain region and electrically connected to the first source / drain region. The bit line contact point has a tapered profile. Further, the memory element includes a capacitor contact disposed on the second source / drain region and electrically connected to the second source / drain region.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 219,241 (i.e., the priority date is "July 7, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a memory element and a method for manufacturing the same, and more particularly to a memory element having a tapered bit line contact and a method for manufacturing the same. Background Art

[0003] Due to its simple structure, dynamic random access memory (DRAM) can provide more memory cells per unit chip area than other types of memory, such as static random access memory (SRAM). A DRAM is composed of multiple DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor to regulate when the capacitor is charged or discharged. During a read operation, the word line (WL) is asserted and the transistor is turned on. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via the bit line (BL). During a write operation, the data to be written is provided on the BL while the WL is asserted.

[0004] In order to meet the demand for greater memory storage, the size of DRAM memory cells continues to shrink, resulting in a significant increase in the packaging density of these DRAMs. However, the manufacture and integration of memory components involve many complex steps and operations. Integration in memory components is becoming increasingly complex. The increased complexity of manufacturing and integration of memory components may lead to defects. Therefore, there is a need to continuously improve the structure and manufacturing process of memory components to address their defects and improve performance.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] One embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having an active region; and a word line extending across the active region. The memory element also includes a first source / drain region and a second source / drain region, which are arranged in the active region and on opposite sides of the word line. The memory element also includes a bit line contact point, which is arranged on the first source / drain region and electrically connected to the first source / drain region. The bit line contact point has a tapered profile. In addition, the memory element includes a capacitor contact point, which is arranged on the second source / drain region and electrically connected to the second source / drain region.

[0007] In one embodiment, the memory element further comprises a dielectric cap layer disposed on the semiconductor substrate, wherein the capacitor contact and the bit line contact pass through the dielectric cap layer. In addition, the memory element comprises a bit line contact spacer disposed between the dielectric cap layer and the bit line contact. In one embodiment, the bit line contact spacer and the dielectric cap layer comprise different materials. In one embodiment, the memory element further comprises a capacitor disposed on the capacitor contact and electrically connected to the capacitor contact.

[0008] In one embodiment, the memory element further comprises a bit line disposed at the bit line contact point and electrically connected to the bit line contact point. In one embodiment, the bit line contact point gradually decreases from the bit line to the semiconductor substrate. In one embodiment, an upper width of the bit line contact point is substantially the same as a lower width of the bit line. In one embodiment, the upper width of the bit line contact point is greater than a lower width of the bit line contact point.

[0009] Another embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having an active region; and a word line extending across the active region. The memory element also includes a first source / drain region and a second source / drain region, which are arranged in the active region and on opposite sides of the word line. The memory element also includes a dielectric cap layer covering the word line; and a bit line contact point passing through the dielectric cap layer to contact the first source / drain region. An upper width of the bit line contact point is greater than a lower width of the bit line contact point. In addition, the memory element includes a capacitor contact point passing through the dielectric cap layer to contact the second source / drain region.

[0010] In one embodiment, the bit line contact has a tapered profile along a direction from an upper surface of the dielectric cap layer to the first source / drain region. In one embodiment, a ratio of the upper width to the lower width of the bit line contact is in a range of about 1.45 to about 1.85. In one embodiment, an angle between an upper surface and a sidewall of the bit line contact is in a range of about 73 degrees to about 81 degrees.

[0011] In one embodiment, the memory element further comprises a bit line contact point spacer, separating the bit line contact point from the dielectric cap layer. In one embodiment, the memory element further comprises a capacitor disposed on the capacitor contact point; and a bit line disposed on the bit line contact point. In one embodiment, the memory element further comprises a bit line spacer disposed on a side wall of the bit line, wherein the bit line spacer is in direct contact with the bit line contact point spacer.

[0012] Another embodiment of the present disclosure provides a method for preparing a memory element. The preparation method includes forming a doped region in a semiconductor substrate; and forming a word line to cross the doped region, so that a first source / drain region and a second source / drain region are formed in the doped region and on opposite sides of the word line. The preparation method also includes forming a dielectric cap layer to cover the word line, the first source / drain region and the second source / drain region; and forming a first opening through the dielectric cap layer to expose the first source / drain region. The first opening has a tapered profile along a direction from an upper surface of the dielectric cap layer to the first source / drain region. The preparation method also includes forming a bit line contact point in the first opening; and forming a second opening through the dielectric cap layer to expose the second source / drain region. In addition, the preparation method includes forming a capacitor contact point in the second opening.

[0013] In one embodiment, an upper width of the first opening is greater than a lower width of the first opening. In one embodiment, the word line includes a gate electrode and a gate dielectric layer surrounding the gate electrode, and the gate dielectric layer is exposed through the first opening. In one embodiment, the step of forming the first opening includes performing a first etching process on the dielectric cap layer using a first etching gas including CH4 / CHF3. In one embodiment, the step of forming the first opening includes performing a second etching process on the dielectric cap layer using a second etching gas including CH4 / CH2F2 after performing the first etching process.

[0014] In one embodiment, the preparation method further comprises, after forming the first opening, depositing a gap layer on the dielectric cap layer; and partially removing the gap layer to expose the first source / drain region, thereby forming a bit line contact point gapper covering a side wall of the first opening. In one embodiment, after forming the bit line contact point gapper, a remaining portion of the first opening is filled with the bit line contact point. In one embodiment, the preparation method further comprises forming a bit line on the bit line contact point, wherein the bit line contact point tapers from the bit line to the first source / drain region. In one embodiment, the preparation method further comprises forming a bit line gapper to cover a side wall of the bit line. In one embodiment, the preparation method further comprises forming a dielectric layer on the dielectric cap layer, wherein the bit line and the bit line gapper are covered by the dielectric layer. In addition, the preparation method comprises forming the second opening through the dielectric layer and the dielectric cap layer to expose the second source / drain region.

[0015] The present invention provides an embodiment of a memory element and a method for preparing the same. In some embodiments, the memory element includes a bit line contact having a tapered profile. Therefore, coverage or alignment failure problems can be reduced, and leakage current between source / drain regions can be avoided. As a result, overall element performance can be improved, and the yield of the memory element can be improved.

[0016] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0018] Figure 1 is a top view schematically illustrating a memory element according to some embodiments of the present disclosure.

[0019] Figure 2 is a cross-sectional schematic diagram illustrating the memory elements of some embodiments of the present disclosure along the Figure 1 The cross section is taken along the section line A-A'.

[0020] Figure 3 is a flow chart illustrating a method for preparing a memory element according to some embodiments of the present disclosure.

[0021] Figure 4 is a top view schematically illustrating an intermediate stage of forming a plurality of active regions in a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0022] Figure 5 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Figure 4 The section line AA' shows the middle stage of the memory element.

[0023] Figure 6 is a top view schematically illustrating an intermediate stage of forming a plurality of trenches across the active regions during formation of a memory device according to some embodiments of the present disclosure.

[0024] Figure 7 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Figure 6 The section line AA' shows the middle stage of the memory element.

[0025] Figure 8 is a top view schematically illustrating an intermediate stage of forming a plurality of word lines in the trenches during formation of a memory device according to some embodiments of the present disclosure.

[0026] Fig. 9 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Figure 8 The section line AA' shows the middle stage of the memory element.

[0027] Fig.10 is a top view schematically illustrating an intermediate stage of forming a dielectric capping layer on the word lines and forming a plurality of first openings through the dielectric capping layer during formation of a memory device according to some embodiments of the present disclosure.

[0028] Fig.11 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Fig.10 The section line AA' shows the middle stage of the memory element.

[0029] Fig.12 is a top view schematically illustrating an intermediate stage of forming a gap sub-layer on a dielectric cap layer during formation of a memory element according to some embodiments of the present disclosure.

[0030] Fig.13 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Fig.12 The section line AA' shows the middle stage of the memory element.

[0031] Fig.14 is a top view schematically illustrating an intermediate stage of partially removing a spacer layer to form a plurality of bit line contact spacers in the first openings during formation of a memory device according to some embodiments of the present disclosure.

[0032] Fig.15 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Fig.14 The section line AA' shows the middle stage of the memory element.

[0033] Fig.16 1 is a top view schematic diagram illustrating intermediate stages of forming a plurality of bit line contacts in the first openings, forming a plurality of bit lines on the bit line contacts, and forming a plurality of bit line spacers on sidewalls of the bit lines during formation of a memory element in some embodiments of the present disclosure.

[0034] Fig.17 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Fig.16 The section line AA' shows the middle stage of the memory element.

[0035] Fig.18 is a top view schematically illustrating an intermediate stage of forming a dielectric layer on the bit lines and forming a plurality of second openings through the dielectric layer and the dielectric cap layer during formation of a memory device according to some embodiments of the present disclosure.

[0036] Fig.19 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Fig.18 The section line AA' shows the middle stage of the memory element.

[0037] Fig. 20 is a top view schematically illustrating an intermediate stage of forming a plurality of capacitor contacts in the second openings during formation of a memory element according to some embodiments of the present disclosure.

[0038] Fig.21 is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure formed along Fig. 20 The section line AA' shows the middle stage of the memory element.

[0039] The reference numerals are described as follows:

[0040] 10: Preparation method

[0041] 100: Memory components

[0042] 101: Semiconductor substrate

[0043] 103: Isolation Structure

[0044] 105: Active Zone

[0045] 107: Doping area

[0046] 110: Groove

[0047] 113a: Source / drain region

[0048] 113b: Source / drain region

[0049] 115: Gate dielectric layer

[0050] 117: Gate electrode

[0051] 119: Character line

[0052] 121: Dielectric cover layer

[0053] 122: Opening

[0054] 125: Gap sublayer

[0055] 127: Bit line contact gap

[0056] 129: Bit line contact

[0057] 131: Lower bit line layer

[0058] 133: Upper bit line layer

[0059] 135: Bit line

[0060] 137: Bit line spacer

[0061] 141: Dielectric layer

[0062] 144: Opening

[0063] 147: Capacitor contact point

[0064] 151: Dielectric layer

[0065] 154: Opening

[0066] 161: Lower electrode

[0067] 163: Capacitor dielectric layer

[0068] 165: Upper electrode

[0069] 167: Capacitor

[0070] S1: Sidewall

[0071] S2: Sidewall

[0072] S3: Sidewall

[0073] S11: Steps

[0074] S13: Steps

[0075] S15: Steps

[0076] S17: Steps

[0077] S19: Steps

[0078] S21: Steps

[0079] S23: Steps

[0080] S25: Steps

[0081] S27: Steps

[0082] S29: Steps

[0083] T1: Top surface

[0084] T2: Upper surface

[0085] W1: bottom width

[0086] W2: Upper width

[0087] W3: bottom width

[0088] W4: Upper width

[0089] θ: Angle DETAILED DESCRIPTION

[0090] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0091] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0092] Figure 1 FIG. 1 is a top view schematically illustrating a memory device 100 according to some embodiments of the present disclosure. Figure 2 is a cross-sectional schematic diagram illustrating a memory element 100 according to some embodiments of the present disclosure along Figure 1 The cross section is taken along the section line A-A'.

[0093] like Figure 1 and Figure 2 As shown, the memory element 100 includes a semiconductor substrate 101, an isolation structure 103 disposed in the semiconductor substrate 101 defining a plurality of active regions 105, a plurality of word lines 119 (i.e., gate structures) extending across the active regions 105, and a plurality of source / drain regions 113a and 113b separated by the word lines 119 in the active regions 105. In some embodiments, each active region 105 includes two source / drain regions 113b and a source / drain region 113a disposed between the two source / drain regions 113b. The source / drain region 113a is also referred to as a first source / drain region, and the source / drain region 113b is also referred to as a second source / drain region. In addition, each word line 119 includes a gate dielectric layer 115 and a gate electrode 117 surrounded by the gate dielectric layer 115.

[0094] The memory device 100 further includes a dielectric capping layer 121 covering the word line 119, a plurality of bit line contacts 129 penetrating the dielectric capping layer 121, and each bit line contact 129 is separated from the dielectric capping layer 121 by a bit line contact spacer 127. In some embodiments, the bit line contact spacer 127 is in direct contact with the gate dielectric layer 115 of the word line 119. In some embodiments, the bit line contact 129 and the bit line contact spacer 127 are in direct contact with the source / drain region 113a in the active region 105.

[0095] In some embodiments, each bit line contact 129 has a tapered profile along a direction from the upper surface T1 of the dielectric cap layer 121 toward the source / drain region 113a. In some embodiments, an angle θ between the upper surface T2 of the bit line contact 129 and the sidewall S1 is in a range of about 73 degrees to about 81 degrees.

[0096] The memory device 100 further includes a dielectric layer 141 disposed on the dielectric cap layer 121 and a plurality of bit lines 135 disposed in the dielectric layer 141. In some embodiments, each bit line 135 includes a lower bit line layer 131 and an upper bit line layer 133 disposed on the lower bit line layer 131. In some embodiments, the bit line 135 is disposed on the bit line contact 129, and the bit line 135 is electrically connected to the source / drain region 113a via the bit line contact 129.

[0097] In some embodiments, the bit line contact 129 has a lower width W1 and an upper width W2. In some embodiments, the upper width W2 is greater than the lower width W1, so that the bit line contact 129 has a tapered profile along a direction from the upper surface T1 of the dielectric cap layer 121 toward the source / drain region 113a. In some embodiments, the ratio of the upper width W2 to the lower width W1 of the bit line contact 129 is in a range of about 1.45 to about 1.85.

[0098] In some embodiments, the memory device 100 includes a bit line spacer 137 covering a sidewall S2 of the bit line 135. In some embodiments, the bit line spacer 137 is in direct contact with the bit line contact spacer 127. In addition, the memory device 100 includes a plurality of capacitor contacts 147 that pass through the dielectric layer 141 and the dielectric cap layer 121 to be electrically connected to the source / drain region 113b. The memory device 100 also includes a dielectric layer 151 disposed on the dielectric layer 141, and a plurality of capacitors 167 disposed in the dielectric layer 151 to be electrically connected to the source / drain region 113b via the capacitor contacts 147. In some embodiments, each capacitor 167 includes a lower electrode 161, an upper electrode 165 disposed on the lower electrode 161 and surrounded by the lower electrode 161, and a capacitor dielectric layer 163 disposed between the lower electrode 161 and the upper electrode 165 and in direct contact with the lower electrode 161 and the upper electrode 165.

[0099] In some embodiments, the memory device 100 includes a plurality of bit line contacts 129 having a tapered profile, and the bit line contacts 129 are gradually tapered along a direction from the upper surface T1 of the dielectric cap layer 121 toward the source / drain region 113a. Therefore, overlap or alignment failure problems can be reduced, and leakage current between the source / drain regions 113a and 113b can be avoided. As a result, the overall device performance can be improved, and the yield of the memory device 100 can be increased.

[0100] Figure 3 1 is a flow chart illustrating a method 10 for manufacturing a memory element 100 according to some embodiments of the present disclosure, and the method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27 and S29. Figure 3 Steps S11 to S29 are described in detail.

[0101] According to some embodiments, Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig. 20 A top view showing an intermediate stage in the formation of memory element 100, and Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 and Fig.21 1 shows a cross-sectional view of an intermediate stage in the formation of the memory element 100. It should be understood that Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 and Fig.21 Along Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig. 20 Cross-sectional view along the section line A-A'.

[0102] like Figure 4 and Figure 5 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP.

[0103] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0104] Please still refer to Figure 4 and Figure 5 According to some embodiments, an isolation structure 103 is formed in the semiconductor substrate 101 to define the active region 105, and the isolation structure 103 is a shallow trench isolation (STI) structure. In addition, the isolation structure 103 may include silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials, and the formation of the isolation structure 103 may include forming a patterned mask (not shown) on the semiconductor substrate 101; etching the semiconductor substrate 101 by using the patterned mask as a mask to form a plurality of openings (not shown); depositing a dielectric material in the openings and on the semiconductor substrate 101; and planarizing the dielectric material until the semiconductor substrate 101 is exposed.

[0105] In addition, a plurality of doped regions 107 are formed in the active region 105 defined by the isolation structure 103. Each step is shown as follows: Figure 3 Step S11 in the preparation method 10 shown in FIG. 10. In some embodiments, the manufacturing technology of the doped region 107 includes one or more ion implantation processes, and according to the conductivity type of the memory element 100, a P-type dopant such as boron (B), gallium (Ga) or indium (In) or an N-type dopant such as phosphorus (P) or arsenic (As) can be implanted into the active region 105 to form the doped region 107. In addition, the doped region 107 will become the source / drain region of the memory element 100 in subsequent processes.

[0106] According to some embodiments, Figure 6 and Figure 7 As shown, after forming the doped region 107, the semiconductor substrate 101 is etched to form a plurality of trenches 110. In some embodiments, the trenches 110 are parallel to each other. In some embodiments, the trenches 110 extend across the doped region 107 in the active region 105 (see FIG. Figure 4 and Figure 5 ) to form source / drain regions 113a and 113b.

[0107] In some embodiments, the source / drain region 113b is located at opposite ends of the active region 105, and the source / drain region 113a is located at the middle of the active region 105. The formation of the trench 110 may include forming a patterned mask (not shown) on the semiconductor substrate 101; and etching the semiconductor substrate 101 by using the patterned mask as a mask. After the trench 110 is formed, the patterned mask may be removed.

[0108] Next, according to some embodiments, Figure 8 and Fig. 9 As shown, a plurality of word lines 119 (ie, gate structures) are formed in the trenches 110. Each step is shown as follows: Figure 3 The step S13 of the manufacturing method 10 is shown. In some embodiments, the word line 119 includes a plurality of gate dielectric layers 115 and a plurality of gate electrodes 117 .

[0109] In some embodiments, the gate dielectric layer 115 includes silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant (high-k) dielectric material, or a combination thereof, and the gate electrode 117 includes a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or may be a multilayer structure including any combination of the above materials. In some embodiments, a plurality of barrier layers (not shown) are formed between the gate dielectric layer 115 and the gate electrode 117.

[0110] The formation of the gate dielectric layer 115 may include conformally depositing a gate dielectric material (not shown) on the inner surface of the trench 110 and the upper surface of the semiconductor substrate 101; and planarizing the gate dielectric material to expose the upper surface of the semiconductor substrate 101. After forming the gate dielectric layer 115, the formation of the gate electrode 117 may include depositing a gate electrode material (not shown) on the gate dielectric layer 115; and recessing the gate electrode material to form the gate electrode 117.

[0111] The deposition process of the gate dielectric material may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process or other suitable processes. The planarization process of the gate dielectric material may include a chemical mechanical polishing (CMP) process. The deposition process of the gate electrode material may include one or more deposition processes, such as a CVD process, a PVD process, an ALD process, a plasma enhanced chemical vapor deposition (PECVD) process, a metal organic chemical vapor deposition (MOCVD) process, a plating process, a sputtering process or other suitable deposition processes. The gate electrode material may be recessed by an etch-back process so that the upper surface of the gate electrode 117 is lower than the upper surface of the semiconductor substrate 101. The etch-back process may include a wet etching process, a dry etching process or a combination thereof.

[0112] Then, if Fig.10 and Fig.11 According to some embodiments, a dielectric capping layer 121 is formed to cover the word line 119 and the source / drain regions 113a and 113b, and the dielectric capping layer 121 is partially removed to form a plurality of openings 122 (also referred to as first openings) exposing the source / drain regions 113a. Figure 3 Step S15 and step S17 of the manufacturing method 10 are shown. In some embodiments, the remaining portion of the trench 110 on the gate electrode 117 of the word line 119 is filled with the dielectric cap layer 121. In some embodiments, the portion of the dielectric cap layer 121 filled in the trench 110 is surrounded by the gate dielectric layer 115 of the word line 119.

[0113] In some embodiments, the dielectric cap layer 121 includes silicon nitride. However, any other suitable dielectric material may be used, such as silicon oxide, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the manufacturing technology of the dielectric cap layer 121 includes a CVD process, a PVD process, a spin coating process, other suitable processes, or a combination thereof.

[0114] In some embodiments, the dielectric cap layer 121 is etched to form a plurality of openings 122 having a tapered profile. In some embodiments, after performing a first etching process, the technique for forming the openings 122 includes performing a first etching process on the dielectric cap layer 121 using a first etching gas comprising CH4 / CHF3; and performing a second etching process on the dielectric cap layer 121 using a second etching gas comprising CH4 / CH2F2. In some embodiments, each of the openings 122 has a tapered profile. For example, each of the openings 122 has an upper width W4 and a lower width W3, and the upper width W4 is greater than the lower width W3, so that the openings 122 have a tapered profile along a direction from the upper surface T1 of the dielectric cap layer 121 toward the source / drain region 113a.

[0115] In some embodiments, the opening 122 that passes through the dielectric capping layer 121 and exposes the source / drain region 113a is a bit line contact opening. In some embodiments, the gate dielectric layer 115 of the word line 119 is exposed through the opening 122, and after the opening 122 is formed, the gate electrode 117 of the word line 119 is still covered by the dielectric capping layer 121.

[0116] Then, according to some embodiments, Fig.12 and Fig.13As shown, a gap sublayer 125 is conformally deposited on the dielectric cap layer 121. In some embodiments, the gap sublayer 125 includes nitride. However, any other suitable dielectric material may be used, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the manufacturing technology of the gap sublayer 125 includes a CVD process, a PVD process, a spin coating process, other suitable processes, or a combination thereof.

[0117] In some embodiments, the upper surface T1 of the dielectric cap layer 121 and the (tapered) sidewall S3 of the opening 122 are covered by the spacer layer 125. In some embodiments, the source / drain region 113a exposed by the opening 122 is covered by the spacer layer 125. In some embodiments, the spacer layer 125 is in direct contact with the source / drain region 113a, the gate dielectric layer 115 of the word line 119, and the dielectric cap layer 121.

[0118] Next, according to some embodiments, Fig.14 and Fig.15 As shown, the spacer layer 125 is partially removed by an etching process to form a plurality of bit line contact spacers 127 in the opening 122. Each step is shown as follows: Figure 3 The step S19 of the manufacturing method 10 is shown. In some embodiments, the bit line contact spacer 127 covers the (tapered) sidewall S3 of the opening 122 .

[0119] In some embodiments, the spacer layer 125 is etched by an anisotropic etching process that vertically removes the same amount of spacer material at all locations to leave the bit line contact spacers 127 on the sidewalls S3 of the opening 122. In some embodiments, the etching process is a dry etching process. After the bit line contact spacers 127 are formed, the source / drain regions 113a are partially exposed.

[0120] Then, according to some embodiments, Fig.16 and Fig.17 As shown, the bit line contact 129 and the bit line 135 are formed above the source / drain region 113a, and the bit line spacer 137 is formed on the sidewall S2 of the bit line 135. The various steps are shown as follows: Figure 3 In the step S21 and step S23 of the preparation method 10 shown in FIG. Fig.14 and Fig.15 ) is filled with the bit line contact 129, and the bit line 135 is formed on the bit line contact 129. In some embodiments, the bit line 135 is electrically connected to the source / drain region 113a via the bit line contact 129.

[0121] As described above, each bit line 135 includes a lower bit line layer 131 and an upper bit line layer 133 disposed on the lower bit line layer 131. In some embodiments, the lower bit line layer 131 and the bit line contact 129 of the bit line 135 are formed of the same material during the same process step. In this case, Fig.17 The dashed line indicating the boundary between the bit line contact 129 and the lower bit line layer 131 is used to clarify the present disclosure. There is no obvious interface between the bit line contact 129 and the lower bit line layer 131.

[0122] For example, the following material (not shown) is formed on the dielectric cap layer 121 and fills the remaining portion of the opening 122 (see FIG. Fig.14 and Fig.15 ), and an upper material (not shown) is formed on the lower material. Then, a patterned mask (not shown) is formed on the upper material, and an etching process is performed on the upper material and the lower material by using the patterned mask as a mask. In some embodiments, the remaining portion of the lower material surrounded by the bit line contact spacers 127 becomes the bit line contact 129, and the remaining portion of the lower material on the dielectric cap layer 121 becomes the lower bit line layer 131. In addition, the remaining portion of the upper material becomes the upper bit line layer 133. In some embodiments, the lower bit line layer 131 and the upper bit line layer 133 have aligned sidewalls. After the bit line 135 is formed, the patterned mask can be removed.

[0123] In some embodiments, the bit line contact 129 and the lower bit line layer 131 include doped polysilicon, metal, metal silicide or metal compound, and the upper bit line layer 133 includes one or more metals or metal compounds. The deposition process for forming the lower material and the upper material may include CVD, PVD, ALD, PECVD, other suitable methods or combinations thereof. The etching process may include a dry etching process, a wet etching process or combinations thereof.

[0124] According to some embodiments, after forming the bit line 135, the bit line spacer 137 is formed on the sidewall S2 of the bit line 135. In some embodiments, the bit line spacer 137 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In some embodiments, the manufacturing technology of the bit line spacer 137 includes a deposition process and a subsequent etching process. The deposition process may include a CVD process, a PVD process, a spin coating process, other suitable processes or combinations thereof. The etching process may include a dry etching process, a wet etching process or combinations thereof.

[0125] Then, if Fig.18 and Fig.19According to some embodiments, a dielectric layer 141 is formed on the dielectric cap layer 121 and covers the bit line 135 and the bit line spacer 137, and the dielectric layer 141 and the dielectric cap layer 121 are partially removed to form an opening 144 (also referred to as a second opening) exposing the source / drain region 113b. Figure 3 Step S25 in the preparation method 10 shown.

[0126] In some embodiments, the dielectric layer 141 includes a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) less than about 4. Examples of low-k dielectric materials include silicon oxide, silicon nitride, silicon carbonitride (SiCN), silicon carbonitride (SiOCN), fluorinated silicon glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene (BCB) or polyimide, but are not limited thereto. In addition, the manufacturing technology of the dielectric layer 141 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process or other suitable processes.

[0127] The formation of the opening 144 may include forming a patterned mask (not shown) on the dielectric layer 141; and performing an etching process on the dielectric layer 141 and the dielectric cap layer 121 by using the patterned mask as a mask. The etching process may include a dry etching process, a wet etching process, or a combination thereof. After forming the opening 144, the patterned mask may be removed. In some embodiments, the opening 144 through the dielectric layer 141 and the dielectric cap layer 121 is a capacitor contact point opening.

[0128] Next, if Fig. 20 and Fig.21 As shown, according to some embodiments, capacitor contact 147 is formed in opening 144, dielectric layer 151 is formed on dielectric layer 141, and a plurality of openings 154 are formed through dielectric layer 151 to expose capacitor contact 147. The various steps are shown as follows: Figure 3 In some embodiments, the capacitor contact 147 electrically connects the source / drain region 113b to the subsequently formed capacitor 167 (see Figure 1 and Figure 2 ).

[0129] In some embodiments, the capacitor contact 147 includes a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), or a combination thereof. The manufacturing technology of the capacitor contact 147 may include a deposition process and a subsequent planarization process. The deposition process may include a CVD process, a PVD process, a sputtering process, a plating process, or other suitable processes. The planarization process may be a CMP process. Some materials and processes used to form the dielectric layer 151 are similar or identical to the materials and processes used to form the dielectric layer 141, and are not repeated here.

[0130] According to some embodiments, after forming the dielectric layer 151, an opening 154 is formed through the dielectric layer 151 to expose the capacitor contact 147. The formation of the opening 154 may include forming a patterned mask (not shown) on the dielectric layer 151; and etching the dielectric layer 151 using the patterned mask as a mask to expose the capacitor contact 147. The etching process may be a wet etching process, a dry etching process, or a combination thereof. After forming the opening 154, the patterned mask may be removed.

[0131] Then, according to some embodiments, Figure 1 and Figure 2 As shown, a plurality of capacitors 167 are formed in the openings 154 in the dielectric layer 151. The various steps are shown as follows: Figure 3 10. In some embodiments, the capacitor 167 is electrically connected to the source / drain region 113b via the capacitor contact 147. As described above, each capacitor 167 includes a lower electrode 161, an upper electrode 165 disposed on and surrounded by the lower electrode 161, and a capacitor dielectric layer 163 disposed between the lower electrode 161 and the upper electrode 165 and in direct contact with the lower electrode 161 and the upper electrode 165.

[0132] The formation of capacitor 167 may include sequentially depositing a conductive material, a dielectric material, and another conductive material in opening 154 (see Fig. 20 and Fig.21 ) and extending on the dielectric layer 151; and performing a planarization process (e.g., a CMP process) to remove excess portions of the two conductive materials and the dielectric material. In some embodiments, the lower electrode 161 includes titanium nitride (TiN), the capacitor dielectric layer 163 includes a dielectric material, such as silicon dioxide (SiO2), hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2) or a combination thereof, and the upper electrode 165 includes titanium nitride (TiN), low stress silicon germanium (SiGe) or a combination thereof.

[0133] After forming capacitor 167, memory element 100 is obtained. In some embodiments, memory element 100 is part of a dynamic random access memory (DRAM).

[0134] The present disclosure provides an embodiment of a memory device having a tapered bit line contact and a method for making the same. In some embodiments, the memory device 100 includes a plurality of bit line contacts 129 having a tapered profile. In some embodiments, the bit line contacts 129 taper along a direction from the bit line 135 to the semiconductor substrate 101. Therefore, overlap or alignment failure problems can be reduced, and leakage current between the source / drain regions 113a and 113b can be avoided. As a result, the overall device performance can be improved, and the yield of the memory device 100 can be increased.

[0135] One embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having an active region; and a word line extending across the active region. The memory element also includes a first source / drain region and a second source / drain region, which are arranged in the active region and on opposite sides of the word line. The memory element also includes a bit line contact point, which is arranged on the first source / drain region and electrically connected to the first source / drain region. The bit line contact point has a tapered profile. In addition, the memory element includes a capacitor contact point, which is arranged on the second source / drain region and electrically connected to the second source / drain region.

[0136] Another embodiment of the present disclosure provides a memory element. The memory element includes a semiconductor substrate having an active region; and a word line extending across the active region. The memory element also includes a first source / drain region and a second source / drain region, which are arranged in the active region and on opposite sides of the word line. The memory element also includes a dielectric cap layer covering the word line; and a bit line contact point passing through the dielectric cap layer to contact the first source / drain region. An upper width of the bit line contact point is greater than a lower width of the bit line contact point. In addition, the memory element includes a capacitor contact point passing through the dielectric cap layer to contact the second source / drain region.

[0137] Another embodiment of the present disclosure provides a method for preparing a memory element. The preparation method includes forming a doped region in a semiconductor substrate; and forming a word line to cross the doped region, so that a first source / drain region and a second source / drain region are formed in the doped region and on opposite sides of the word line. The preparation method also includes forming a dielectric cap layer to cover the word line, the first source / drain region and the second source / drain region; and forming a first opening through the dielectric cap layer to expose the first source / drain region. The first opening has a tapered profile along a direction from an upper surface of the dielectric cap layer to the first source / drain region. The preparation method also includes forming a bit line contact point in the first opening; and forming a second opening through the dielectric cap layer to expose the second source / drain region. In addition, the preparation method includes forming a capacitor contact point in the second opening.

[0138] Embodiments of the present disclosure have some advantageous features. In some embodiments, the memory element includes a bit line contact having a tapered profile. Therefore, coverage or alignment failure problems can be reduced, and leakage current between source / drain regions can be avoided. As a result, overall element performance can be improved, and the yield of the memory element can be increased.

[0139] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0140] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: A semiconductor substrate having an active region; a character line extending across the active area; A first source / drain region and a second source / drain region are disposed in the active region and on opposite sides of the word line; a bit line contact disposed on the first source / drain region and electrically connected to the first source / drain region, wherein the bit line contact has a tapered profile; as well as A capacitor contact point is disposed on the second source / drain region and electrically connected to the second source / drain region.

2. The memory element of claim 1 , further comprising: a dielectric capping layer disposed on the semiconductor substrate, wherein the capacitor contact and the bit line contact pass through the dielectric capping layer; as well as A bit line contact point spacer is disposed between the dielectric cap layer and the bit line contact point.

3. The memory device of claim 2, wherein the bit line contact spacer and the dielectric cap layer comprise different materials.

4. The memory element of claim 1 , further comprising: A capacitor is disposed on the capacitor contact point and electrically connected to the capacitor contact point.

5. The memory element of claim 1, further comprising: A bit line is disposed at the bit line contact point and electrically connected to the bit line contact point. 6 . The memory device of claim 5 , wherein the bit line contact gradually becomes smaller from the bit line to the semiconductor substrate.

7. The memory device of claim 5, wherein an upper width of the bit line contact is substantially the same as a lower width of the bit line. 8 . The memory device as claimed in claim 7 , wherein the upper width of the bit line contact is greater than a lower width of the bit line contact.

9. A memory element comprising: A semiconductor substrate having an active region; a character line extending across the active area; A first source / drain region and a second source / drain region are disposed in the active region and on opposite sides of the word line; a dielectric cap layer covering the word line; a bit line contact, passing through the dielectric cap layer to contact the first source / drain region, wherein an upper width of the bit line contact is greater than a lower width of the bit line contact; as well as A capacitor contact passes through the dielectric cap layer to contact the second source / drain region. 10 . The memory device of claim 9 , wherein the bit line contact has a tapered profile along a direction from an upper surface of the dielectric cap layer to the first source / drain region.

11. The memory device of claim 9, wherein a ratio of the upper width to the lower width of the bit line contact is in a range of about 1.45 to about 1.

85.

12. The memory device of claim 9, wherein an angle between a top surface and a sidewall of the bit line contact is in a range of about 73 degrees to about 81 degrees.

13. The memory element of claim 9, further comprising: A bit line contact spacer separates the bit line contact from the dielectric cap layer.

14. The memory element of claim 9, further comprising: a capacitor disposed at the capacitor contact point; as well as A bit line is arranged on the bit line contact point.

15. The memory element of claim 14, further comprising: A bit line spacer is disposed on a side wall of the bit line, wherein the bit line spacer is in direct contact with the bit line contact point spacer.

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