Semiconductor device

Abstract

A semiconductor device may include first and second active patterns, first and second gate structures, a source / drain layer, a bit line structure, a contact plug structure, and a capacitor. The first and second active patterns are on the cell region and the peripheral circuit region, respectively, of the substrate. The first gate structure extends through an upper portion of the first active pattern. A second gate structure is on an upper surface and an upper sidewall of the second active pattern. A source / drain layer is on a portion of the second active pattern adjacent the second gate structure. The bit line structure is on a central portion of the first active pattern and overlaps the second gate structure in a horizontal direction. Contact plug structures are on opposite ends of the first active pattern. A capacitor is on the contact plug structure.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0086188 filed on July 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to semiconductor devices. More particularly, example embodiments of the present disclosure relate to dynamic random access memory (DRAM) devices. Background Art

[0003] As the integration density in DRAM devices has increased, the size of components of the DRAM devices has decreased, and the area of ​​transistors in the peripheral circuit region may need to be reduced. In a planar transistor, a gate electrode has low controllability of a channel, and the planar transistor may have a problem of gate induced drain leakage (GIDL) or gate induced junction leakage (GIJL). Summary of the invention

[0004] Example embodiments provide a semiconductor device having improved characteristics.

[0005] According to an example embodiment of the inventive concept, a semiconductor device is provided. The semiconductor device may include: a first active pattern and a second active pattern, respectively on a cell region and a peripheral circuit region of a substrate; a first gate structure, extending through an upper portion of the first active pattern; a second gate structure, on an upper surface and an upper sidewall of the second active pattern; a source / drain layer, on a portion of the second active pattern adjacent to the second gate structure; a bit line structure, on a central portion of the first active pattern, the bit line structure overlapping the second gate structure in a horizontal direction substantially parallel to an upper surface of the substrate; a contact plug structure, on an opposite end of the first active pattern; and a capacitor, on the contact plug structure.

[0006] According to an example embodiment of the inventive concept, a semiconductor device is provided. The semiconductor device may include: a first active pattern on a substrate; a first gate structure extending through an upper portion of the first active pattern in a first direction substantially parallel to an upper surface of the substrate; a bit line structure on a central portion of the first active pattern, the bit line structure extending in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction, wherein the bit line structure includes a first conductive pattern, a blocking pattern, a second conductive pattern, and a covering pattern stacked in a vertical direction substantially perpendicular to the upper surface of the substrate; a contact plug structure on an end opposite to the first active pattern; and a capacitor on the contact plug structure. The end of the blocking pattern in the second direction may have an "L" shape in a cross-sectional view.

[0007] According to an example embodiment of the inventive concept, a semiconductor device is provided. The semiconductor device may include: a first active pattern and a second active pattern, respectively, on a cell region and a peripheral circuit region of a substrate; an isolation structure, on the substrate and on the sidewalls of the first active pattern and the second active pattern, the isolation structure including a first isolation pattern, a second isolation pattern, and a third isolation pattern; a first gate structure, on the cell region of the substrate, extending through the first active pattern and an upper portion of the isolation structure in a first direction substantially parallel to an upper surface of the substrate; a second gate structure, on an upper surface and an upper sidewall of the second active pattern, wherein the second gate structure is on the isolation structure and on the peripheral circuit region of the substrate; a source / drain a layer, on a portion of the second active pattern adjacent to the second gate structure; a bit line structure, on a central portion of the first active pattern and on the isolation structure, the bit line structure extending in a second direction substantially parallel to an upper surface of the substrate and intersecting the first direction, wherein the bit line structure is on a cell region and on a portion of a peripheral circuit region adjacent to the cell region, and wherein the bit line structure includes a first conductive pattern, a blocking pattern, a second conductive pattern, and a covering pattern stacked in a vertical direction substantially perpendicular to the upper surface of the substrate; a contact plug structure, on an end portion opposite to the first active pattern; and a capacitor, on the contact plug structure.

[0008] A semiconductor device according to example embodiments may include a transistor on a peripheral circuit region of a substrate, and a gate structure of the transistor may contact an upper sidewall of an active pattern protruding from the substrate and an upper surface of the active pattern. Therefore, controllability of the gate structure on a channel in the active pattern may be improved, and GIDL or GIJL phenomenon may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan view showing a semiconductor device according to example embodiments, Figure 2 It is along Figure 1 A cross-sectional view taken along line A-A', Figure 3 It is along Figure 1 A cross-sectional view taken along line BB' of Figure 4 It is along Figure 1 A cross-sectional view taken along line CC'.

[0010] Figures 5 to 47 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0011] Fig.48 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0012] Figure 49 to Figure 53 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0013] Fig.54 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0014] Figures 55 to 60 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0015] Figure 61 to Figure 63 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0016] With reference to the accompanying drawings, the above and other aspects and features of the semiconductor device and the method for forming the semiconductor device according to the example embodiments will become easily understood from the following detailed description. It will be understood that although the terms "first", "second" and / or "third" may be used herein to describe various materials, layers (films), regions, electrodes, pads (or pads), patterns, structures and processes, these materials, layers (films), regions, electrodes, pads, patterns, structures and processes should not be limited by these terms. These terms are only used to distinguish one material, layer (film), region, electrode, pad, pattern, structure and process from another material, layer (film), region, electrode, pad, pattern, structure and process. Therefore, without departing from the teachings of the inventive concept, the first material, first layer (film), first region, first electrode, first pad, first pattern, first structure and first process discussed below may also be referred to as the second material or third material, the second layer (film) or third layer (film), the second region or third region, the second electrode or third electrode, the second pad or third pad, the second pattern or third pattern, the second structure or third structure and the second process or third process.

[0017] Hereinafter, two directions among the horizontal directions substantially parallel to the upper surface of the substrate may be respectively referred to as a first direction D1 and a second direction D2, and a direction among the horizontal directions having an acute angle with respect to the first direction D1 and the second direction D2 may be referred to as a third direction D3. A direction substantially perpendicular to the upper surface of the substrate may be referred to as a vertical direction.

[0018] As used herein, the terms “includes,” “comprising,” “having,” and any other variations thereof specify the presence of stated features, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0019] Figure 1 is a plan view showing a semiconductor device according to example embodiments, Figure 2 It is along Figure 1 A cross-sectional view taken along line A-A', Figure 3 It is along Figure 1A cross-sectional view taken along line BB' of Figure 4 It is along Figure 1 A cross-sectional view taken along line CC'.

[0020] Reference Figures 1 to 4 The semiconductor device may include first and second active patterns 101 and 105 , first and second gate structures 150 and 320 , a source / drain layer 220 , a bit line structure 395 , a contact plug structure, and a capacitor 670 .

[0021] The semiconductor device may also include a polysilicon layer 120, an isolation structure 130, a spacer structure 465, a first spacer 210 and a sixth spacer 490, a fence pattern 480, a buffer pattern 165, a first etch stop pattern 175, a first insulating interlayer 230, a protection pattern 330, a fifth covering pattern 377, first to third contact plugs 552, 554 and 556, wiring 551, a third etch stop layer 630 and a first insulating pattern structure to a third insulating pattern structure.

[0022] The substrate 100 may include silicon, germanium, silicon-germanium, or a III-V compound semiconductor such as GaP, GaAs, or GaSb. In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0023] The substrate 100 may include a first region I and a second region II surrounding the first region I, and Figures 1 to 4 Parts of the first region I and the second region II of the substrate 100 are shown. The first region I of the substrate 100 may be a cell region in which a memory cell is formed, and the second region II of the substrate 100 may be a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed.

[0024] The first and second active patterns 101 and 105 may be formed by removing upper portions of the first and second regions I and II of the substrate 100 , respectively, and thus may include substantially the same material as that of the substrate 100 .

[0025] The first active pattern 101 may extend in the third direction D3 in the first region I of the substrate 100 , and a plurality of the first active patterns 101 may be spaced apart from each other in the first direction D1 and the second direction D2 .

[0026] The second active pattern 105 may protrude from an upper portion of the second region II of the substrate 100 and may also be referred to as an active fin.

[0027] In one example embodiment, the second active pattern 105 may extend in the first direction D1 in the second region II of the substrate 100, and a plurality of second active patterns 105 may be spaced apart from each other in the second direction D2. However, the inventive concept is not limited thereto. In another example embodiment, the second active pattern 105 may extend in the second direction D2 in the second region II of the substrate 100, and a plurality of second active patterns 105 may be spaced apart from each other in the first direction D1.

[0028] In example embodiments, the first active pattern 101 may have a lower surface lower than the second active pattern 105. For example, in the case where the lower surface of the substrate 100 provides a base reference plane, the first active pattern 101 may have a lower surface lower than the second active pattern 105.

[0029] The polysilicon layer 120 may be formed on the sidewalls of the first active pattern 101 , the lower sidewalls of the second active pattern 105 , and the upper surface of the substrate 100 .

[0030] The isolation structure 130 may be formed on the polysilicon layer 120. In example embodiments, the isolation structure 130 may include a first isolation pattern 132, a second isolation pattern 134, and a third isolation pattern 136. The first isolation pattern 132 may be formed between the first active patterns 101 on the first region I of the substrate 100. The first to third isolation patterns 132, 134, and 136 may be sequentially stacked between the second active patterns 105 on the second region II of the substrate 100.

[0031] The upper surface of the first isolation pattern 132 surrounding the first active pattern 101 may be substantially coplanar with the uppermost surface of the first active pattern 101. In example embodiments, the upper surface of a portion of the isolation structure 130 adjacent to the second active pattern 105 in the second direction D2 may be lower than the upper surface of the second active pattern 105, and thus the upper sidewall of the second active pattern 105 may not be covered by the isolation structure 130 (see, for example, Figure 2 ).

[0032] Each of the first isolation pattern 132 and the third isolation pattern 136 may include an oxide (eg, silicon oxide), and the second isolation pattern 134 may include an insulating nitride (eg, silicon nitride).

[0033] The first gate structure 150 may extend in the first direction D1 through the first active pattern 101, the polysilicon layer 120, and the upper portion of the first isolation pattern 132 in the first region I of the substrate 100. In example embodiments, a plurality of first gate structures 150 may be spaced apart from each other in the second direction D2 in the first region I of the substrate 100. For example, the first gate structure 150 may extend through the upper portion of the isolation structure 130 (e.g., may extend through the upper portion of the first isolation pattern 132).

[0034] The first gate structure 150 may include a first conductive pattern 144, a second conductive pattern 146 and a first gate mask 148 sequentially stacked in a vertical direction, and a first gate insulating pattern 142 covering the sidewalls of the first conductive pattern 144, the second conductive pattern 146 and the first gate mask 148, and the first conductive pattern 144 and the second conductive pattern 146 may jointly form a first gate electrode.

[0035] The first gate insulating pattern 142 may include an oxide (e.g., silicon oxide), the first conductive pattern 144 may include a metal, a metal nitride, a metal silicide, etc., the second conductive pattern 146 may include, for example, polysilicon doped with n-type impurities, and the first gate mask 148 may include an insulating nitride (e.g., silicon nitride).

[0036] The second gate structure 320 may extend in the second direction D2 on the second active pattern 105, the polysilicon layer 120, and the isolation structure 130 on the second region II of the substrate 100, and a plurality of the second gate structures 320 may be spaced apart from each other in the first direction D1. However, the inventive concept is not limited thereto, and if the second active pattern 105 extends in the second direction D2, the second gate structure 320 may extend in the first direction D1, and a plurality of the second gate structures 320 may be spaced apart from each other in the second direction D2.

[0037] The second gate structure 320 may include an interface pattern 290 on the upper surface and upper sidewall of the second active pattern 105, and a high-k dielectric pattern 300 and a fourth conductive pattern 310 (also referred to as a second gate electrode 310) sequentially stacked on the interface pattern 290. The interface pattern 290 and the high-k dielectric pattern 300 may together form a second gate insulating pattern. In some embodiments, the interface pattern 290 may also be formed on the upper surface of the isolation structure 130 and the upper surface and upper sidewall of the second active pattern 105.

[0038] The interface pattern 290 may include oxide (eg, silicon oxide), the high-k dielectric pattern 300 may include metal oxide having a high-k dielectric constant (eg, hafnium oxide, zirconium oxide, etc.), and the fourth conductive pattern 310 may include metal, metal nitride, metal silicide, etc.

[0039] The source / drain layer 220 may be formed on a portion of the second active pattern 105 adjacent to the second gate structure 320 in the first direction D1. An upper surface of the portion of the second active pattern 105 may be lower than an upper surface of a portion of the second active pattern 105 below the second gate structure 320. For example, in a case where the lower surface of the substrate 100 provides a base reference plane, an upper surface of a first portion of the second active pattern 105 below the source / drain layer 220 may be lower than an upper surface of a second portion of the second active pattern 105 below the second gate structure 320.

[0040] In example embodiments, a cross-section of the source / drain layer 220 in the second direction D2 may have a shape of, for example, a rhombus or a pentagon. The source / drain layer 220 may include single crystalline silicon doped with p-type impurities or n-type impurities.

[0041] In example embodiments, in a portion of the isolation structure 130 adjacent to the source / drain layer 220 in the second direction D2, the second isolation pattern 134 may protrude from the first isolation pattern 132 and the third isolation pattern 136 in a vertical direction (eg, see Figure 3 In an example embodiment, an uppermost surface of a portion of the isolation structure 130 adjacent to the source / drain layer 220 in the second direction D2 (eg, an uppermost surface of the second isolation pattern 134 ) may be substantially coplanar with an upper surface of a portion of the second active pattern 105 under the second gate structure 320 .

[0042] The second gate structure 320 and the source / drain layer 220 may form a transistor together, and the second gate structure 320 may be on the upper portion of the second active pattern 105 protruding from the second region II of the substrate 100 (e.g., may cover the upper portion of the second active pattern 105 protruding from the second region II of the substrate 100). Therefore, the transistor may be a fin field effect transistor (FinFET).

[0043] The second insulating pattern structure may include a buffer pattern 165 and a first etch stop pattern 175 stacked in a vertical direction. The second insulating pattern structure may be formed on the first isolation pattern 132, the first gate structure 150, and the first active pattern 101 on the first region I of the substrate 100, and a portion of the second region II adjacent to the first region I of the substrate 100. In example embodiments, a plurality of buffer patterns 165 may be spaced apart from each other in the first direction D1 and the second direction D2, and a plurality of first etch stop patterns 175 may be spaced apart from each other in the first direction D1 and the second direction D2. The buffer pattern 165 may include an oxide (e.g., silicon oxide), and the first etch stop pattern 175 may include an insulating nitride (e.g., silicon nitride).

[0044] The bit line structure 395 may extend in the second direction D2 on portions of the first region I and the second region II of the substrate 100 adjacent to the first region I of the substrate 100, and a plurality of the bit line structures 395 may be spaced apart from each other in the first direction D1. In example embodiments, the bit line structure 395 may overlap a central portion in the third direction D3 of each of the first active patterns 101 disposed in the second direction D2. For example, the bit line structure 395 may overlap the second gate structure 320 in the second direction D2. As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting both elements A and B.

[0045] The bit line structure 395 may include a third conductive pattern 195, a bit line contact plug 265, a first barrier pattern 345, a fifth conductive pattern 355, and a fourth capping pattern 375. The first barrier pattern 345, the fifth conductive pattern 355, and the fourth capping pattern 375 may be sequentially stacked on the bit line contact plug 265 and the third conductive pattern 195.

[0046] The bit line contact plug 265 may contact the upper surface of the central portion in the third direction D3 of each of the first active patterns 101 disposed in the second direction D2, and may be disposed between adjacent second insulating pattern structures in the second insulating pattern structures (e.g., including the buffer pattern 165 and the first etch stop pattern 175) disposed in the second direction D2. Therefore, a plurality of bit line contact plugs 265 may be spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the substrate 100. In example embodiments, (e.g., in the case where the lower surface of the substrate 100 provides a base reference plane), the lowermost surface of the bit line contact plug 265 and the upper surface of the central portion of the first active pattern 101 may be lower than the lower surface of the second insulating pattern structure.

[0047] The third conductive pattern 195 may be formed on the second insulating pattern structure. Each of the bit line contact plug 265 and the third conductive pattern 195 may include, for example, polysilicon doped with n-type impurities, and therefore, in some embodiments, the bit line contact plug 265 and the third conductive pattern 195 may be merged with each other. The merged bit line contact plug 265 and the third conductive pattern 195 may extend in the second direction D2.

[0048] Each of the first barrier pattern 345, the fifth conductive pattern 355, and the fourth capping pattern 375 may extend in the second direction D2 on portions of the first and second regions I and II of the substrate 100 adjacent to the first region I of the substrate 100. A sidewall of an end portion of the fifth conductive pattern 355 in the second direction D2 may be covered by the first barrier pattern 345, and thus a cross-section of the first barrier pattern 345 in the second direction D2 may have an “L” shape (e.g., see Figure 2 and Figure 3 ). For example, an end portion of the first barrier pattern 345 in the second direction D2 may have an "L" shape in a cross-sectional view. For example, a cross-section of the first barrier pattern 345 in the second region II of the substrate 100 in the second direction D2 may have an "L" shape.

[0049] In an example embodiment, the upper surface of the end portion of the third conductive pattern 195 in the second direction D2 may not have the first barrier pattern 345 thereon (e.g., may not be covered by the first barrier pattern 345), and thus the first barrier pattern 345 and the third conductive pattern 195 may have a stepped shape in the second direction D2 (e.g., see Figure 2 and Figure 3 ). That is, the first barrier pattern 345 and the third conductive pattern 195 may have a stepped profile in common in the second direction D2. However, the inventive concept is not limited thereto, and the sidewalls of the ends of the first barrier pattern 345 and the third conductive pattern 195 in the second direction D2 may be aligned with each other in the vertical direction.

[0050] The first barrier pattern 345 may include metal silicon nitride (eg, titanium silicon nitride), the fifth conductive pattern 355 may include metal (eg, tungsten), and the fourth capping pattern 375 may include insulating nitride (eg, silicon nitride).

[0051] The first spacer 210 may be formed on a portion of the second region II adjacent to the first region I of the substrate 100, and may extend in the first direction D1. The first spacer 210 may contact an upper sidewall of the isolation structure 130, a sidewall of the second insulation pattern structure in the second direction D2 (e.g., a sidewall of the buffer pattern 165 and the first etch stop pattern 175 in the second direction D2), and a sidewall of the third conductive pattern 195 in the second direction D2.

[0052] The spacer structure 465 may be formed on each of the opposite sidewalls of the bit line structure 395 in the first direction D1, and may include a third spacer 400, an air spacer 435, and a fifth spacer 450 sequentially stacked in the first direction D1 (eg, see Figure 4 ).

[0053] The third spacer 400 may cover each of the opposite side walls of the bit line structure 395 in the first direction D1 and the upper surface of the second insulating pattern structure, the air spacer 435 may be formed on the outer sidewall of the third spacer 400, and the fifth spacer 450 may be on the outer sidewall of the air spacer 435 and the sidewall of the second insulating pattern structure (e.g., may cover the outer sidewall of the air spacer 435 and the sidewall of the second insulating pattern structure). In example embodiments (e.g., where the lower surface of the substrate 100 provides a base reference plane), the uppermost surface of the third spacer 400 may be higher than the uppermost surfaces of the air spacer 435 and the fifth spacer 450.

[0054] The sixth spacer 490 may be located on the outer sidewall of a portion of the third spacer 400 on the upper sidewall of the bit line structure 395, the top of the air spacer 435, and the upper surface and the upper outer sidewall of the fifth spacer 450 (for example, may cover the outer sidewall of a portion of the third spacer 400 on the upper sidewall of the bit line structure 395, the top of the air spacer 435, and the upper surface and the upper outer sidewall of the fifth spacer 450) (for example, see Figure 4 ).

[0055] Each of the first spacer 210 , the third spacer 400 , the fifth spacer 450 , and the sixth spacer 490 may include an insulating nitride (eg, silicon nitride), and the air spacer 435 may include air.

[0056] The first insulating pattern structure may include a first insulating pattern 410 and a second insulating pattern 420 sequentially stacked on the outer sidewall of a portion of the third spacer 400 disposed on the lower sidewall of the bit line contact plug 265 (eg, see Figure 4 ). The first insulating pattern structure may contact the bottom end of the air spacer 435 and the lower surface of the fifth spacer 450. The first insulating pattern 410 may include an oxide (eg, silicon oxide), and the second insulating pattern 420 may include an insulating nitride (eg, silicon nitride).

[0057] The first insulating interlayer 230 may be formed on the isolation structure 130 on the second region II of the substrate 100, and may contact sidewalls of the second gate structure 320, sidewalls of the source / drain layer 220, sidewalls of the first spacer 210, and lower portions of sidewalls in the second direction D2 of the first barrier pattern 345. The first insulating interlayer 230 may include an oxide (e.g., silicon oxide).

[0058] The protection pattern 330 may contact upper surfaces of the first insulating interlayer 230 and the second gate structure 320 and upper portions of sidewalls of the first barrier pattern 345 in the second direction D2. The protection pattern 330 may include insulating nitride (eg, silicon nitride).

[0059] The fifth capping pattern 377 may be formed on the protection pattern 330 on the second region II of the substrate 100, and may contact the sidewalls of the fourth capping pattern 375 and the fence pattern 480 on the first region I of the substrate 100. The fifth capping pattern 377 may include a material substantially the same as that of the fourth capping pattern 375, and in some embodiments, the fourth capping pattern 375 and the fifth capping pattern 377 may be indistinguishable from each other.

[0060] The contact plug structure may include a lower contact plug 475, an ohmic contact pattern 500, and an upper contact plug 559 sequentially stacked on the first active pattern 101 and the first isolation pattern 132 in a vertical direction (eg, see Figure 4 ).

[0061] The lower contact plug 475 may contact the upper surface of each of the opposite ends of the first active pattern 101 in the third direction D3. For example, the contact plug structure may be on the opposite ends of the first active pattern 101 in the third direction D3. In example embodiments, a plurality of lower contact plugs 475 may be spaced apart from each other in the second direction D2 between adjacent bit line structures 395 in the first direction D1 among the bit line structures 395, and a fence pattern 480 may be formed between adjacent lower contact plugs 475 in the second direction D2 among the lower contact plugs 475. The fence pattern 480 may include an insulating nitride (e.g., silicon nitride).

[0062] The lower contact plug 475 may include, for example, doped polysilicon, and the ohmic contact pattern 500 may include metal silicide (eg, titanium silicide, cobalt silicide, nickel silicide, etc.).

[0063] The upper contact plug 559 may include an eleventh conductive pattern 549 and a sixth barrier pattern 539 on a lower surface of (e.g., covering) the eleventh conductive pattern 549. The eleventh conductive pattern 549 may include a metal (e.g., tungsten), and the sixth barrier pattern 539 may include a metal nitride (e.g., titanium nitride).

[0064] In example embodiments, a plurality of upper contact plugs 559 may be spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the substrate 100 and may be arranged in a honeycomb pattern or a grid pattern in a plan view. Each of the upper contact plugs 559 may have a shape such as a circle, an ellipse, a polygon, etc.

[0065] The first contact plug 552 may be formed on a portion of the second region II adjacent to the first region I of the substrate 100, and may extend through the fourth capping pattern 375 to contact an upper surface of the fifth conductive pattern 355. The second contact plug 554 may be formed on the second region II of the substrate 100, and may extend through the fifth capping pattern 377 and the protection pattern 330 to contact an upper surface of the second gate electrode 310 (e.g., see Figure 2 ). The third contact plug 556 may be formed on the second region II of the substrate 100, and may extend through the fifth capping pattern 377 and the protection pattern 330 to contact the upper surface of the source / drain layer 220 (eg, see Figure 3 ).

[0066] The first contact plug 552 may include an eighth conductive pattern 542 and a third barrier pattern 532 on a lower surface and sidewalls of the eighth conductive pattern 542 (e.g., covering the lower surface and sidewalls of the eighth conductive pattern 542). The second contact plug 554 may include a ninth conductive pattern 544 and a fourth barrier pattern 534 on a lower surface and sidewalls of the ninth conductive pattern 544 (e.g., covering the lower surface and sidewalls of the ninth conductive pattern 544). The third contact plug 556 may include a tenth conductive pattern 546 and a fifth barrier pattern 536 on a lower surface and sidewalls of the tenth conductive pattern 546 (e.g., covering the lower surface and sidewalls of the tenth conductive pattern 546).

[0067] The wiring 551 may be formed on the second region II of the substrate 100 and may contact the upper surface of the first contact plug 552. The wiring 551 may also contact the upper surface of the second contact plug 554 and / or the upper surface of the third contact plug 556. In an example embodiment, the wiring 551 may extend in the second direction D2, and a plurality of wirings 551 may be spaced apart from each other in the first direction D1. However, the inventive concept is not limited thereto, and the wiring 551 may have various layouts. The wiring 551 may include a seventh conductive pattern 541 and a second barrier pattern 531 on a lower surface of the seventh conductive pattern 541 (e.g., covering the lower surface of the seventh conductive pattern 541).

[0068] Each of the second to fifth barrier patterns 531 , 532 , 534 , and 536 may include, for example, metal nitride, and each of the seventh to tenth conductive patterns 541 , 542 , 544 , and 546 may include, for example, metal.

[0069] Reference Figures 1 to 4 as well as Figures 44 to 47, the third insulation pattern structure may include a sixth insulation pattern 610 on the eleventh opening 567, a sixth insulation pattern 610 on the inner wall of the twelfth opening 569, and a seventh insulation pattern 620 on the sixth insulation pattern 610 and filling the remaining portions of the eleventh opening 567 and the twelfth opening 569, the sixth insulation pattern 610 on the eleventh opening 567 may extend through the wiring 551 and a portion of the fifth capping pattern 377, and the sixth insulation pattern 610 on the inner wall of the twelfth opening 569 may extend through the upper contact plug 559, the fourth capping pattern 375, the spacer structure 465, and a portion of the sixth spacer 490 to surround the upper contact plug 559 in a plan view. The top end of the air spacer 435 may be closed by the sixth insulation pattern 610.

[0070] The sixth and seventh insulating patterns 610 and 620 may include insulating nitride (eg, silicon nitride).

[0071] A third etch stop layer 630 may be formed on the wiring 551, the upper contact plug 559, and the third insulation pattern structure (eg, including the sixth insulation pattern 610 and the seventh insulation pattern 620). The third etch stop layer 630 may include an insulating nitride (eg, silicon boronitride).

[0072] The capacitor 670 may include a lower electrode 640 extending through the third etch stop layer 630 to contact an upper surface of the upper contact plug 559, a dielectric layer 650, and an upper electrode 660 on the dielectric layer 650. In example embodiments, the plurality of lower electrodes 640 may be spaced apart from each other in the first direction D1 and the second direction D2, and may be arranged in a honeycomb pattern in a plan view.

[0073] The semiconductor device may include a transistor on the second region II of the substrate 100, and the second gate structure 320 included in the transistor may contact an upper sidewall of the second active pattern 105 and an upper surface of the second active pattern 105 (eg, see Figure 2 ). That is, the transistor may not be a planar transistor but a FinFET. Therefore, the controllability of the second gate structure 320 on the channel in the second active pattern 105 may be enhanced in the transistor, and the GIDL or GIJL phenomenon may be reduced.

[0074] Figures 5 to 47 1 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. In particular, Figure 5 , Figure 7 , Fig.10 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig.23 , Fig.29 , Fig.34 , Fig.38 and Fig.44 It is a floor plan. Figure 6 , Figures 8 to 9 , Figures 11 to 13 , Fig.15 , Fig.17 , Fig.21 , Fig.24 , Fig.26 , Fig.28 , Figure 30 to Figure 33 , Fig.35 , Fig.41 and Fig.45 are sectional views taken along the line AA' of the corresponding plan view, Fig.19 , Fig. 22 , Fig.42 and Fig.46 are sectional views taken along line BB' of the corresponding plan view, Fig.25 , Fig. 27 , Figure 36 to Figure 37 , Figure 39 to Figure 40 , Fig.43 and Fig.47 They are respectively cross-sectional views taken along line CC' of the corresponding plan views.

[0075] Reference Figure 5 and Figure 6 , a second active pattern 105 may be formed on the substrate 100 including the first region I and the second region II, and a first sacrificial insulating layer 110 may be formed on the first region I and the second region II of the substrate 100 to cover the second active pattern 105 .

[0076] The second active pattern 105 may be formed by removing an upper portion of the second region II of the substrate 100 to form a first groove. In example embodiments, the second active pattern 105 may extend in the first direction D1 on the second region II of the substrate 100, and a plurality of second active patterns 105 may be spaced apart from each other in the second direction D2. Figure 5 A single second active pattern 105 is shown among the plurality of second active patterns 105. As another example, the second active pattern 105 may extend in the second direction D2 on the second region II of the substrate 100, and the plurality of second active patterns 105 may be spaced apart from each other in the first direction D1.

[0077] The first sacrificial insulating layer 110 may be on the upper surface and sidewalls of the second active pattern 105 and the upper surface of the first region I of the substrate 100 (e.g., may cover the upper surface and sidewalls of the second active pattern 105 and the upper surface of the first region I of the substrate 100), and may include silicon oxide (e.g., tonen silazene (TOSZ)).

[0078] Reference Figure 7 and Figure 8 A first etching mask can be formed on the first sacrificial insulating layer 110, and an etching process can be performed using the first etching mask to partially etch the first sacrificial insulating layer 110 and an upper portion of the substrate 100, so that the second groove 102 and the third groove 106 can be formed in the first region I of the substrate 100 and in the boundary between the first region I and the second region II of the substrate 100, respectively.

[0079] Through the etching process, the first sacrificial insulating layer 110 may be transformed into first and second sacrificial insulating patterns 112 and 114 on the first and second regions I and II of the substrate 100 , respectively, and the first active pattern 101 may be formed on the first region I of the substrate 100 .

[0080] In example embodiments, the first active pattern 101 may extend in the third direction D3 on the first region I of the substrate 100, and a plurality of first active patterns 101 may be spaced apart from each other in the first direction D1 and the second direction D2. In example embodiments, the third groove 106 may have a width and a depth greater than those of the second groove 102, respectively.

[0081] The first etch mask may be removed.

[0082] Reference Fig. 9 The first and second sacrificial insulating patterns 112 and 114 may be removed by, for example, a lift-off process, and the polysilicon layer 120 may be conformally formed on the first and second regions I and II of the substrate 100 having the first and second active patterns 101 and 105 thereon.

[0083] The isolation structure 130 may be formed on the polysilicon layer 120. The isolation structure 130 may be formed by sequentially forming a first isolation layer, a second isolation layer, and a third isolation layer on the polysilicon layer 120 and performing a planarization process on the first to third isolation layers until an upper surface of a portion of the first isolation layer on each of the first active pattern 101 and the second active pattern 105 is exposed. Each of the first isolation layer and the third isolation layer may include an oxide (e.g., silicon oxide), and the second isolation layer may include an insulating nitride (e.g., silicon nitride).

[0084] The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process. In example embodiments, the isolation structure 130 may include a first isolation pattern 132, a second isolation pattern 134, and a third isolation pattern 136 sequentially stacked on inner walls of the first and third grooves 106. However, only the first isolation pattern 132 may be formed in the second groove 102 having a width smaller than that of the third groove 106.

[0085] Reference Fig.10 and Fig.11 The first active pattern 101 and the isolation structure 130 on the first region I of the substrate 100 may be etched by an etching process to form a fourth groove extending in the first direction D1, and the first gate structure 150 may be formed in the fourth groove.

[0086] The first gate structure 150 may include a first gate insulating pattern 142 on the inner wall of the fourth groove, and a first conductive pattern 144, a second conductive pattern 146, and a first gate mask 148 sequentially stacked in a vertical direction on the first gate insulating pattern 142, and the first conductive pattern 144 and the second conductive pattern 146 may jointly form a first gate electrode. In example embodiments, the first gate structure 150 may extend in the first direction D1, and a plurality of first gate structures 150 may be spaced apart from each other in the second direction D2.

[0087] Reference Fig.12 , a buffer layer 160, a first etch stop layer 170 and a third sacrificial insulating layer 180 may be sequentially stacked on the first gate structure 150, the isolation structure 130 and the polysilicon layer 120, a second etch mask may be formed on the second region II of the substrate 100, and an etching process may be performed using the second etch mask to remove the buffer layer 160, the first etch stop layer 170 and the third sacrificial insulating layer 180 on the second region II of the substrate 100.

[0088] Each of the buffer layer 160 and the third sacrificial insulating layer 180 may include an oxide (eg, silicon oxide), and the first etch stop layer 170 may include an insulating nitride (eg, silicon nitride).

[0089] In an example embodiment, the third sacrificial insulating layer 180 and the buffer layer 160 may be removed by a wet etching process, and may be removed by using, for example, phosphoric acid (H 3 PO 4 ) is used to remove the first etch stop layer 170.

[0090] The second etch mask may be removed.

[0091] Reference Fig.13 , a wet etching process may be performed using, for example, HF, and thus upper portions of the first and third isolation patterns 132 and 136 included in the isolation structure 130 and the third sacrificial insulating layer 180 may be removed.

[0092] Through the wet etching process, portions of the polysilicon layer 120 on the upper surface and upper sidewalls of the second active pattern 105 may be exposed, and a plasma oxidation process may be performed on the exposed portions of the polysilicon layer 120. Thus, the exposed portions of the polysilicon layer 120 may be converted into oxide patterns 129.

[0093] A portion of the second isolation pattern 134 adjacent to the second active pattern 105 may include a protruding portion protruding from upper surfaces of the first isolation pattern 132 and the third isolation pattern 136 in a vertical direction.

[0094] Reference Fig.14 and Fig.15 , a dummy gate electrode layer and a dummy gate mask layer may be sequentially stacked on the first etch stop layer 170, the isolation structure 130, and the oxide pattern 129, and may be partially removed to form a dummy gate structure on the second region II of the substrate 100, and an initial bit line structure may be formed on portions of the first region I and the second region II of the substrate 100 that are adjacent to the first region I of the substrate 100.

[0095] The dummy gate electrode layer may include, for example, polysilicon, and the dummy gate mask layer may include an insulating nitride (eg, silicon nitride).

[0096] The dummy gate structure may include a dummy gate electrode 194 and a dummy gate mask 205 sequentially stacked in a vertical direction, and the initial bit line structure may include an initial third conductive layer 190 and a sacrificial mask layer 200 sequentially stacked in a vertical direction.

[0097] In example embodiments, the dummy gate structure may extend in the second direction D2 on the second region II of the substrate 100 to partially overlap the second active pattern 105 in the vertical direction, and the plurality of dummy gate structures may be spaced apart from each other in the first direction D1. Alternatively, if the second active pattern 105 extends in the second direction D2, the dummy gate structure may extend in the first direction D1, and the plurality of dummy gate structures may be spaced apart from each other in the second direction D2.

[0098] The initial bit line structure may be on (eg, may cover) portions of the first and second regions I and II of the substrate 100 adjacent to the first region I of the substrate 100 .

[0099] Reference Fig.16 and Fig.17 A first spacer layer may be formed on the dummy gate structure, the initial bit line structure, the isolation structure, and the oxide pattern 129, and may be anisotropically etched to form a first spacer 210 and a second spacer 215 on the sidewalls of the initial bit line structure and the sidewalls of the dummy gate structure, respectively.

[0100] In example embodiments, the first spacer layer may include a material substantially the same as that of the dummy gate mask layer (e.g., an insulating nitride such as silicon nitride), and thus, in some embodiments, the first spacer 210 and the second spacer 215 may be merged with the sacrificial mask layer 200 and the dummy gate mask 205, respectively.

[0101] Reference Fig.18 and Fig.19 , portions of the oxide pattern 129 on the upper surface and upper sidewalls of the second active pattern 105 that are not covered by the dummy gate structure and the second spacer 215 and an upper portion of the second active pattern 105 below the portion of the oxide pattern 129 can be removed to form a fifth groove, and a selective epitaxial growth (SEG) process can be performed using the upper surface of the portion of the second active pattern 105 below the fifth groove to form a source / drain layer 220.

[0102] In example embodiments, a cross-section of the source / drain layer 220 in the second direction D2 may have a shape such as a rhombus or a pentagon. If the distance between the second active patterns 105 disposed in the second direction D2 is small, the source / drain layers 220 on adjacent second active patterns 105 in the second direction D2 may merge with each other.

[0103] Reference Figure 20 to Figure 22 A first insulating interlayer 230 may be formed on the dummy gate structure, the initial bit line structure, the first and second spacers 210 and 215, the isolation structure 130, and the source / drain layer 220, and a planarization process may be performed on the first insulating interlayer 230 until an upper surface of the dummy gate mask is exposed.

[0104] The first insulating interlayer 230 may include oxide (eg, silicon oxide), and the planarization process may include, for example, a CMP process and / or an etch-back process.

[0105] A third etching mask covering the second region II of the substrate 100 may be formed, and the sacrificial mask layer 200 and upper portions of the preliminary third conductive layer 190 may be removed so that the thickness of the preliminary third conductive layer 190 may be reduced.

[0106] An ion implantation process may be performed on the preliminary third conductive layer 190 to form a third conductive layer 193 including, for example, n-type impurities.

[0107] The third etch mask may be removed.

[0108] Reference Figure 23 to Figure 25A second insulating interlayer 240 can be formed on the dummy gate mask 205, the first insulating interlayer 230, the first spacer 210 and the third conductive layer 193, a fourth etching mask can be formed on the second insulating interlayer 240, and an etching process can be performed using the fourth etching mask to pattern a portion of the second insulating interlayer 240 on the first region I of the substrate 100, the third conductive layer 193, the first etch stop layer 170, the buffer layer 160, the polysilicon layer 120 and the first active pattern 101, so that a first opening 250 can be formed.

[0109] In example embodiments, after the etching process, a portion of the second insulating interlayer 240 remaining on the first region I of the substrate 100 may have a shape such as a circle or an ellipse in a plan view, and a plurality of second insulating interlayers 240 may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the second insulating interlayers 240 may overlap in a vertical direction an end portion of an adjacent first active pattern 101 in the second direction D2 in the third direction D3 of the first active pattern 101. The second insulating interlayer 240 may include an oxide (e.g., silicon oxide), and in some embodiments, the second insulating interlayer 240 may be merged with the first insulating interlayer 230.

[0110] The fourth etch mask may be removed.

[0111] Reference Fig.26 and Fig. 27 , a bit line contact plug layer may be formed on the first active pattern 101 and the second insulating interlayer 240 to fill the first opening 250 , and, for example, an etch-back process may be performed on the bit line contact plug layer to form a bit line contact plug 265 in a lower portion of the first opening 250 .

[0112] In example embodiments, an upper surface of the bit line contact plug 265 may be substantially coplanar with an upper surface of the third conductive layer 193. The bit line contact plug 265 may include, for example, polysilicon doped with n-type impurities, and may be merged with the third conductive layer 193 in some embodiments.

[0113] A third insulating interlayer may be formed on the bit line contact plug 265 and the second insulating interlayer 240 to fill an upper portion of the first opening 250 , and a planarization process may be performed on the third insulating interlayer, the second insulating interlayer 240 , and the first insulating interlayer 230 .

[0114] In example embodiments, after a planarization process, (eg, where the lower surface of the substrate 100 provides a base reference plane), upper surfaces of the third insulating interlayer, the second insulating interlayer 240 , and the first insulating interlayer 230 may be lower than an upper surface of the dummy gate electrode 194 .

[0115] The third insulating interlayer may include a material substantially the same as that of the second insulating interlayer 240 (e.g., an oxide such as silicon oxide), and in some embodiments, the third insulating interlayer may be merged with the second insulating interlayer 240. Hereinafter, after removing an upper portion of the merged structure including the third insulating interlayer and the second insulating interlayer 240, the remaining portion of the merged structure may be referred to as a fourth insulating interlayer 270.

[0116] Reference Fig.28 , a second etch stop layer 280 may be formed on the dummy gate mask 205 and the first and fourth insulating interlayers 230 and 270 , and a planarization process may be performed on the second etch stop layer 280 .

[0117] The second etch stop layer 280 may include a material substantially the same as that of the dummy gate mask 205 (e.g., an insulating nitride such as silicon nitride), and a planarization process may be performed until an upper surface of the dummy gate electrode 194 is exposed. Thus, the second etch stop layer 280 may remain on the first insulating interlayer 230 and the fourth insulating interlayer 270.

[0118] Reference Fig.29 and Fig.30 The exposed dummy gate electrode 194 and the oxide pattern 129 thereunder may be removed by, for example, a wet etching process and / or a dry etching process to form a second opening, and thus the upper surface and upper sidewalls of the second active pattern 105 may be exposed.

[0119] This can be accomplished by, for example, using phosphoric acid (H 3 PO 4 ) to remove the second etch stop layer 280, and thus the upper surfaces of the first insulating interlayer 230 and the fourth insulating interlayer 270 may be exposed. During the stripping process, the second spacer 215 and the protruding portion of the second isolation pattern 134 exposed by the second opening may also be removed.

[0120] An oxidation process may be performed on the upper surface and upper sidewalls of the second active pattern 105 to form the interface pattern 290. A deposition process may be performed on the interface pattern 290, the isolation structure 130, the sidewall and upper surface of the first insulating interlayer 230, and the upper surface of the fourth insulating interlayer 270 to form a high-k dielectric layer, and a fourth conductive layer may be formed on the high-k dielectric layer to fill the second opening.

[0121] A planarization process may be performed on the fourth conductive layer and the high-k dielectric layer until upper surfaces of the first insulating interlayer 230 and the fourth insulating interlayer 270 are exposed, and thus a fourth conductive pattern 310 and a high-k dielectric pattern 300 may be formed in the second opening.

[0122] The planarization process may include a CMP process and / or an etch-back process.The interface pattern 290, the high-k dielectric pattern 300, and the fourth conductive pattern 310 may collectively form a second gate structure 320, and the interface pattern 290 and the high-k dielectric pattern 300 may collectively form a second gate insulation pattern.

[0123] Alternatively, the interface pattern 290 may be formed by a deposition process instead of an oxidation process, and in this case, the interface pattern 290 may be formed on the upper surface of the isolation structure 130 and the sidewalls of the first insulating interlayer 230 and the upper surface and upper sidewalls of the second active pattern 105 .

[0124] Reference Fig.31 A protective layer can be formed on the second gate structure 320 and the first insulating interlayer 230 and the fourth insulating interlayer 270, a fifth etching mask can be formed on the protective layer to cover the second region II of the substrate 100, and the fifth etching mask can be used to etch the protective layer and the fourth insulating interlayer 270, so that the protective layer can be converted into a protective pattern 330, and most of the fourth insulating interlayer 270 can be removed to expose the upper surface of the third conductive layer 193.

[0125] Hereinafter, the portion of the fourth insulating interlayer 270 remaining on the first spacer 210 after the etching process is considered to be merged with the first insulating interlayer 230 adjacent thereto. The protection pattern 330 may be on the upper surfaces of the second gate structure 320 and the first insulating interlayer 230 (e.g., may cover the upper surfaces of the second gate structure 320 and the first insulating interlayer 230).

[0126] The fifth etch mask may be removed.

[0127] Reference Fig.32 , a first barrier layer 340 , a fifth conductive layer 350 , and a second capping layer 360 may be sequentially stacked on the protection pattern 330 and the third conductive layer 193 .

[0128] The second capping layer 360 may include insulating nitride (eg, silicon nitride).

[0129] Reference Fig.33 A sixth etching mask may be formed on the second covering layer 360 to cover portions of the first region I and the second region II of the substrate 100 that are adjacent to the first region I of the substrate 100, and the second covering layer 360, the fifth conductive layer 350, and the first barrier layer 340 may be etched using the sixth etching mask.

[0130] Therefore, the second covering layer 360, the fifth conductive layer 350 and the first barrier layer 340 may remain on the portions of the first region I and the second region II of the substrate 100 adjacent to the first region I of the substrate 100, and the upper surface of the protection pattern 330 and the upper surfaces of the portions of the first barrier layer 340 and the fifth conductive layer 350 adjacent to the protection pattern 330 may be exposed.

[0131] The sixth etch mask may be removed.

[0132] Reference Figure 34 to Figure 36 , a third capping layer may be formed on the protection pattern 330, the second capping layer 360, and the exposed portions of the first barrier layer 340 and the fifth conductive layer 350, and a planarization process may be performed on the third capping layer.

[0133] The third capping layer may include an insulating nitride (eg, silicon nitride). In some embodiments, the third capping layer and the second capping layer 360 may be merged with each other, and the third capping layer and the second capping layer 360 may be collectively referred to as a fourth capping layer.

[0134] A portion of the fourth cover layer on the first region I of the substrate 100 may be patterned to form a fourth cover pattern 375, and the remaining portion of the fourth cover layer on the second region II of the substrate 100 may be referred to as a fifth cover pattern 377. In example embodiments, the fourth cover pattern 375 may extend in the second direction D2, and a plurality of fourth cover patterns 375 may be spaced apart from each other in the first direction D1. Each of the fourth cover patterns 375 may overlap in a vertical direction with a central portion of a corresponding one of the first active patterns 101 in the third direction D3.

[0135] The fifth conductive layer 350, the first barrier layer 340, the third conductive layer 193, and the bit line contact plug 265 on the first region I of the substrate 100 and a portion of the second region II adjacent to the first region I of the substrate 100 may be patterned by an etching process using the fourth capping pattern 375 and the fifth capping pattern 377 as etching masks.

[0136] Therefore, the lower portion of the first opening 250 may be formed again, the bit line contact plug 265, the first barrier pattern 345, the fifth conductive pattern 355, and the fourth capping pattern 375 sequentially stacked in the vertical direction may be formed on the first active pattern 101 exposed by the first opening 250, and the third conductive pattern 195, the first barrier pattern 345, the fifth conductive pattern 355, and the fourth capping pattern 375 sequentially stacked in the vertical direction may be formed on the first etch stop layer 170. The bit line contact plug 265, the third conductive pattern 195, the first barrier pattern 345, the fifth conductive pattern 355, and the fourth capping pattern 375 may collectively form a bit line structure 395.

[0137] In example embodiments, the bit line structure 395 may extend in the second direction D2 on portions of the first and second regions I and II of the substrate 100 adjacent to the first region I of the substrate 100 , and a plurality of the bit line structures 395 may be spaced apart from each other in the first direction D1 .

[0138] Reference Fig.37 A third spacer layer may be formed on the upper surface and sidewalls of the bit line structure 395, the upper surface of the fifth covering pattern 377, the upper surface of the first etch stop layer 170, and the inner wall of the first opening 250, and a first insulating layer and a second insulating layer may be sequentially formed on the third spacer layer.

[0139] The first insulating layer and the second insulating layer may be etched by an etching process. In example embodiments, the first insulating layer and the second insulating layer may be etched by using an etching solution (e.g., phosphoric acid (H 3 PO 4 ), SCl, HF, etc.), and all portions of the first insulating layer and the second insulating layer except the portions of the first insulating layer and the second insulating layer in the first opening 250 may be removed. Therefore, most of the surface of the third spacer layer (that is, all portions of the surface of the third spacer layer except the portion of the surface of the third spacer layer in the first opening 250) may be exposed, and the portions of the first insulating layer and the second insulating layer remaining in the first opening 250 may form the first insulating pattern 410 and the second insulating pattern 420, respectively. The first insulating pattern 410 and the second insulating pattern 420 may form a first insulating pattern structure together.

[0140] A fourth spacer layer can be formed on the exposed surface of the third spacer layer and the first insulating pattern 410 and the second insulating pattern 420 in the first opening 250, and the fourth spacer layer can be anisotropically etched to form a fourth spacer 430 on the surface of the third spacer layer and the first insulating pattern 410 and the second insulating pattern 420, and the third spacer layer and the first insulating pattern 410 and the second insulating pattern 420 will be on the sidewalls of the bit line structure 395 (for example, covering the sidewalls of the bit line structure 395).

[0141] For example, a dry etching process may be further performed to form a third opening 440 exposing an upper surface of the first active pattern 101 , and an upper surface of the first isolation pattern 132 , an upper surface of the first gate mask 148 , and an uppermost surface of the polysilicon layer 120 may also be exposed by the third opening 440 .

[0142] Through the dry etching process, portions of the third spacer layer on upper surfaces of the bit line structure 395 , the fifth capping pattern 377 , and the first etch stop layer 170 may be removed, and thus the third spacer 400 may be formed on the sidewall of the bit line structure 395 .

[0143] During the dry etching process, the buffer layer 160 and the first etch stop layer 170 may also be partially removed to form a buffer pattern 165 and a first etch stop pattern 175 respectively under the bit line structure 395 , and the buffer pattern 165 and the first etch stop pattern 175 may together form a second insulating pattern structure.

[0144] Reference Fig.38 and Fig.39 , a fifth spacer layer can be formed on the upper surfaces of the bit line structure 395, the fifth covering pattern 377 and the third spacer 400, the upper surface and outer side walls of the fourth spacer 430, a portion of the upper surface of the first insulating pattern structure, and the upper surfaces of the first active pattern 101, the first isolation pattern 132 and the first gate mask 148 exposed by the third opening 440, and can be anisotropically etched to form a fifth spacer 450 on the outer side walls of the fourth spacer 430 on the side walls of the bit line structure 395 (for example, the fifth spacer 450 is formed to cover the outer side walls of the fourth spacer 430 on the side walls of the bit line structure 395).

[0145] The third to fifth spacers 400 , 430 , and 450 sequentially stacked on the sidewalls of the bit line structure 395 in a horizontal direction may be collectively referred to as a preliminary spacer structure 460 .

[0146] A sixth conductive layer may be formed on the substrate 100 to fill the third opening 440 , and may be planarized until upper surfaces of the bit line structure 395 and the fifth capping pattern 377 are exposed to form a lower contact plug 475 .

[0147] The lower contact plugs 475 may extend in the second direction D2 between adjacent bit line structures 395 in the first direction D1 among the bit line structures 395 on the first region I of the substrate 100, and a plurality of the lower contact plugs 475 may be spaced apart from each other in the first direction D1. Each of the lower contact plugs 475 may contact an upper surface of an end portion of the corresponding first active pattern 101 in the third direction D3.

[0148] A seventh etching mask having fourth openings may be formed on the bit line structure 395, the fifth capping pattern 377, and the lower contact plugs 475, and the lower contact plugs 475 may be etched using the seventh etching mask to form fifth openings, each of which may extend in the first direction D1 and be spaced apart from each other in the second direction D2.

[0149] In example embodiments, each of the fourth openings may overlap the first gate structure 150 in a vertical direction, and thus the fifth opening may expose an upper surface of the first gate mask 148 of the first gate structure 150. When the fifth opening is formed, the lower contact plug 475 extending in the second direction D2 may be divided into a plurality of pieces spaced apart from each other in the second direction D2.

[0150] After removing the seventh etch mask, a fence pattern 480 may be formed in the fifth opening. In example embodiments, a plurality of fence patterns 480 may be spaced apart from each other in the second direction D2 between adjacent ones of the bit line structures 395 in the first direction D1.

[0151] The lower contact plugs 475 and the fence patterns 480 may be alternately arranged in the second direction D2 in the following manner: lower contact plugs 475 extending in the second direction D2 are formed between adjacent bit line structures 395 in the first direction D1 in the bit line structure 395, fifth openings spaced apart from each other in the second direction D2 are formed through the lower contact plugs 475, and fence patterns 480 are formed in the fifth openings, respectively; however, the inventive concept is not limited thereto.

[0152] In other example embodiments, the lower contact plugs 475 and the fence pattern 480 may be alternately arranged in the second direction D2 in the following manner: a fence layer extending in the second direction D2 is formed between adjacent bit line structures 395 in the first direction D1 in the bit line structure 395, sixth openings spaced apart from each other in the second direction D2 are formed through the fence layer, and lower contact plugs 475 are respectively formed in the sixth openings.

[0153] In other example embodiments, the lower contact plugs 475 and the fence patterns 480 may be alternately arranged in the second direction D2 by forming a fourth sacrificial insulating layer, forming fence patterns 480 spaced apart from each other in the second direction D2 through the fourth sacrificial insulating layer, removing the fourth sacrificial insulating layer to form seventh openings, and forming lower contact plugs 475 in the seventh openings, respectively, the fourth sacrificial insulating layer extending in the second direction D2 between adjacent bit line structures 395 in the first direction D1 in the bit line structure 395 and including oxide (e.g., silicon oxide).

[0154] Reference Fig.40 , an upper portion of the lower contact plug 475 may be removed to expose an upper portion of the preliminary spacer structure 460 on the sidewall of the bit line structure 395 , and upper portions of the fourth and fifth spacers 430 and 450 of the exposed preliminary spacer structure 460 may be removed.

[0155] The upper portion of the lower contact plug 475 may be further removed. Therefore, the upper surface of the lower contact plug 475 may be lower than the uppermost surfaces of the fourth and fifth spacers 430 and 450 (eg, where the lower surface of the substrate 100 provides a base reference plane).

[0156] The sixth spacer layer may be formed on the bit line structure 395, the fifth capping pattern 377, the preliminary spacer structure 460, the fence pattern 480, and the lower contact plug 475, and may be anisotropically etched to form the sixth spacer 490 on the upper portion of the preliminary spacer structure 460 on each of the opposite side walls of the bit line structure 395 in the first direction D1 (e.g., the sixth spacer 490 is formed to cover the upper portion of the preliminary spacer structure 460 on each of the opposite side walls of the bit line structure 395 in the first direction D1). Thus, the upper surface of the lower contact plug 475 may be exposed.

[0157] The ohmic contact pattern 500 may be formed on the exposed upper surface of the lower contact plug 475. In example embodiments, the ohmic contact pattern 500 may be formed by forming a metal layer on the bit line structure 395, the fifth capping pattern 377, the third and sixth spacers 400 and 490, the fence pattern 480, and the lower contact plug 475, and performing a heat treatment process on the metal layer. Unreacted portions of the metal layer may be removed.

[0158] Reference Figure 41 to Figure 43 , an eighth opening may be formed, the eighth opening extending through a portion of the fourth covering pattern 375 to expose an upper surface of the fifth conductive pattern 355 on a portion of the second region II adjacent to the first region I of the substrate 100 in the second direction D2; a ninth opening may be formed, the ninth opening extending through the fifth covering pattern 377 and the protection pattern 330 to expose an upper surface of the second gate electrode 310; and a tenth opening may be formed, the tenth opening extending through the fifth covering pattern 377, the protection pattern 330 and an upper portion of the first insulating interlayer 230 to expose an upper surface of the source / drain layer 220; a second blocking layer 530 may be formed on the upper surfaces of the fifth conductive pattern 355, the second gate electrode 310 and the source / drain layer 220 exposed by the eighth opening to the tenth opening, and the bit line structure 395, the fifth covering pattern 377, the third spacer 400 and the sixth spacer 490 and the ohmic contact pattern 500; and a seventh conductive layer 540 may be formed to fill the eighth opening to the tenth opening.

[0159] Hereinafter, portions of the second barrier layer 530 in the eighth to tenth openings may be respectively referred to as third to fifth barrier patterns 532, 534, and 536, and portions of the seventh conductive layer 540 in the eighth to tenth openings may be respectively referred to as eighth to tenth conductive patterns 542, 544, and 546. The third barrier pattern 532 and the eighth conductive pattern 542 may collectively form a first contact plug 552, the fourth barrier pattern 534 and the ninth conductive pattern 544 may collectively form a second contact plug 554, and the fifth barrier pattern 536 and the tenth conductive pattern 546 may collectively form a third contact plug 556.

[0160] Reference Figures 44 to 47 , the seventh conductive layer 540 and the second barrier layer 530 may be patterned.

[0161] Thus, the upper contact plug 559 may be formed on the first region I of the substrate 100, and the wiring 551 may be formed on the second region II of the substrate 100. The eleventh opening 567 may be formed between the wirings 551, and the twelfth opening 569 may be formed between the upper contact plugs 559.

[0162] The eleventh opening 567 can be formed by partially removing not only the seventh conductive layer 540 and the second barrier layer 530 but also the upper portion of the fifth covering pattern 377, and the twelfth opening 569 can be formed by partially removing not only the seventh conductive layer 540 and the second barrier layer 530 but also the fourth covering pattern 375, the fence pattern 480, the initial spacer structure 460 and the sixth spacer 490, and thus the twelfth opening 569 can expose the upper surface of the fourth spacer 430.

[0163] The wiring 551 may include a seventh conductive pattern 541 and a second barrier pattern 531 on a lower surface of (eg, covering a lower surface of) the seventh conductive pattern 541 , and the upper contact plug 559 may include an eleventh conductive pattern 549 and a sixth barrier pattern 539 .

[0164] In example embodiments, a plurality of upper contact plugs 559 may be spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the substrate 100 and may be arranged in a honeycomb pattern. Each of the upper contact plugs 559 may have a shape such as a circle, an ellipse, or a polygon in a plan view.

[0165] The lower contact plug 475 , the ohmic contact pattern 500 , and the upper contact plug 559 may collectively form a contact plug structure on the first region I of the substrate 100 .

[0166] The wiring 551 can have various layouts. Fig.44It is shown that the plurality of wirings 551 are spaced apart from each other in the first direction D1 , and each of the wirings 551 extends in the second direction D2 , however, the inventive concept is not limited thereto.

[0167] Refer again Figures 1 to 4 , the fourth spacer 430 may be removed to form an air gap 435 connected to the twelfth opening 569. The fourth spacer 430 may be removed by, for example, a wet etching process.

[0168] In example embodiments, not only the portion of the fourth spacer 430 directly exposed by the twelfth opening 569 but also other portions of the fourth spacer 430 parallel thereto in a horizontal direction may be removed by the wet etching process. That is, not only the portion of the fourth spacer 430 exposed by the twelfth opening 569 and not covered by the upper contact plug 559 but also the portion of the fourth spacer 430 covered by the upper contact plug 559 may be removed by the wet etching process.

[0169] A third insulation pattern structure may be formed to fill the twelfth opening 569 .

[0170] In example embodiments, the third insulating pattern structure may include a sixth insulating pattern 610 and a seventh insulating pattern 620 stacked sequentially. The sixth insulating pattern 610 may be formed using an insulating material having a poor gap filling property, and thus the air gap 435 under the twelfth opening 569 may not be filled. The air gap 435 may also be referred to as an air spacer 435, and the third spacer 400 and the fifth spacer 450 and the air spacer 435 may collectively form a spacer structure 465. The air gap 435 may be a spacer including air.

[0171] The capacitor 670 may be formed to contact an upper surface of the upper contact plug 559 .

[0172] That is, the third etch stop layer 630 and the mold layer may be formed on the upper contact plug 559 , the third insulation pattern structure, and the wiring 551 , and may be partially etched to form a thirteenth opening exposing the upper surface of the upper contact plug 559 .

[0173] The lower electrode layer may be formed on the exposed upper surface of the upper contact plug 559 and the mold layer to fill the thirteenth opening, and may be planarized until the upper surface of the mold layer is exposed to divide the lower electrode layer. For example, a wet etching process may be performed to remove the mold layer, and a lower electrode 640 having a columnar shape may be formed on the upper surface of the upper contact plug 559. Alternatively, the lower electrode 640 may be formed in a cylindrical shape in the ninth opening.

[0174] A dielectric layer 650 may be formed on the lower electrode 640 and the third etch stop layer 630 , and an upper electrode 660 may be formed on the dielectric layer 650 to form a capacitor 670 including the lower electrode 640 , the dielectric layer 650 , and the upper electrode 660 on the first region I of the substrate 100 .

[0175] Contact plugs and upper wirings may be further formed to be electrically connected to the capacitor 670 , the bit line structure 395 , and the wiring 551 , so that the manufacture of the semiconductor device may be completed.

[0176] As described above, the second active pattern 105 may be formed on the second region II of the substrate 100, the first active pattern 101 may be formed on the first region I of the substrate 100, and the first gate structure 150 may be formed on the first region I of the substrate 100. A dummy gate electrode layer may be formed on the first region I and the second region II of the substrate 100, and may be patterned to form an initial third conductive layer 190 and a dummy gate electrode 194, respectively.

[0177] A source / drain layer 220 may be formed on the second active pattern 105 adjacent to the dummy gate electrode 194, the thickness of the initial third conductive layer 190 may be reduced, and an ion implantation process may be performed on the initial third conductive layer 190 to form a third conductive layer 193. A bit line contact plug 265 may be formed through the third conductive layer 193 to contact an upper surface of the first active pattern 101, the dummy gate electrode 194 may be removed, and a second gate structure 320 may be formed.

[0178] The first barrier layer 340, the fifth conductive layer 350, and the fourth capping layer may be formed on the third conductive layer 193 and the bit line contact plug 265, and may be patterned to form a bit line structure 395. A contact plug structure may be formed between the bit line structures 395, and a capacitor 670 may be formed on the contact plug structure to manufacture a semiconductor device including a FinFET on the second region II of the substrate 100.

[0179] Fig.48 is a diagram showing a method corresponding to Figure 2 A cross-sectional view of a semiconductor device.

[0180] In addition to some components, the semiconductor device can be Figures 1 to 4 The semiconductor devices are substantially the same or similar, and thus repeated explanations are omitted here.

[0181] Reference Fig.48, the lower sidewall of the second active pattern 105 may be covered by the fifth insulating interlayer pattern 115 instead of the isolation structure 130. For example, the fifth insulating interlayer pattern 115 may be on the lower sidewall of the second active pattern 105, and the fifth insulating interlayer pattern 115 may be between the isolation structure 130 and the lower sidewall of the second active pattern 105.

[0182] The fifth insulating interlayer pattern 115 may be formed on the second region II of the substrate 100, and may also be formed on a portion of the isolation structure 130. Thus, the second gate structure 320 may be formed on the second active pattern 105 and the fifth insulating interlayer pattern 115. For example, the fifth insulating interlayer pattern 115 may be between the isolation structure 130 and the second gate structure 320. The fifth insulating interlayer pattern 115 may include an oxide (e.g., silicon oxide).

[0183] The second spacer 215 may be formed on a sidewall of the second gate structure 320 and may contact a sidewall of the first insulating interlayer 230. The second spacer 215 may include a material substantially the same as that of the first spacer 210.

[0184] The end of the first barrier pattern 345 in the bit line structure 395 included in the second region II of the substrate 100 in the second direction D2 may be on the upper surface of the first spacer 210 and the portion of the upper surface of the first insulating interlayer 230 (e.g., may cover the upper surface of the first spacer 210 and the portion of the upper surface of the first insulating interlayer 230). Therefore, the end of the first barrier pattern 345 and the end of the third conductive pattern 195 on the second region II of the substrate 100 may have a stepped shape. That is, the end of the first barrier pattern 345 and the end of the third conductive pattern 195 on the second region II of the substrate 100 may have a stepped profile together.

[0185] Figures 49 to 53 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0186] The method may include referring to Figures 1 to 47 The processes shown are substantially the same or similar processes, and thus repeated explanations thereof are omitted here.

[0187] Reference Fig.49 , executable and reference Figures 5 to 9 The illustrated processes are substantially the same or similar processes to form the first active pattern 101 on the first region I of the substrate 100 , and the isolation structure 130 may be formed on the first region I and the second region II of the substrate 100 .

[0188] However, forming the second active pattern 105 on the second region II of the substrate 100 may not be performed, and the second isolation pattern 134 included in the isolation structure 130 may be formed on the upper surface of the portion of the first isolation pattern 132 on the first region I and the second region II of the substrate 100 and on the upper surface of the portion of the first isolation pattern 132 in the third groove 106.

[0189] Reference Fig.50 An eighth etching mask may be formed on the isolation structure 130 to cover a portion of the second region II of the substrate 100 and the first region I of the substrate 100, and the isolation structure 130 and the second region II of the substrate 100 may be partially etched by an etching process using the eighth etching mask to form a second active pattern 105 on the second region II of the substrate 100.

[0190] During the etching process, portions of the first and second isolation patterns 132 and 134 on the second active pattern 105 may be converted into first and second insulating masks 133 and 135 , respectively, and a sixth groove 700 may be formed on the second region II of the substrate 100 .

[0191] The eighth etch mask may be removed.

[0192] Reference Fig.51 A fifth insulating interlayer may be formed on the isolation structure 130 and the second insulating mask 135 to fill the sixth groove 700 , and a planarization process may be performed on the fifth insulating interlayer until an upper surface of the second insulating mask 135 is exposed to form a fifth insulating interlayer pattern 115 .

[0193] A wet etching process may be performed on the fifth insulating interlayer pattern 115 until the upper surface of the third isolation pattern 136 is exposed, and the portion of the second isolation pattern 134 on the first region I of the substrate 100 and the second insulating mask 135 may be removed by, for example, a stripping process. Thus, the uppermost surface of the second isolation pattern 134 remaining in the third groove 106 may be substantially coplanar with the uppermost surface of the first isolation pattern 132 and the upper surface of the first insulating mask 133.

[0194] Reference Fig.52 , executable and reference Figures 10 to 12 The processes shown are substantially the same or similar processes to form the first gate structure 150 , the buffer layer 160 , the first etch stop layer 170 , and the third sacrificial insulating layer 180 .

[0195] However, the polysilicon layer 120 may not be formed, and the first insulating mask 133 may be removed during the above process.

[0196] Reference Fig.53 , executable and reference Fig.13 The illustrated process is substantially the same or similar to the process to remove the upper portion of the fifth insulation interlayer pattern 115 and the third sacrificial insulation layer 180 , and thus the upper portion of the second active pattern 105 may be exposed.

[0197] In addition, a plasma oxidation process may be performed on the upper surface and upper sidewalls of the second active pattern 105 to form an oxide pattern 129 .

[0198] Reference Fig.48 , executable and reference Figures 14 to 47 as well as Figures 1 to 4 The processes shown are basically the same or similar processes for manufacturing semiconductor devices.

[0199] As mentioned above, with reference Figures 1 to 47 The method of manufacturing the semiconductor device shown is different, the first active pattern 101 can be formed on the first area I of the substrate 100, the second active pattern 105 can be formed on the second area II of the substrate 100, and the lower side wall of the second active pattern 105 can be covered by the fifth insulating interlayer pattern 115 instead of the isolation structure 130.

[0200] Fig.54 is a diagram showing a method that can correspond to Figure 2 A cross-sectional view of a semiconductor device.

[0201] In addition to some components, the semiconductor device can be Figures 1 to 4 The semiconductor devices are substantially the same or similar, and thus repeated explanations are omitted here.

[0202] Reference Fig.54 , the sidewall of the fifth conductive pattern 355 in the second direction D2 may not be covered by the first barrier pattern 345, and the cross-section of the first barrier pattern 345 in the second direction D2 may not have an “L” shape. That is, the sidewall of the fifth conductive pattern 355 in the second direction D2 may not have the first barrier pattern 345 thereon.

[0203] In addition, sidewalls of the ends of the third conductive pattern 195 in the second direction D2 may be vertically aligned with sidewalls of the first barrier pattern 345 and the fifth conductive pattern 355 in the second direction D2.

[0204] A fourth etch stop layer 710 may be formed on the second gate structure 320, the first insulating interlayer 230, the first spacer 210, and the second capping layer 360, and a fourth capping pattern 375 and a fifth capping pattern 377 may be formed on the fourth etch stop layer 710. The fourth etch stop layer 710 may include an insulating nitride (e.g., silicon nitride).

[0205] Figures 55 to 60is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0206] The method may include referring to Figures 48 to 53 or Figures 1 to 47 The processes shown are substantially the same or similar processes, and thus repeated explanations thereof are omitted here.

[0207] Reference Fig.55 , executable and reference Figure 49 to Figure 53 The illustrated processes are substantially the same or similar processes, and a dummy gate electrode layer and a dummy gate mask layer may be sequentially stacked on the first etch stop layer 170 , the isolation structure 130 , the fifth insulating interlayer pattern 115 , and the oxide pattern 129 .

[0208] Executable and Reference Figure 20 to Figure 22 The process shown is substantially the same as or similar to the process to form a third etching mask covering the second region II of the substrate 100, and an etching process may be performed using the third etching mask to remove upper portions of the dummy gate mask layer and the dummy gate electrode layer.

[0209] Therefore, the thickness of the dummy gate electrode layer on the first region I of the substrate 100 and the portion of the second region II adjacent to the first region I of the substrate 100 may be reduced, and an initial dummy gate electrode 192 and an initial dummy gate mask 202 may be formed on the second region II of the substrate 100 .

[0210] An ion implantation process may be performed on a portion of the dummy gate electrode layer on the first region I of the substrate 100 and a portion of the second region II adjacent to the first region I of the substrate 100 to form a third conductive layer 193 including, for example, n-type impurities.

[0211] Reference Fig.56 , executable and reference Figure 23 to Figure 27 The illustrated process is substantially the same or similar to the process to form a bit line contact plug 265 passing through the third conductive layer 193 , the first etch stop layer 170 , the buffer layer 160 , and an upper portion of the first active pattern 101 .

[0212] However, the fourth insulating interlayer 270 may not be formed on the third conductive layer 193 and the bit line contact plug 265 .

[0213] Reference Fig.57 , executable and reference Fig.32 and Fig.33 The process shown is substantially the same or similar process to form a first barrier layer 340 , a fifth conductive layer 350 , and a second covering layer 360 sequentially stacked in a vertical direction on portions of the first region I and the second region II of the substrate 100 adjacent to the first region I of the substrate 100 .

[0214] The first barrier layer residue 342 and the fifth conductive layer residue 352 may remain on the initial dummy gate mask 202 on a portion of the second region II of the substrate 100 .

[0215] Reference Fig.58 The initial dummy gate mask 202 and the initial dummy gate electrode 192 may be patterned by an etching process to form a dummy gate mask 205 and a dummy gate electrode 194, respectively. The dummy gate mask 205 and the dummy gate electrode 194 may together form a dummy gate structure.

[0216] During the etching process, an upper portion of the third isolation pattern 136 , the fifth conductive layer 350 , the first barrier layer 340 , the third conductive layer 193 , the buffer layer 160 , and the first etch stop layer 170 on a portion of the second region II adjacent to the first region I of the substrate 100 may also be removed.

[0217] Reference Fig.59 , executable and reference Figures 16 to 22 The process shown is substantially the same as or similar to the process shown in the figure to form the first spacer 210 and the second spacer 215, the source / drain layer 220 and the first insulating interlayer 230, and can be performed with reference to Fig.29 and Fig.30 The process shown is substantially the same or similar to the process for forming the second gate structure 320 .

[0218] However, the high-k dielectric pattern 300 included in the second gate structure 320 may also be formed on an upper surface of the first insulating interlayer 230 , upper sidewalls and upper surfaces of the first spacer 210 , and an upper surface of the second capping layer 360 .

[0219] Reference Fig.60 , portions of the high-k dielectric pattern 300 on the upper surface of the first insulating interlayer 230, the upper sidewall and upper surface of the first spacer 210, and the upper surface of the second covering layer 360 can be removed by, for example, a wet etching process, and a fourth etch stop layer 710 and a third covering layer 370 can be sequentially stacked on the second gate structure 320, the first insulating interlayer 230, the first spacer 210, and the second covering layer 360, and a planarization process can be performed on the third covering layer.

[0220] Refer again Fig.54 , executable and reference Figures 34 to 47 and Figures 1 to 4 The processes shown are basically the same or similar processes for manufacturing semiconductor devices.

[0221] As mentioned above, with reference Figures 1 to 47 The method or reference shown Figures 48 to 53Different from the method shown, a dummy gate mask layer and a dummy gate electrode layer can be formed on the first region I and the second region II of the substrate 100, a third conductive layer 193, a bit line contact plug 265, a first barrier layer 340, a fifth conductive layer 350 and a second covering layer 360 can be formed on the first region I of the substrate 100, and a dummy gate structure can be formed on the second region II of the substrate 100.

[0222] Figure 61 to Figure 63 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0223] The method may include referring to Figures 54 to 60 , Figures 48 to 53 or Figures 1 to 47 Those processes shown are substantially the same or similar processes, and thus repeated explanations thereof are omitted here.

[0224] Reference Fig.61 , executable and reference Fig.49 The illustrated process is substantially the same or similar to the process to form the first active pattern 101 and the isolation structure 130 , and the first gate structure 150 may be formed through upper portions of the first active pattern 101 and the first isolation pattern 132 in the first region I of the substrate 100 .

[0225] The buffer layer 160, the first etch stop layer 170, and the third insulating layer 720 may be formed on portions of the first and second regions I and II of the substrate 100 adjacent to the first region I of the substrate 100. The third insulating layer 720 may include oxide (eg, silicon oxide).

[0226] Reference Fig.62 , a second active pattern 105 may be formed on the second region II of the substrate 100 , and a sixth groove 700 may also be formed.

[0227] Reference Fig.63 A fifth insulating interlayer may be formed on the isolation structure 130, the second active pattern 105, and the third insulating layer 720 to fill the sixth groove 700, and a planarization process may be performed on the fifth insulating interlayer until an upper surface of the first etch stop layer 170 is exposed to form a fifth insulating interlayer pattern 115.

[0228] During the planarization process, the third insulating layer 720 may be removed.

[0229] A wet etching process may be performed on an upper portion of the fifth insulation interlayer pattern 115 until an upper portion of the second active pattern 105 is exposed.

[0230] A plasma oxidation process may be performed to form an oxide pattern 129 on an upper surface and a sidewall of an upper portion of the second active pattern 105 .

[0231] Reference Fig.54 , executable and reference Figures 14 to 47 and Figures 1 to 4 The processes shown are basically the same or similar processes for manufacturing semiconductor devices.

[0232] As described above, the first active pattern 101 may be formed on the first region I of the substrate 100 , the first gate structure 150 may be formed, and the second active pattern 105 may be formed on the second region II of the substrate 100 .

[0233] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept.

Claims

1. A semiconductor device comprising: A first active pattern and a second active pattern are respectively on a cell region and a peripheral circuit region of the substrate; a first gate structure extending through an upper portion of the first active pattern; a second gate structure on an upper surface and an upper sidewall of the second active pattern; a source / drain layer on a portion of the second active pattern adjacent to the second gate structure; a bit line structure, on a central portion of the first active pattern, the bit line structure overlapping the second gate structure in a horizontal direction parallel to an upper surface of the substrate; a contact plug structure on an end portion opposite to the first active pattern; as well as Capacitor, on the contact plug structure.

2. The semiconductor device according to claim 1, further comprising: an isolation structure on the substrate and on sidewalls of the first active pattern and the second active pattern, The isolation structure includes a first isolation pattern, a second isolation pattern and a third isolation pattern, and The first gate structure extends through an upper portion of the isolation structure, and the second gate structure is on the isolation structure.

3. The semiconductor device according to claim 2, wherein: A first portion of the isolation structure on the cell region of the substrate includes a first isolation pattern, and The second portion of the isolation structure on the peripheral circuit region of the substrate includes first to third isolation patterns.

4. The semiconductor device according to claim 3, wherein: An upper surface of a portion of the first isolation pattern on the cell region of the substrate is coplanar with an uppermost surface of the first active pattern.

5. The semiconductor device according to claim 3, wherein: The second active pattern extends in a first direction parallel to the upper surface of the substrate, and the second gate structure extends in a second direction parallel to the upper surface of the substrate and intersecting the first direction, and Wherein, when the lower surface of the substrate provides a base reference plane, an upper surface of a third portion of the isolation structure on the peripheral circuit region of the substrate and adjacent to the second active pattern in the second direction is lower than an upper surface of the second active pattern.

6. The semiconductor device according to claim 5, wherein: The uppermost surface of a portion of the second isolation pattern on the peripheral circuit region of the substrate and adjacent to the source / drain layer in the second direction is higher than the uppermost surfaces of portions of the first isolation pattern and the third isolation pattern on the peripheral circuit region of the substrate and adjacent to the source / drain layer in the second direction.

7. The semiconductor device according to claim 6, wherein: An uppermost surface of the portion of the second isolation pattern is coplanar with an upper surface of the second active pattern.

8. The semiconductor device according to claim 2, further comprising: The insulating intermediate layer pattern is between the isolation structure and the second gate structure.

9. The semiconductor device according to claim 8, further comprising: A spacer is on the insulating interlayer pattern, wherein the spacer is on a sidewall of the second gate structure.

10. The semiconductor device according to claim 1, wherein The first gate structure extends in a first direction parallel to the upper surface of the substrate, The bit line structure extends in a second direction, the second direction is parallel to the upper surface of the substrate and intersects with the first direction, wherein the bit line structure extends on the cell region of the substrate and on a portion of the peripheral circuit region of the substrate adjacent to the cell region of the substrate, and The bit line structure includes a first conductive pattern, a blocking pattern, a second conductive pattern and a covering pattern stacked in a vertical direction perpendicular to an upper surface of the substrate.

11. The semiconductor device according to claim 10, wherein The barrier pattern is on a side wall of an end portion of the second conductive pattern in the second direction, Wherein, the end portion of the second conductive pattern is on a peripheral circuit region of the substrate.

12. The semiconductor device according to claim 10, wherein: The cross section of the blocking pattern on the peripheral circuit region of the substrate in the second direction is “L” shaped.

13. The semiconductor device according to claim 10, wherein: A sidewall of an end portion of the first conductive pattern in the second direction is not aligned with a sidewall of an end portion of the barrier pattern in the second direction in a vertical direction, so that the barrier pattern and the first conductive pattern have a stepped profile in the second direction together, and The end portion of the first conductive pattern and the end portion of the barrier pattern are on a peripheral circuit region of the substrate.

14. The semiconductor device according to claim 10, wherein: A side wall of an end portion of the first conductive pattern in the second direction is vertically aligned with a side wall of an end portion of the barrier pattern in the second direction, The end portion of the first conductive pattern and the end portion of the barrier pattern are on a peripheral circuit region of the substrate.

15. A semiconductor device comprising: a first active pattern on a substrate; a first gate structure extending through an upper portion of the first active pattern in a first direction parallel to an upper surface of the substrate; a bit line structure, on a central portion of the first active pattern, the bit line structure extending in a second direction parallel to an upper surface of the substrate and intersecting the first direction, wherein the bit line structure includes a first conductive pattern, a blocking pattern, a second conductive pattern, and a capping pattern stacked in a vertical direction perpendicular to the upper surface of the substrate; a contact plug structure on an end portion of the first active pattern facing away from the first active pattern; and Capacitor, on the contact plug structure, Wherein, an end portion of the barrier pattern in the second direction has an “L” shape in a cross-sectional view.

16. The semiconductor device according to claim 15, wherein: The barrier pattern is on a sidewall of an end portion of the second conductive pattern in the second direction.

17. The semiconductor device according to claim 15, wherein: A sidewall of an end portion of the first conductive pattern in the second direction is not vertically aligned with a sidewall of an end portion of the barrier pattern in the second direction, so that the barrier pattern and the first conductive pattern have a stepped profile in the second direction.

18. A semiconductor device comprising: A first active pattern and a second active pattern are respectively on a cell region and a peripheral circuit region of the substrate; an isolation structure on the substrate and on sidewalls of the first active pattern and the second active pattern, the isolation structure comprising a first isolation pattern, a second isolation pattern and a third isolation pattern; a first gate structure extending through an upper portion of the first active pattern and the isolation structure in a first direction parallel to an upper surface of the substrate on a cell region of the substrate; a second gate structure on an upper surface and an upper sidewall of the second active pattern, wherein the second gate structure is on the isolation structure and on a peripheral circuit region of the substrate; a source / drain layer on a portion of the second active pattern adjacent to the second gate structure; a bit line structure on a central portion of the first active pattern and on the isolation structure, the bit line structure extending in a second direction parallel to an upper surface of the substrate and intersecting the first direction, wherein the bit line structure is on a cell region and on a portion of a peripheral circuit region adjacent to the cell region, and wherein the bit line structure includes a first conductive pattern, a blocking pattern, a second conductive pattern, and a capping pattern stacked in a vertical direction perpendicular to an upper surface of the substrate; a contact plug structure on an end portion of the first active pattern facing away from the first active pattern; and Capacitor, on the contact plug structure.

19. The semiconductor device according to claim 18, wherein: The barrier pattern is on a side wall of an end portion of the second conductive pattern in the second direction, Wherein, the end portion of the second conductive pattern is on a peripheral circuit region of the substrate.

20. The semiconductor device according to claim 18, wherein A sidewall of an end portion of the first conductive pattern in the second direction is not aligned with a sidewall of an end portion of the barrier pattern in the second direction in a vertical direction, so that the barrier pattern and the first conductive pattern have a stepped profile in the second direction together, and The end portion of the first conductive pattern and the end portion of the barrier pattern are on a peripheral circuit region of the substrate.

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