Inorganic salt framework layer and preparation method thereof, and preparation method of perovskite device

Abstract

The invention relates to the technical field of perovskite devices, and particularly provides an inorganic salt framework layer and a preparation method thereof, and a preparation method of a perovskite device. The objective of the invention is to solve the problem that unreacted lead iodide is easy to remain on the bottom layer of an existing perovskite thin film, so that the stability of a perovskite device is affected. Therefore, the preparation method of the inorganic salt framework layer comprises the following steps: forming a bottom-buried interface layer on the surface of a base material; forming an inorganic salt frame layer on the surface of the bottom-buried interface layer, and then performing pre-annealing treatment to obtain an inorganic salt frame layer with a plurality of permeation channels; wherein the buried interface layer can expand when the temperature is higher than the room temperature, so that a plurality of permeation channels can be generated in the inorganic salt framework layer in the pre-annealing treatment process. The inorganic salt frame layer prepared by the preparation method provided by the invention has a permeation channel, which is beneficial to smooth downward permeation of the organic salt and full reaction with the inorganic salt, and the stability of the perovskite device is effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of perovskite devices, and specifically provides an inorganic salt framework layer and a preparation method thereof, and a preparation method of a perovskite device. Background Art

[0002] Perovskite solar cells are a highly efficient third-generation photovoltaic cell technology. Compared with crystalline silicon bottom cells, they have attracted widespread attention due to their higher theoretical efficiency limit and lower production cost.

[0003] The two-step solution method is a commonly used preparation method for high-efficiency batteries. However, the problem of incomplete reaction between the second-step organic salt solution and the first-step inorganic lead halide framework often occurs, resulting in the presence of excessive lead halide at the buried interface, which accelerates the attenuation of device performance and seriously affects the stability of perovskite devices.

[0004] Accordingly, this field requires a new technical solution to solve the above technical problems. Summary of the invention

[0005] The present application aims to solve the above-mentioned technical problem, that is, to solve the problem that unreacted lead iodide is easily left in the bottom layer of the existing perovskite film, thereby affecting the stability of the perovskite device.

[0006] In a first aspect, the present application provides a method for preparing an inorganic salt framework layer, the preparation method comprising the following steps: forming a buried interface layer on the surface of a substrate; forming an inorganic salt framework layer on the surface of the buried interface layer, and then performing a pre-annealing treatment to obtain an inorganic salt framework layer having a plurality of permeation channels; wherein the buried interface layer can expand at a temperature higher than room temperature, thereby enabling the generation of a plurality of permeation channels in the inorganic salt framework layer during the pre-annealing treatment.

[0007] In the preferred technical solution of the method for preparing the inorganic salt framework layer, the material of the buried interface layer is not easily soluble in polar solvents and can expand at a temperature higher than room temperature.

[0008] In the preferred technical solution of the above-mentioned method for preparing the inorganic salt framework layer, the material of the buried interface layer includes at least one of high molecular weight ionic liquids, thioalkanes, halogenated alkanes, thioolefins, halogenated olefins, and long alkyl chain aromatic polymers.

[0009] In the preferred technical solution of the above-mentioned method for preparing the inorganic salt framework layer, the material of the buried interface layer includes at least one of 3,5-divinylbenzyl ammonium sulfide, polyethyleneimine, polyacrylamide, polyphenylene sulfide or poly(1,4-phenylene ether-sulfide).

[0010] In the preferred technical solution of the above-mentioned method for preparing the inorganic salt framework layer, the thickness of the buried interface layer is 1 nm to 20 nm.

[0011] In the preferred technical solution of the above-mentioned method for preparing the inorganic salt framework layer, the buried interface layer is prepared by any one of spin coating, scraper coating, slit coating, immersion, pulling or spraying.

[0012] In the preferred technical solution of the method for preparing the inorganic salt framework layer, in the process of preparing the buried interface layer, the buried interface layer is prepared by spin coating, and the spin coating temperature is 58°C to 63°C.

[0013] In the preferred technical solution of the method for preparing the inorganic salt framework layer, the pre-annealing temperature of the pre-annealing treatment is 95° C. to 105° C.; and / or the treatment time of the pre-annealing treatment is 1 min to 2 min.

[0014] In a second aspect, the present application provides an inorganic salt framework layer having a plurality of permeation channels therein, wherein the permeation channels facilitate the penetration of organic salts into the inorganic salt framework layer during the preparation of the perovskite film.

[0015] In a third aspect, the present application provides a method for preparing a perovskite device, the preparation method comprising the following steps: preparing a substrate; preparing an inorganic salt framework layer on the surface of the substrate by the above-mentioned method for preparing an inorganic salt framework layer; forming an organic salt layer on the surface of the inorganic salt framework layer, and then annealing to obtain a perovskite film; and sequentially preparing an electron transport layer, a buffer layer and an electrode layer on the surface of the perovskite film.

[0016] In the preferred technical solution of the above-mentioned method for preparing the perovskite device, the annealing temperature of the annealing treatment is 130° C. to 150° C., and the annealing time is 10 min to 30 min.

[0017] Compared with the prior art, this application has the following technical effects:

[0018] The preparation method of the inorganic salt framework layer of the present application first forms a buried interface layer that can expand when the temperature is higher than room temperature on the surface of the substrate, and then prepares the inorganic salt framework layer on the surface of the buried interface layer. After the inorganic salt framework layer is formed, a pre-annealing treatment is performed to make the buried interface layer expand again, thereby generating a number of permeation channels in the inorganic salt framework layer. The permeation channels help the organic salt to penetrate downward into the inorganic salt framework layer, thereby allowing the inorganic salt in the inorganic salt framework layer and at the bottom to fully react with the organic salt, so that the lead iodide reacts thoroughly and without residue, effectively slowing down the attenuation rate of the perovskite device and improving the stability of the perovskite device.

[0019] In addition, during the perovskite annealing stage, the buried interface layer continues to expand, thereby keeping the permeation channel stable and reducing the impact of steric hindrance on the perovskite grain size, allowing the perovskite to grow smoothly. After the perovskite annealing is completed and restored to room temperature, the buried interface layer is cooled to provide compressive stress, thereby coordinating and neutralizing the stress differences of different phases in the mixed-phase 3D perovskite, further improving the stability of the perovskite device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, in which:

[0021] Figure 1 It is a flow chart of the method for preparing the inorganic salt framework layer of the present application;

[0022] Figure 2 is a flow chart of a method for preparing a perovskite device of the present application;

[0023] Figure 3 It is a schematic structural diagram of an embodiment of the perovskite device of the present application.

[0024] List of reference numerals:

[0025] 1. Substrate; 101. Single crystal silicon substrate; 102. a-Si:H passivation layer; 103. Full-area electron transport layer on the front side; 104. ITO transparent electrode; 105. Silver electrode; 106. Full-area hole transport layer on the back side; 107. IZO composite layer; 108. Me-4PACz hole transport layer;

[0026] 2. Buried interface layer; 3. Perovskite film; 4. C 60 Electron transport layer; 5. SnO 2 Buffer layer; 6. IZO transparent electrode; 7. Silver electrode; 8. Full-area MgFx anti-reflection layer. DETAILED DESCRIPTION

[0027] The preferred embodiments of the present application are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the protection scope of the present application.

[0028] In this application, the term "and / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0029] In this application, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, c can be single or multiple, respectively.

[0030] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution, some or all of the steps can be executed in parallel or sequentially, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0031] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0032] The weight of the relevant components mentioned in the embodiment description of the present application can not only refer to the specific content of each component, but also represent the proportional relationship between the weights of the components. Therefore, as long as the content of the relevant components is proportionally enlarged or reduced according to the embodiment description of the present application, it is within the scope disclosed in the embodiment description of the present application. Specifically, the mass described in the embodiment description of the present application can be a mass unit known in the chemical industry such as μg, mg, g, kg, etc.

[0033] In the present application, the terms "first", "second", "third", etc. in "the first aspect", "the second aspect", "the third aspect", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or quantity, nor can they be understood as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first", "second", "third", etc. only serve the purpose of non-exhaustive enumeration and description, and it should be understood that they do not constitute a closed limitation on quantity.

[0034] The experimental methods in the following examples are conventional methods unless otherwise specified, and the materials, reagents, etc. used in the following examples are commercially available unless otherwise specified.

[0035] Based on the problem pointed out in the background technology that unreacted lead iodide is easily left in the bottom layer of the existing perovskite film, which in turn affects the stability of the perovskite device.

[0036] The preparation method of the inorganic salt framework layer of the present application is to first form a buried interface layer on the surface of a substrate that can expand when the temperature is higher than room temperature, then prepare an inorganic salt framework layer on the surface of the buried interface layer, and perform a pre-annealing treatment after the inorganic salt framework layer is formed, so that the buried interface layer expands again, thereby generating a number of permeation channels in the inorganic salt framework layer, and the permeation channels help the organic salt to penetrate downward into the inorganic salt framework layer, so that the inorganic salt in the inorganic salt framework layer and at the bottom thereof fully reacts with the organic salt, so that the lead iodide reacts thoroughly and without residue, effectively slowing down the attenuation rate of the perovskite device and improving the stability of the perovskite device.

[0037] Specifically, in the first aspect, see Figure 1 The present application provides a method for preparing an inorganic salt framework layer, the preparation method comprising the following steps:

[0038] S1: forming a buried interface layer on the surface of the substrate.

[0039] S2: forming an inorganic salt framework layer on the surface of the buried interface layer, and then performing a pre-annealing treatment to obtain an inorganic salt framework layer having a plurality of permeation channels.

[0040] The buried interface layer can expand when the temperature is higher than room temperature, so that a number of permeation channels can be generated in the inorganic salt framework layer during the pre-annealing process.

[0041] The method for preparing the inorganic salt framework layer of the present application forms a buried interface layer on the surface of the substrate before preparing the inorganic salt framework layer on the substrate, and the buried interface layer is configured to expand when the temperature is higher than room temperature, and then forms an inorganic salt framework layer on the surface of the buried interface layer, and performs a pre-annealing treatment. During the pre-annealing treatment, the buried interface layer expands again, so that the inorganic salt framework layer generates a plurality of permeation channels under the tensile stress of the expansion of the buried interface layer, thereby obtaining an inorganic salt framework layer with a plurality of permeation channels. The permeation channel helps the subsequent organic salt to penetrate downward into the inorganic salt framework layer, so that the inorganic salt inside the inorganic salt framework layer and at the bottom thereof can fully react with the organic salt, so that the lead iodide reacts thoroughly and without residue, effectively slowing down the attenuation rate of the obtained perovskite device and improving the stability of the perovskite device.

[0042] It should be noted that the room temperature is a temperature within the temperature range of room temperature known in the art, and in the present application, the room temperature is 25°C.

[0043] In addition, during the perovskite annealing stage, the buried interface layer will continue to expand, thereby maintaining the stability of several permeation channels within the inorganic salt framework layer, and reducing the effect of steric hindrance on the size of perovskite grains during the reaction of organic salts and inorganic salts to form perovskite grains, thereby enabling the perovskite to grow smoothly and ensuring the size of the perovskite grains. After the perovskite annealing is completed and restored to room temperature, the buried interface layer shrinks after cooling to provide compressive stress, thereby coordinating and neutralizing the stress differences between different phases in the mixed phase 3D perovskite, further improving the stability of the perovskite device.

[0044] Preferably, the material of the buried interface layer is not easily soluble in polar solvents and can swell at a temperature higher than room temperature.

[0045] Making the material of the buried interface layer insoluble in polar solvents can prevent the buried interface layer from being dissolved during the subsequent preparation of the perovskite film, so that the buried interface layer can always maintain its shape. In addition, the material of the buried interface layer can expand at temperatures above room temperature, and can expand during the pre-annealing treatment and the perovskite annealing treatment, thereby generating a permeation channel in the inorganic salt framework layer to facilitate the penetration of organic salts and sufficient reaction with inorganic salts, thereby effectively improving the performance of the perovskite device.

[0046] In some embodiments, the material of the buried interface layer includes at least one of a high molecular weight ionic liquid (e.g., 3,5-divinylbenzyl ammonium sulfide, polyethyleneimine (PEI)), a thioalkane, a halogenated alkane, a thioolefin, a halogenated olefin, and a long alkyl chain aromatic polymer (e.g., polyphenylene sulfide).

[0047] In some embodiments, the material of the buried interface layer includes at least one of 3,5-divinylbenzyl ammonium sulfide, polyethyleneimine (PEI), polyacrylamide (PAM), polyphenylene sulfide, or poly(1,4-phenylene ether-sulfide).

[0048] In some embodiments, the buried interface layer has a thickness of 1 nm to 20 nm.

[0049] Controlling the thickness of the buried interface layer between 1nm and 20nm can effectively control the tensile force after the buried interface layer expands, thereby effectively regulating the number and size of the permeation channels in the organic salt estimation layer, so that the permeation channels can be evenly distributed. It should be noted that when the material of the buried interface layer is different, the optimal thickness of the buried interface layer corresponding to it is also different. Controlling the thickness of the buried interface layer within the range of 20nm is more universal for conventional optional buried interface layer materials and has a better effect.

[0050] In some embodiments, the buried interface layer is prepared by any one of spin coating, blade coating, slit coating, immersion, Czochralski or spray coating.

[0051] In some embodiments, in step S1, the buried interface layer is prepared by spin coating, and the spin coating temperature is 58°C to 63°C. When spin coating the buried interface layer, the spin coating temperature is controlled at 58°C to 63°C to avoid the spin coating temperature being too high or too low, so that during the spin coating of the buried interface layer, the material of the buried interface layer is in a pre-expansion state, so that after the annealing treatment is completed and the room temperature is restored, the buried interface layer shrinks and provides compressive stress, which helps to coordinate and neutralize the stress difference between different phases in the mixed phase 3D perovskite and improve the performance of the perovskite. The preferred spin coating temperature is 60°C.

[0052] In some embodiments, the pre-annealing temperature of the pre-annealing process is 95° C. to 105° C.

[0053] During the pre-annealing process, the pre-annealing temperature is controlled to 95°C to 105°C to avoid the temperature being too high or too low during the pre-annealing process, which can effectively control the expansion rate of the buried interface layer and prevent the buried interface layer from expanding too much in an instant, thereby regulating the quality of the permeation channel of the inorganic salt framework layer and preventing the permeation channel from being too large and unevenly distributed. The preferred pre-annealing temperature is 100°C.

[0054] In some embodiments, the pre-annealing treatment takes 1 to 2 minutes.

[0055] During the pre-annealing process, the pre-annealing time is controlled within 1 to 2 minutes to remove the residual solvent in the inorganic salt framework layer, and the number and quality of the permeation channels in the inorganic salt framework layer can be regulated to obtain permeation channels with uniform distribution and reasonable size.

[0056] In a second aspect, the present application provides an inorganic salt framework layer having a plurality of permeation channels therein, which facilitate the penetration of organic salts into the inorganic salt framework layer during the preparation of the perovskite film, so that the inorganic salts in the inorganic salt framework layer can fully react with the organic salts.

[0057] On the third side, see Figure 2 The present application provides a method for preparing a perovskite device, comprising the following steps:

[0058] S100: preparing a substrate.

[0059] S210: forming a buried interface layer on the surface of the substrate.

[0060] S220: forming an inorganic salt framework layer on the surface of the buried interface layer, and then performing a pre-annealing treatment to obtain an inorganic salt framework layer having a plurality of permeation channels.

[0061] S300: forming an organic salt layer on the surface of the inorganic salt framework layer, and then performing annealing treatment to obtain a perovskite film.

[0062] S400: Preparing an electron transport layer on the surface of the perovskite film.

[0063] S500: preparing a buffer layer on the surface of the electron transport layer.

[0064] S600: preparing an electrode layer on the surface of the buffer layer.

[0065] It should be noted that the perovskite device of the present application can be a perovskite cell or a perovskite / crystalline silicon stacked solar cell.

[0066] In some embodiments, in step S300 , the annealing temperature of the annealing treatment is 130° C. to 150° C., and the annealing time is 10 min to 30 min.

[0067] During the annealing process, the annealing temperature is controlled at 130°C to 150°C, and the annealing time is controlled at 10min to 30min, so that the buried interface layer maintains a stable expansion state, thereby forming sufficient channels or gaps required for the growth of perovskite crystal nuclei in the inorganic salt framework layer, providing sufficient growth space for the perovskite crystal nuclei, facilitating the growth of perovskite grains, ensuring the size of perovskite grains, and thus improving the performance of perovskite batteries.

[0068] The performance of the inorganic salt framework layer of the present application is described in detail below through several specific examples of perovskite devices. The perovskite device in the example has a structure such as Figure 3 The perovskite / crystalline silicon tandem solar cell shown, wherein steps (1) to (8) are specific execution steps of step S100 of the method for preparing the perovskite cell provided in the third aspect.

[0069] Example 1

[0070] The perovskite / crystalline silicon tandem solar cell of this embodiment is prepared by the following steps:

[0071] (1) Select n-type single crystal silicon and perform RCA standard cleaning process. 3 , H 2 O 2 A porous structure was prepared on the surface of the silicon substrate by metal-assisted chemical etching in a mixed solution of HNO 3 Cleaning.

[0072] (2) The porous silicon was heated to 5℃~10℃ in HF / HNO 3=1:3 (vol) mixed solution to remove the surface porous silicon, put it into 70℃~90℃ NaOH for etching to obtain a single crystal silicon substrate 101 with an angle of 60° between the top inverted pyramid and the silicon surface and a depth of 1μm, and an angle of 25° between the bottom inverted pyramid and the silicon surface and a depth of 1μm.

[0073] (3) A PECVD process is used to deposit an a-Si:H passivation layer 102 on the front and back sides of the single crystal silicon substrate 101 with a thickness of about 5 nm and a deposition temperature of 200°C.

[0074] (4) A boron-doped a-Si:H layer (12 nm) is deposited on the front side using a PECVD process at a deposition temperature of 200° C. to form a full-area hole transport layer 106 on the back side.

[0075] (5) A phosphorus-doped a-Si:H layer (6 nm) is deposited on the back side by using a PECVD process at a deposition temperature of 200° C. to form a full-area electron transport layer 103 on the front side.

[0076] (6) An ITO transparent electrode 104 (110 nm) with a square resistance of about 120 Ω / sq is deposited on the back by magnetron sputtering; then a gate line silver electrode 105 is deposited at low temperature.

[0077] (7) An IZO composite layer 107 with a thickness of 15 nm is deposited on the front side by magnetron sputtering.

[0078] (8) The Me-4PACz hole transport layer 108 is prepared by spin coating with a thickness of 1 nm.

[0079] (9) Spin coating 3,5-divinylbenzyl ammonium sulfide on the hole transport layer 108 using isopropyl alcohol as solvent, with a thickness of 10 nm and a spin coating temperature of 60° C. to obtain a buried interface layer 2.

[0080] (10) An inorganic salt solution is spin-coated on the buried interface layer 2 by a spin coating method. The inorganic salt solution is prepared by dissolving metal halides PbI2 and CsI in N,N-dimethylformamide (DMF) and stirring for 12 hours. The solution is pre-annealed at 100° C. for 1 minute to obtain an inorganic salt framework layer. The spin coating thickness is 500 nm.

[0081] (11) The wide bandgap perovskite light absorbing layer (Cs 0.05 MA 0.15 FA 0.8 PbI 2.25 Br 0.75 ), the annealing temperature is 150°C, the band gap is about 1.68eV, the thickness is 800nm, and the perovskite film 3 is obtained.

[0082] (12) Thermal evaporation was used to prepare C on perovskite film 3 60 The electron transport layer 4 has a thickness of 20 nm.

[0083] (13) Preparation of SnO by ALD 2 The buffer layer 5 has a thickness of 20 nm.

[0084] (14) Magnetron sputtering was used to deposit SnO 2 An IZO transparent electrode 6 is deposited on the buffer layer with a thickness of 100 nm.

[0085] (15) Thermal evaporation is used to prepare a silver electrode 7 with a thickness of 400 nm through a mask. At the same time, thermal evaporation is used to prepare a full-area MgFx anti-reflection layer 8 with a thickness of 100 nm.

[0086] Example 2

[0087] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of Embodiment 1, and the only difference from Embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 1 nm.

[0088] Example 3

[0089] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of Embodiment 1. The only difference between this embodiment and Embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 2 nm.

[0090] Example 4

[0091] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 5 nm.

[0092] Example 5

[0093] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 15 nm.

[0094] Example 6

[0095] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 20 nm.

[0096] Example 7

[0097] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 25 nm.

[0098] Example 8

[0099] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the spin coating thickness of the buried interface layer 2 in step (9) is 30 nm.

[0100] Example 9

[0101] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of Embodiment 1. The only difference between this embodiment and Embodiment 1 is that the pre-annealing time in step (10) is 2 minutes.

[0102] Example 10

[0103] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the material of the buried interface layer 2 in step (9) is polyethyleneimine (PEI).

[0104] Embodiment 11

[0105] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the material of the buried interface layer 2 in step (9) is polyacrylamide (PAM).

[0106] Example 12

[0107] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this embodiment are the same as those of embodiment 1. The only difference between this embodiment and embodiment 1 is that the material of the buried interface layer 2 in step (9) is polyphenylene sulfate.

[0108] Comparative Example 1

[0109] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this comparative example are the same as those of Example 1. The only difference between this comparative example and Example 1 is that step (9) is not included, and step (10) is directly executed, that is, the inorganic salt framework layer is directly prepared on the hole transport layer 108.

[0110] Comparative Example 2

[0111] The preparation steps of the perovskite / crystalline silicon tandem solar cell of this comparative example are the same as those of Example 1. The only difference between this comparative example and Example 1 is that the pre-annealing time in step (10) is 30 seconds.

[0112] Comparative Example 3

[0113] The preparation steps of the perovskite / crystalline silicon stacked solar cell of this comparative example are the same as those of Example 1. The only difference between this comparative example and Example 1 is that the pre-annealing time in step (10) is 5 minutes.

[0114] Comparative Example 4

[0115] The preparation steps of the perovskite / crystalline silicon tandem solar cell of this comparative example are the same as those of Example 1. The only difference between this comparative example and Example 1 is that the spin coating temperature in step (9) is 80°C.

[0116] Comparative Example 5

[0117] The preparation steps of the perovskite / crystalline silicon tandem solar cell of this comparative example are the same as those of Example 1. The only difference between this comparative example and Example 1 is that the spin coating temperature in step (9) is 40°C.

[0118] The solar cells prepared in Examples 1 to 12 and Comparative Examples 1 to 5 were tested to detect their performance, and the test results are shown in Table 1. The test items include: Voc (open circuit voltage), FF (fill factor), PCE (photovoltaic conversion efficiency) and MPP retention rate (maximum power point tracking, 400 hours).

[0119] Table 1 Experimental data of embodiments and comparative examples project Voc(V) FF(%) PCE(%) MPP(%) Example 1 1.941 79.94 31.19 96％ Example 2 1.852 73.74 27.87 82％ Example 3 1.880 74.59 27.9 85％ Example 4 1.923 78.08 29.85 90％ Example 5 1.836 69.49 26.65 82％ Example 6 1.727 68.43 25.98 78％ Example 7 1.711 67.62 24.55 72％ Example 8 1.705 55.08 20.33 70％ Example 9 1.883 75.12 29.08 90％ Example 10 1.923 78.08 29.85 97％ Embodiment 11 1.944 79.28 31.13 95％ Example 12 1.930 79.92 30.97 93％ Comparative Example 1 1.825 71.37 27.35 80％ Comparative Example 2 1.899 72.84 27.82 79％ Comparative Example 3 1.750 72.59 26.12 77％ Comparative Example 4 1.894 74.92 28.51 72％ Comparative Example 5 1.884 73.25 28.41 75％

[0120] Compare and analyze the above experimental data:

[0121] 1. Comparing Examples 1 to 6 and Examples 9 to 12 with Comparative Example 1, the open circuit voltage, fill factor, photoelectric conversion efficiency and MPP retention rate of Examples 1 to 4 and Examples 9 to 12 are all higher than those of Comparative Example 1. It can be seen that the present application can improve the performance of perovskite film and solar cell by preparing a buried interface layer on the surface of the substrate that can expand at a temperature higher than room temperature before preparing the inorganic salt framework layer. And it can be seen from Examples 1 and Examples 10 to 12 that when the material of the buried interface layer is 3,5-divinylbenzyl ammonium sulfide, polyethyleneimine, polyacrylamide or polyphenylene alum, the performance of the solar cell can be effectively improved relative to Comparative Example 1. Therefore, as long as the material of the buried interface layer is not easily soluble in polar solvents and can expand at a temperature higher than room temperature, it can be used.

[0122] 2. Comparing Examples 1 to 8, when the material of the buried interface layer is 3,5-divinylbenzyl ammonium sulfide, when the thickness of the buried interface layer is in the range of 1nm to 10nm, as the thickness of the buried interface layer increases, the various performances of the solar cell are gradually improved, and when the thickness of the buried interface layer is in the range of 10nm to 20nm, as the thickness of the buried interface layer increases, the various performances of the solar cell gradually decrease. When the thickness of the buried interface layer is higher than 20nm, the performance of the solar cell is greatly reduced; it can be seen that the thickness of the buried interface layer is too thick, which will affect the performance of the solar cell, so the thickness of the buried interface layer needs to be controlled within a certain range. When the material of the buried interface layer is 3,5-divinylbenzyl ammonium sulfide, it is preferred to control the thickness of the buried interface layer to 1nm to 10nm; when the material of the buried interface layer is other materials, the thickness of the buried interface layer can be adjusted according to actual needs.

[0123] 3. Comparing Example 1, Example 9, Comparative Example 2 and Comparative Example 3, the open circuit voltage, filling factor, photoelectric conversion efficiency and MPP retention rate of Example 1 are all higher than those of Example 9, Comparative Example 2 and Comparative Example 3. The filling factor, photoelectric conversion efficiency and MPP retention rate of Example 9 are all higher than those of Comparative Example 2 and Comparative Example 3. The open circuit voltage, filling factor, photoelectric conversion efficiency and MPP retention rate of Comparative Example 2 are all higher than those of Comparative Example 3. It can be seen that a pre-annealing time that is too long or too short will affect the performance of the solar cell. If the pre-annealing time is too short, the number of permeation channels of the inorganic salt skeleton layer is small during the pre-annealing stage, which is not conducive to the penetration of organic salts, thereby affecting the filling factor. If the pre-annealing time is too long, the buried interface layer will expand transitionally during the pre-annealing stage, affecting the continued expansion of the buried interface layer during the subsequent annealing treatment stage, affecting the growth of the 3D perovskite nucleus, and thus affecting the performance of the solar cell. Therefore, it is preferred to control the pre-annealing time to 1 min to 2 min.

[0124] 4. Comparing Example 1, Comparative Example 4 and Comparative Example 5, the open circuit voltage, fill factor, photoelectric conversion efficiency and MPP retention rate of Comparative Example 4 and Comparative Example 5 are all lower than those of Example 1. It can be seen that when the buried interface layer is spin-coated, the temperature that is too high or too low will affect the performance of the solar cell. Therefore, the spin coating temperature when spin coating the buried interface layer is controlled to be 58°C to 63°C, and the preferred spin coating temperature is 60°C. At this spin coating temperature, the material of the buried interface layer maintains a stable pre-expansion state, and a moderate number of uniformly distributed permeation channels are formed in the inorganic salt framework layer during the pre-annealing process, and the buried interface layer continues to expand during the annealing process to provide space for the smooth growth of the 3D perovskite nucleus, which is conducive to the growth of the perovskite grains and ensures the size of the perovskite grains. In addition, after the annealing treatment is accepted and cooled to room temperature, the buried interface layer shrinks and provides compressive stress, which helps to coordinate and neutralize the stress difference between different phases in the mixed phase 3D perovskite, thereby improving the performance of the perovskite.

[0125] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. A method for preparing an inorganic salt framework layer, characterized in that: The following steps are involved: forming a buried interface layer on the surface of the substrate; forming an inorganic salt framework layer on the surface of the buried interface layer, and then performing a pre-annealing treatment to obtain an inorganic salt framework layer having a plurality of permeation channels; The buried interface layer can expand when the temperature is higher than room temperature, so that a plurality of permeation channels can be generated in the inorganic salt framework layer during the pre-annealing treatment.

2. The method for preparing an inorganic salt framework layer according to claim 1, characterized in that: The material of the buried interface layer is not easily soluble in polar solvents and can swell at a temperature higher than room temperature.

3. The method for preparing the inorganic salt framework layer according to claim 2, characterized in that: The material of the buried interface layer includes at least one of high molecular weight ionic liquid, thioalkanes, halogenated alkanes, thioolefins, halogenated olefins, and long alkyl chain aromatic polymers.

4. The method for preparing an inorganic salt framework layer according to claim 1, characterized in that: The thickness of the buried interface layer is 1 nm to 20 nm.

5. The method for preparing an inorganic salt framework layer according to claim 1, characterized in that: The buried interface layer is prepared by any one of spin coating, scraping, slit coating, immersion, pulling or spraying.

6. The method for preparing an inorganic salt framework layer according to claim 1, characterized in that: In the process of preparing the buried interface layer, the buried interface layer is prepared by spin coating, and the spin coating temperature is 58° C. to 63° C.

7. The method for preparing an inorganic salt framework layer according to claim 1, characterized in that: The pre-annealing temperature of the pre-annealing treatment is 95°C to 105°C; And / or, the pre-annealing treatment has a treatment time of 1 min to 2 min.

8. An inorganic salt framework layer, characterized in that: The inorganic salt framework layer has a plurality of permeation channels inside, and the permeation channels facilitate the organic salt to permeate into the inorganic salt framework layer during the preparation of the perovskite film.

9. A method for preparing a perovskite device, characterized in that: The following steps are involved: preparing a substrate; The inorganic salt framework layer is prepared on the surface of the substrate by the method for preparing an inorganic salt framework layer according to any one of claims 1 to 7; forming an organic salt layer on the surface of the inorganic salt framework layer, and then performing annealing treatment to obtain a perovskite film; An electron transport layer, a buffer layer and an electrode layer are sequentially prepared on the surface of the perovskite film.

10. The method for preparing a perovskite device according to claim 9, characterized in that: The annealing temperature of the annealing treatment is 130° C. to 150° C., and the annealing time is 10 min to 30 min.

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