Implementation method of FPGA multichannel pulse compression based on MicroBlaze
Through the MicroBlaze-based FPGA, multi-channel pulse compression is achieved using DMA devices and AXIDMA IP cores, solving the complex circuit design and data transfer problems in the existing technology, and achieving efficient and integrated pulse compression processing, reducing hardware costs and Bandwidth pressure.
Patent Information
- Application Number
- CN202411362234.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2025-01-10
AI Technical Summary
In the prior art, multiple digital signal processing chips are often used to work together in the pulse compression process, resulting in complex circuit design, large space and high power consumption. Data transfer is required after multi-channel pulse pressure processing, increasing time overhead.
Using MicroBlaze-based FPGA, multi-channel pulse compression is realized through DMA devices and AXIDMA IP core, and data processing and storage are used using DDR storage and AXIDMA bus, eliminating the data transfer process.
Use one FPGA to complete the multi-channel pulse compression task of multi-chip DSP, reducing design costs, improving hardware integration, saving time overhead, reducing bandwidth pressure for subsequent signal processing, and having high bandwidth and high real-time performance.
Smart Images
Figure CN119291615A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of radar signal processing software design, and in particular to a method for implementing FPGA multi-channel pulse compression based on MicroBlaze. Background Art
[0002] In pulse Doppler radar, pulse compression technology is generally used to accumulate signal energy in order to improve the detection distance and distance resolution. During operation, the radar transmits a linear frequency modulation signal, receives the echo signal through multiple sub-arrays, and then obtains the digital signal through sampling. Signal processing requires pulse compression of the channel signals of multiple sub-arrays. The core of pulse compression technology is to transform the signal into the frequency domain, multiply it by a pulse compression function that matches the transmitted linear frequency modulation signal in the frequency domain, and transform the multiplication result into the time domain.
[0003] At present, in engineering, the pulse compression process is often implemented using digital signal processing chips (DSP), which has the following disadvantages:
[0004] (1) When performing operations on multiple sets of data, it is slower than an FPGA that can perform a large number of parallel operations simultaneously.
[0005] (2) Complex circuit design. Due to the limited performance of DSP, the pulse compression process requires multiple chips to work together to complete, resulting in complex circuit design, large space occupation, and is not conducive to the high integration design of hardware modules. In addition, due to the use of multiple chips, the overall power consumption is high and the hardware design cost is high.
[0006] (3) After multi-channel pulse compression processing, all channel data need to be moved together, which increases a lot of time overhead.
[0007] Therefore, an engineering implementation method of FPGA multi-channel pulse compression based on MicroBlaze is proposed. Summary of the invention
[0008] In order to solve the above problems, the present application provides a method comprising:
[0009] Step 1, initialize DMA device and interrupt, configure the DDR address where the front-end data is to be stored;
[0010] Step 2, wait for receiving interrupt;
[0011] Step 3: Receive interrupt response, receive a packet of front-end data, and store it in the configured DDR address;
[0012] Step 4: Configure the DDR address where the next packet of front-end data is to be stored;
[0013] Step 5: Configure the pulse compression IP core, including the number of channels;
[0014] Step 6, configure the AXIDMA IP core to read and write, the configuration content includes the number of channels and the stride of the preset storage interval; input a packet of front-end data stored in DDR into the pulse compression IP core through the AXIDMA IP core for processing, and store the processing result in DDR;
[0015] Step 7, wait for output interruption;
[0016] Step 8: Output interrupt response and output result;
[0017] Step 9. Go to step 2.
[0018] Preferably, the number of channels of the pulse compression IP core and the number of channels of the AXIDMA IP core are configured based on the front-end data frame header.
[0019] Preferably, the processing result storage is specifically as follows: the processing result of each packet is stored separately according to different channels, and the processing results of all packets in the same channel are stored together in order.
[0020] Preferably, configuring the pulse compression IP core also includes pulse compression points, pulse compression interception points, accumulation points, sampling rate and bandwidth.
[0021] Preferably, configuring the AXIDMA IP core to read and write also includes: read and write addresses, packet length and number of packets.
[0022] Preferably, the number of channels of the pulse compression IP core is the same as the number of channels of the AXIDMA IP core.
[0023] The advantages of the present application include: The present invention adopts an FPGA multi-channel pulse compression method based on MicroBlaze, which has the following advantages:
[0024] (1) Using one FPGA to complete the multi-channel pulse compression task of multiple DSPs can greatly reduce the DSP design cost and improve the hardware integration, which has good economic benefits and promotion value.
[0025] (2) According to the radar multi-channel multi-packet format data, a multi-channel pulse compression method based on FPGA is adopted, and the AXIDMA bus is used to store the sub-array data after pulse compression in DDR according to the channel. The single-channel one-frame data is stored sequentially, eliminating the data movement process and saving time.
[0026] It can be applied to scenarios such as digital front-end processing and radar raw data preprocessing, greatly compressing the data volume and effectively reducing the bandwidth pressure of subsequent signal processing. It has the processing advantages of high bandwidth and high real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1It is the signal preprocessing MicroBlaze program flow chart;
[0028] Figure 2 It is the pulse pressure module processing flow chart;
[0029] Figure 3 It is a schematic diagram of the storage of data after pulse pressure;
[0030] Figure 4 This is a schematic diagram of the AXIDMA framework. DETAILED DESCRIPTION
[0031] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present application will be further described in detail in detail and in detail in conjunction with the accompanying drawings. It can be understood that the specific embodiments described here are only partial embodiments of the present application, which are only used to explain the present application, not to limit the present application. It should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments in the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.
[0032] like Figure 1-Figure 4 As shown, in order to solve the above problems, the present application provides a method comprising:
[0033] Step 1, initialize DMA device and interrupt, attach interrupt and device to handle, configure DDR address where front-end data is to be stored;
[0034] Step 2, wait for receiving interrupt;
[0035] Step 3: Receive interrupt response, receive a packet of front-end data, and store it in the configured DDR address;
[0036] Step 4: Configure the DDR address where the next packet of front-end data is to be stored;
[0037] Step 5: Configure the pulse compression IP core, including the number of channels;
[0038] Step 6. Configure the AXIDMA IP core to read and write. The configuration content includes the number of channels and the stride of the preset storage interval; input a packet of front-end data stored in DDR into the pulse compression IP core through the AXIDMA IP core for processing, and store the processing results in DDR; configure the AXIDMA IP core to read and write and also include: read and write address, packet length, number of packets, number of channels, stride, and start. Stride = packet length x number of packets. For example, a frame of data contains 128 packets, the number of channels per packet is 16, and the number of pulse compression points is required to be 2048. Configure the pulse compression IP core: pulse compression points 2048, pulse compression interception points 2032, number of channels 16, accumulation points 128, sampling rate 4M, bandwidth 3.6M. Configure the AXIDMA IP core to read and write: read and write address, packet length 2048, number of packets 128, number of channels 16, stride is 262144, and start
[0039] Step 7, wait for output interruption;
[0040] Step 8: Output interrupt response and output result;
[0041] Step 9. Go to step 2.
[0042] Among them, Figure 2 As shown, the pulse compression module processing flow includes:
[0043] a) Generate the configuration of FFT and IFFT modules according to the number of pulse pressure points;
[0044] b) generating a matched filter time domain signal according to the configuration information, and after FFT processing, flowing to the pulse compression coefficient storage module, storing the pulse compression coefficient in the BRAM;
[0045] c) Fill the input with zeros according to the actual number of sampling points and pulse pressure points;
[0046] d) After the input data passes through FFT, it flows to the data coefficient synchronization module. After the data coefficient synchronization module reads out the data, it generates two synchronized AXIS for complex multiplication and then flows to the IFFT module;
[0047] e) Intercept data according to the configuration, generate the packet data end TLAST signal, and output the result.
[0048] In some optional implementations, the number of channels of the pulse compression IP core and the number of channels of the AXIDMA IP core are configured based on the front-end data frame header.
[0049] In some optional implementations, the processing result storage is specifically as follows: the processing result of each packet is stored separately according to different channels, and the processing results of all packets of the same channel are stored together in order. For example, after a frame (assuming 128 packets) of data is processed, the processing results of all packets of the same channel are stored together in order, and the data results can be directly called for subsequent processing, such as transposition.
[0050] In some optional implementations, configuring the pulse compression IP core also includes pulse compression points, pulse compression interception points, accumulation points, sampling rate, and bandwidth.
[0051] In some optional implementations, configuring the AXIDMA IP core to read and write also includes: read and write addresses, packet length, and number of packets.
[0052] In some optional implementations, the number of channels of the pulse compression IP core is the same as the number of channels of the AXIDMA IP core.
[0053] The advantages of the present application include: The present invention adopts an FPGA multi-channel pulse compression method based on MicroBlaze, which has the following advantages:
[0054] (1) Using one FPGA to complete the multi-channel pulse compression task of multiple DSPs can greatly reduce the DSP design cost and improve the hardware integration, which has good economic benefits and promotion value.
[0055] (2) According to the radar multi-channel multi-packet format data, a multi-channel pulse compression method based on FPGA is adopted, and the AXIDMA bus is used to store the sub-array data after pulse compression in DDR according to the channel. The single-channel one-frame data is stored sequentially, eliminating the data movement process and saving time.
[0056] It can be applied to scenarios such as digital front-end processing and radar raw data preprocessing, greatly compressing the data volume and effectively reducing the bandwidth pressure of subsequent signal processing. It has the processing advantages of high bandwidth and high real-time performance.
[0057] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A method for implementing FPGA multi-channel pulse compression based on MicroBlaze, characterized in that: include: Step 1, initialize DMA device and interrupt, configure the DDR address where the front-end data is to be stored; Step 2, wait for receiving interrupt; Step 3: Receive interrupt response, receive a packet of front-end data, and store it in the configured DDR address; Step 4: Configure the DDR address where the next packet of front-end data is to be stored; Step 5: Configure the pulse compression IP core, including the number of channels; Step 6, configure the AXIDMA IP core to read and write, the configuration content includes the number of channels and the stride of the preset storage interval; input a packet of front-end data stored in the DDR into the pulse compression IP core through the AXIDMA IP core for processing, and store the processing result in the DDR; Step 7, wait for output interruption; Step 8: Output interrupt response and output result; Step 9. Go to step 2.
2. The method for implementing FPGA multi-channel pulse compression based on MicroBlaze as claimed in claim 1, characterized in that: The number of channels of the pulse compression IP core and the number of channels of the AXIDMA IP core are configured based on the front-end data frame header.
3. The method for implementing FPGA multi-channel pulse compression based on MicroBlaze as claimed in claim 1, characterized in that: The processing result storage is specifically as follows: the processing result of each packet is stored separately according to different channels, and the processing results of all packets of the same channel are stored together in order.
4. The method for implementing FPGA multi-channel pulse compression based on MicroBlaze as claimed in claim 1, characterized in that: Configuring the pulse compression IP core also includes the number of pulse compression points, the number of pulse compression interception points, the number of accumulation points, the sampling rate, and the bandwidth.
5. The method for implementing FPGA multi-channel pulse compression based on MicroBlaze as claimed in claim 1, characterized in that: Configuring the AXIDMA IP core to read and write also includes: read and write address, packet length and number of packets.
6. The method for implementing FPGA multi-channel pulse compression based on MicroBlaze as claimed in claim 1, characterized in that: The number of channels of the pulse compression IP core is the same as that of the AXIDMA IP core.