A verification method for parallel queue scheduling circuit

Abstract

The present invention provides a verification method for a parallel queue scheduling circuit, the method comprising: generating a parallel queue task set corresponding to the parallel queue scheduling circuit according to a preset parallel queue design requirement, wherein the parallel queue task set includes a plurality of parallel queue tasks; performing hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set; running the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and comparing the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit. The present invention can generate a more comprehensive parallel queue task set, and perform a full coverage verification of the behavior of the parallel queue scheduling circuit according to these task sets, ensuring that the circuit can operate stably in various task scenarios, thereby improving the reliability and performance of the artificial intelligence chip.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence chips, and in particular to a verification method for a parallel queue scheduling circuit. Background Art

[0002] The parallel queue scheduling circuit is the core module for processing task scheduling in artificial intelligence chips and is widely used in high-performance computing chips such as neural network processors. This circuit is mainly responsible for distributing, scheduling and controlling the execution of various tasks in multiple parallel queues to ensure that task dependencies are correctly handled. However, due to the coexistence of parallel tasks between queues and dependencies within queues, the complexity of scheduling is greatly increased. Especially when the task dependencies are complicated and the parallel execution of tasks is intertwined with the sequential execution, scheduling errors are very likely to occur, affecting chip performance.

[0003] Existing verification methods usually verify based on a single queue and only test some typical parallel task scenarios. Although some common errors can be captured, in actual applications, due to the diversity and complexity of the scenarios, a single verification method is difficult to fully cover all parallel task scenarios, and verification blind spots are prone to occur, thereby increasing the risk of errors in the scheduling circuit. Especially when the dependencies, queue depths, and task combinations of complex tasks vary greatly, the existing verification system is difficult to ensure the comprehensiveness and accuracy of verification. Summary of the invention

[0004] The main purpose of the present invention is to solve the technical problem that the existing verification method usually performs verification based on a single queue and only tests some typical parallel task scenarios, which makes it difficult to ensure the comprehensiveness and accuracy of the verification;

[0005] A first aspect of the present invention provides a verification method for a parallel queue scheduling circuit, the verification method for the parallel queue scheduling circuit comprising:

[0006] According to the preset parallel queue design requirements, a parallel queue task set corresponding to the parallel queue scheduling circuit is generated, wherein the parallel queue task set includes multiple parallel queue tasks;

[0007] Performing hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set;

[0008] The parallel queue scheduling circuit is run according to the hardware excitation signal set to obtain a corresponding output result, and the output result is compared with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit.

[0009] Optionally, in a first implementation manner of the first aspect of the present invention, generating a parallel queue task set corresponding to the parallel queue scheduling circuit according to a preset parallel queue design requirement includes:

[0010] According to the number of queues and queue depth parameters in the parallel queue design requirements, initial task generation processing is performed on each queue to obtain an initial task set;

[0011] According to the initial task set and predefined dependency rules, dependency building processing is performed on tasks between different queues to obtain a task dependency set;

[0012] According to the initial task set and the task dependency set, adjacent tasks in each queue are subjected to non-dependency task insertion processing to obtain a parallel queue task set.

[0013] Optionally, in a second implementation of the first aspect of the present invention, the dependency building process is performed on tasks between different queues according to the initial task set and predefined dependency rules, and the task dependency set obtained includes:

[0014] Randomly generating first task dependencies between different tasks in the initial task set;

[0015] Filter the first task dependency according to the dependency rule to obtain a second task dependency;

[0016] All second task dependencies are integrated into a task dependency set.

[0017] Optionally, in a third implementation of the first aspect of the present invention, after integrating all second task dependencies into a task dependency set, the method further includes:

[0018] A circuit design attribute of the parallel queue scheduling circuit is obtained, and a second task dependency in the task dependency set is adjusted according to the circuit design attribute to obtain a new task dependency set.

[0019] Optionally, in a fourth implementation manner of the first aspect of the present invention, the filtering the first task dependency relationship according to the dependency relationship rule to obtain the second task dependency relationship includes:

[0020] Determine, according to the dependency rule, whether the first task dependency is a forward unidirectional task dependency or a front-to-back adjacent task dependency;

[0021] The first task dependency relationships that are not forward unidirectional task dependency relationships or front-to-back adjacent task dependency relationships are screened out to obtain the second task dependency relationships.

[0022] Optionally, in a fifth implementation of the first aspect of the present invention, the adjacent tasks in each queue are subjected to independent task insertion processing according to the initial task set and the task dependency set to obtain the parallel queue task set, including:

[0023] Randomly determine the positions to be inserted between adjacent tasks in the same queue in the initial task set;

[0024] Perform random task generation processing at each to-be-inserted position to obtain an insertion task set, wherein the number, type, parameters and format of the insertion tasks in the insertion task set are all randomly generated;

[0025] According to the inserted task set, the initial task set and the task dependency set, task integration processing is performed on each queue to obtain a parallel queue task set and standard results corresponding to each task in the parallel queue task set.

[0026] Optionally, in a sixth implementation manner of the first aspect of the present invention, running the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and comparing the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit includes:

[0027] Running the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and determining whether the output result corresponding to each task is the same as the corresponding standard result;

[0028] If they are the same, determining whether all circuit design problems of the parallel queue scheduling circuit have been eliminated according to the circuit design properties of the parallel queue scheduling circuit;

[0029] If all circuit design problems have not been eliminated, regenerate a parallel queue task set for verification until all circuit design problems of the parallel queue scheduling circuit are eliminated, and set the verification result as no problem with the parallel queue scheduling circuit;

[0030] If they are different, the verification result is set as a problem with the parallel queue scheduling circuit.

[0031] A second aspect of the present invention provides a verification device for a parallel queue scheduling circuit, the verification device for the parallel queue scheduling circuit comprising:

[0032] A queue task generation module, used to generate a parallel queue task set corresponding to the parallel queue scheduling circuit according to a preset parallel queue design requirement, wherein the parallel queue task set includes multiple parallel queue tasks;

[0033] An excitation generation module, used for performing hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set;

[0034] The data comparison module is used to run the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and compare the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit.

[0035] The third aspect of the present invention provides a verification device for a parallel queue scheduling circuit, comprising: a memory and at least one processor, wherein instructions are stored in the memory, and the memory and the at least one processor are interconnected via lines; the at least one processor calls the instructions in the memory so that the verification device of the parallel queue scheduling circuit executes the steps of the above-mentioned verification method for the parallel queue scheduling circuit.

[0036] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the steps of the above-mentioned verification method for the parallel queue scheduling circuit.

[0037] The verification method of the above-mentioned parallel queue scheduling circuit generates a parallel queue task set corresponding to the parallel queue scheduling circuit according to the preset parallel queue design requirements, wherein the parallel queue task set includes multiple parallel queue tasks; performs hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set; runs the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and compares the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit. The present invention can generate a more comprehensive parallel queue task set, and perform full coverage verification of the behavior of the parallel queue scheduling circuit based on these task sets, ensuring that the circuit can operate stably in various task scenarios, thereby improving the reliability and performance of the artificial intelligence chip.

[0038] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1It is a schematic diagram of a first embodiment of a verification method for a parallel queue scheduling circuit in an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of an embodiment of a verification device for a parallel queue scheduling circuit in an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of an embodiment of a verification device for a parallel queue scheduling circuit in an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of initial task generation of a verification method for a parallel queue scheduling circuit in an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of dependency task generation for a verification method for a parallel queue scheduling circuit in an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of independent task insertion generation of a verification method for a parallel queue scheduling circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device end including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or device ends.

[0048] To facilitate understanding of this embodiment, a verification method for a parallel queue scheduling circuit disclosed in an embodiment of the present invention is first described in detail, wherein the photovoltaic power generation device is integrated with a satellite receiving device. Figure 1 As shown, the method comprises the following steps:

[0049] 101. Generate a parallel queue task set corresponding to a parallel queue scheduling circuit according to a preset parallel queue design requirement, wherein the parallel queue task set includes multiple parallel queue tasks;

[0050] In one embodiment of the present invention, generating a parallel queue task set corresponding to the parallel queue scheduling circuit according to preset parallel queue design requirements includes: performing initial task generation processing on each queue according to the number of queues and queue depth parameters in the parallel queue design requirements to obtain an initial task set; performing dependency construction processing on tasks between different queues according to the initial task set and predefined dependency rules to obtain a task dependency set; performing non-dependency task insertion processing on adjacent tasks in each queue according to the initial task set and the task dependency set to obtain a parallel queue task set.

[0051] Specifically, first, in the process of obtaining the initial task set, the system performs initial task generation processing on each queue according to the number of queues and queue depth parameters in the parallel queue design requirements. The system reads the preset number of queues parameters to determine the number of parallel queues that need to be generated, and at the same time obtains the depth parameters of each queue to determine the number of tasks that need to be generated in each queue. For each queue, the system randomly generates a specified number of initial tasks. Each task contains a randomly generated task type, task parameters, and task format. These tasks are arranged in the queue in the order of generation. Through this processing process, the system finally obtains an initial task set containing multiple queues, each of which contains a predetermined number of randomly generated tasks, such as Figure 4 As shown, this embodiment can generate three parallel queues, and each queue is initialized to generate four tasks. The parameters in each task can be fully random or specified according to the situation. Among them, in the scenario of the parallel queue scheduling circuit, the number of queues and the queue depth parameters have specific meanings. The number of queues refers to the number of parallel processing queues contained in the parallel queue scheduling circuit, and each queue is responsible for processing tasks of different types or priorities. For example, in an artificial intelligence chip, there may be a queue that specializes in matrix operation tasks, another queue that specializes in vector operation tasks, and another queue that processes data handling tasks. In this case, three parallel queues are required. The queue depth parameter indicates the maximum number of tasks that each queue can store. This parameter is determined by the hardware design and directly reflects the physical storage capacity of the parallel queue. To illustrate with a specific example, assuming that the parallel queue scheduling circuit of an artificial intelligence chip has 3 parallel queues, each with a depth of 4, then queue A can store 4 matrix operation tasks (A0, A1, A2, A3), queue B can store 4 vector operation tasks (B0, B1, B2, B3), and queue C can store 4 data handling tasks (C0, C1, C2, C3). These tasks are executed in parallel in different queues according to dependencies and scheduling strategies.

[0052] Specifically, then, in the process of constructing dependencies between tasks in different queues according to the initial task set and predefined dependency rules to obtain a task dependency set, the system first randomly pairs tasks in different queues to generate preliminary task dependencies. Then the system screens these preliminary dependencies according to the predefined dependency rules, and in the process of inserting non-dependent tasks into adjacent tasks in each queue according to the initial task set and the task dependency set to obtain a parallel queue task set, the system first determines the positions to be inserted between adjacent tasks in each queue. Then, for each position to be inserted, the system randomly determines whether to insert a task and the number of tasks to be inserted. For the positions where tasks are determined to be inserted, the system randomly generates new tasks, including task types, parameters and formats. These newly inserted tasks will not establish new dependencies with tasks in other queues, thereby keeping the original dependency structure unchanged. Through this insertion process, the system finally obtains a complete parallel queue task set.

[0053] Furthermore, according to the initial task set and predefined dependency rules, dependency building processing is performed on tasks between different queues to obtain a task dependency set, including: randomly generating a first task dependency between different tasks in the initial task set; screening the first task dependency according to the dependency rules to obtain a second task dependency; and integrating all second task dependencies into a task dependency set.

[0054] Specifically, in the process of randomly generating the first task dependency relationship between different tasks in the initial task set, the system first traverses all tasks in the initial task set and numbers each task. Then, connection relationships are randomly established between tasks in different queues. These connection relationships are not restricted by any rules and are completely randomly generated. For example, for tasks A0, A1, A2, A3 in queue A, tasks B0, B1, B2, B3 in queue B, and tasks C0, C1, C2, C3 in queue C, the system randomly selects any two tasks in different queues to establish a dependent connection to form a first task dependency relationship. This process does not consider constraints such as the location of the task and the order of execution, and only performs random pairing.

[0055] Specifically, in the process of filtering the first task dependency according to the dependency rules and obtaining the second task dependency, the system filters the first task dependency according to two core principles. The first principle is to retain only the forward one-way task dependency, that is, the source task must be before the target task; the second principle is to retain only the dependencies between the front and back adjacent tasks. Specifically, the system checks each dependency. If a task attempts to depend on a task that is later in the other queue (such as task B2 depends on task A3) or a non-adjacent task (such as task B2 depends on task A0), these dependencies will be eliminated, and finally the second task dependency that meets the rules will be obtained.

[0056] Specifically, in the process of integrating all second task dependencies into a task dependency set, the system organizes and stores all the screened second task dependencies according to a unified data structure. This data structure needs to contain source task information, target task information, and the type of dependency between them. In this way, the system establishes a complete task dependency network, which contains all dependencies that meet the rules. This dependency set accurately reflects the forward unidirectional dependencies and adjacent task dependencies between tasks in different queues, providing a basis for subsequent scheduling verification.

[0057] Furthermore, after integrating all second task dependencies into a task dependency set, it also includes: obtaining circuit design properties of the parallel queue scheduling circuit, and adjusting the second task dependencies in the task dependency set according to the circuit design properties to obtain a new task dependency set.

[0058] Specifically, in the process of obtaining the circuit design properties of the parallel queue scheduling circuit, the system needs to read the hardware design specifications of the parallel queue scheduling circuit. These specifications include hardware-level constraints such as the physical storage capacity of the queue, the number of data processing units, the priority strategy of task scheduling, and the resource allocation mechanism. For example, in the design of an artificial intelligence chip, the matrix operation queue is equipped with 4 operation units, the vector operation queue is equipped with 2 operation units, and the data handling queue is equipped with 8 storage channels, which are all circuit design properties. At the same time, the circuit design properties also include the timing requirements of task processing, such as tasks in certain queues must be completed within a specific clock cycle, or data transmission between certain queues must follow specific bandwidth restrictions. By parsing the hardware design document or configuration file, the system obtains these specific circuit design attribute parameters.

[0059] Specifically, in the process of adjusting the second task dependency in the task dependency set according to the circuit design attributes, the system first checks whether each dependency complies with the constraints of the circuit design attributes. When it is found that some dependencies violate the hardware design constraints, the system will make corresponding adjustments to these dependencies. Taking the dependency between matrix operations and data handling as an example, if the circuit design stipulates that the matrix operation task must wait for the data handling to be completed before execution, then the system needs to add a mandatory dependency between the matrix operation task A1 and the data handling task C0. On the contrary, if some of the original dependencies will lead to a waste of hardware resources or a reduction in scheduling efficiency, such as causing idle waiting of the operation unit, the system will delete these unnecessary dependencies. In this way, the system dynamically adjusts the dependencies between tasks according to the actual hardware design constraints.

[0060] Specifically, in the end, the system reorganizes the adjusted dependencies to form a new set of task dependencies. This new set not only meets the basic forward unidirectional and adjacent task dependency rules, but also fully considers the actual constraints of hardware design. For example, in the final dependency set, the data handling task C0 must be executed before the matrix operation task A1, while the vector operation tasks B0 and B1 need to be executed serially due to hardware resource limitations. Such a set of task dependencies more accurately reflects the task execution constraints in the actual hardware environment, making the verification process closer to the actual operation scenario.

[0061] Furthermore, the screening of the first task dependency according to the dependency rule to obtain the second task dependency includes: determining whether the first task dependency is a forward unidirectional task dependency or a front-to-back adjacent task dependency according to the dependency rule; and screening out the first task dependency that is not a forward unidirectional task dependency or a front-to-back adjacent task dependency to obtain the second task dependency.

[0062] Specifically, in the process of judging whether the first task dependency is a forward unidirectional task dependency or a front-to-back adjacent task dependency according to the dependency rule, the system analyzes each dependency, such as analyzing the dependency of task B2. First, for the forward unidirectional dependency principle, the system checks whether the position of the source task in the global task sequence is before B2. By checking the position numbers of the tasks, the system finds that the position numbers of tasks A3 and C3 are greater than B2, indicating that these two tasks are after B2 in the execution order, so the dependency between B2 and A3 and C3 violates the forward unidirectional principle. Then, for the front-to-back adjacent principle, the system checks the relative positions of the source task and B2 in their respective queues. By calculating the position difference of the tasks in the queue, the system finds that the position difference between tasks A0 and C0 and B2 is greater than 1, indicating that these tasks are not adjacent to B2, so the dependency between B2 and A0 and C0 violates the front-to-back adjacent principle. After analysis, the system determines that task B2 can only establish a dependency with tasks A1, C1, or both tasks at the same time.

[0063] Specifically, in the process of filtering out the first task dependencies that are not forward unidirectional task dependencies or front-to-back adjacent task dependencies, and obtaining the second task dependencies, the system processes all dependencies involving task B2. When the dependency between task B2 and task A3 or C3 is found, since these dependencies violate the forward unidirectional principle, the system removes them from the dependency set. Similarly, when the dependency between task B2 and task A0 or C0 is found, since these dependencies violate the front-to-back adjacent principle, the system also removes them from the dependency set. After such screening, the system ultimately retains only the dependency between B2 and A1, C1, or the combination of dependencies established between B2 and A1 and C1 at the same time. These retained dependencies satisfy both the forward unidirectional principle and the front-to-back adjacent principle, and constitute a reasonable set of second task dependencies, and ultimately obtain the dependencies such as Figure 5 shown.

[0064] Furthermore, the adjacent tasks in each queue are processed with independent tasks according to the initial task set and the task dependency set to obtain a parallel queue task set, including: randomly determining the positions to be inserted between adjacent tasks of the same queue in the initial task set; performing random task generation processing at each position to be inserted to obtain an insertion task set, wherein the number, type, parameters and format of the inserted tasks in the insertion task set are all randomly generated; and performing task integration processing on each queue according to the insertion task set, the initial task set and the task dependency set to obtain a parallel queue task set and standard results corresponding to each task in the parallel queue task set.

[0065] Specifically, in the process of randomly determining the positions to be inserted between adjacent tasks of the same queue in the initial task set, the system first scans the positions between adjacent tasks in each queue. Taking queue B in the example, the system sets the positions to be inserted between tasks B0 and B1, between B1 and B2, and between B2 and B3, and finally randomly selects between B0 and B1 as the actual insertion position. Similarly, in queue C, the system randomly selects between C0 and C1, and between C1 and C2 as the actual insertion positions for subsequent task insertion.

[0066] Specifically, random task generation processing is then performed at each position to be inserted. In the process of obtaining the set of inserted tasks, the system generates random tasks for each determined insertion position. The number of inserted tasks refers to the number of tasks generated at each position to be inserted. For example, in the example, one task B0 is generated at the position to be inserted in queue B, and tasks C0 and C1 are generated at the two positions to be inserted in queue C. Task type refers to the functional attributes of a task, such as a matrix operation task, a vector operation task, or a data handling task. Task parameters refer to the specific configuration information required for task execution, such as the data size of the operation, the accuracy requirements of the operation, etc. The task format refers to the storage format of the task in the queue, including the task identifier, priority, and other information. The system randomly generates these features to form a complete insertion task.

[0067] Specifically, in the process of task integration for each queue based on the inserted task set, the initial task set, and the task dependency set, the system inserts the inserted tasks into the original queue according to their position information. In the example, task B0 is inserted into queue B, and tasks C0 and C1 are inserted into queue C. These inserted tasks follow three principles: the inserted tasks are randomly generated, the number of inserted tasks is random, and the inserted tasks no longer have dependencies on tasks in other queues. However, the dependencies between the original tasks will change position due to the insertion of new tasks. For example, task C1 in queue C has a backward dependency on task B0 in queue B, task C2 has a backward dependency on task A1, and task C3 has a non-adjacent dependency on task B2. These are all due to the change in the distance between the original adjacent tasks caused by the insertion of new tasks. The system finally integrates these tasks and their dependencies to obtain the following: Figure 6 The complete set of parallel queue tasks is shown.

[0068] 102. Perform hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set;

[0069] In one embodiment of the present invention, in the process of hardware signal conversion processing for each parallel queue task in the parallel queue task set, the system first identifies the hardware signal format corresponding to each task type according to the input interface specification of the parallel queue scheduling circuit. Then, the system performs signal format conversion on each task in the parallel queue task set, and maps the type, parameters and format of the task into a signal sequence recognizable by the hardware. Next, the system generates global control signals, including clock signals, reset signals, etc., which are used to control the basic operation of the hardware circuit. For the dependency between tasks, the system converts them into specific control signals or flags to indicate the order of task execution. At the same time, in order to test the performance of the circuit under various working conditions, the system also needs to generate some special boundary condition signals, such as signals for simulating queue full, queue empty, task cancellation, etc. After generating all necessary signals, the system packages these signals according to the predefined protocol to form a complete hardware excitation signal sequence. Finally, the system adjusts the timing of the generated signals to ensure that the transmission timing of the signals meets the requirements of the hardware design. After these processing steps, the system finally obtains a complete set of hardware stimulus signals, which includes the hardware representation of all parallel queue tasks and the necessary control signals, and can be directly used to drive the parallel queue scheduling circuit for verification testing.

[0070] 103. Run the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and compare the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit.

[0071] In one embodiment of the present invention, the parallel queue scheduling circuit is run according to the hardware excitation signal set to obtain the corresponding output result, and the output result is compared with the parallel queue task set to obtain the verification result of the parallel queue scheduling circuit, which includes: running the parallel queue scheduling circuit according to the hardware excitation signal set to obtain the corresponding output result, and judging whether the output result corresponding to each task is the same as the corresponding standard result; if they are the same, judging whether all circuit design problems of the parallel queue scheduling circuit have been eliminated according to the circuit design properties of the parallel queue scheduling circuit; if all circuit design problems have not been eliminated, regenerating the parallel queue task set for verification until all circuit design problems of the parallel queue scheduling circuit are eliminated, and setting the verification result as no problem with the parallel queue scheduling circuit; if they are different, setting the verification result as a problem with the parallel queue scheduling circuit.

[0072] Specifically, in the process of running the parallel queue scheduling circuit according to the hardware excitation signal set, obtaining the corresponding output results and judging whether the output results corresponding to each task are the same as the corresponding standard results, the system first collects the output signals and internal state information of the parallel queue scheduling circuit through the result acquisition module, including the task scheduling order, queue occupancy, task execution time and dependency processing, etc. Then, the system calculates the standard scheduling results based on the initial task set and the task dependency set according to the pre-defined ideal scheduling algorithm. Then, the system compares the collected actual output results with the calculated standard results in detail to check whether the scheduling order and execution time of each task are in line with expectations, and whether all dependency constraints are met.

[0073] When the actual output result is the same as the standard result, the system will determine whether all circuit design problems of the circuit have been eliminated based on the circuit design properties of the parallel queue scheduling circuit. The system first checks whether the current verification scenario covers all key test points, including different types of task combinations, various dependency situations, queue full and empty boundary conditions. If it is found that some test scenarios have not been covered, the system will re-call the task generation module to generate a new parallel queue task set, which will test the uncovered scenarios in a targeted manner. The system will repeatedly perform this verification process until all design problems are verified and eliminated, at which point the system will mark the verification result as no problem with the parallel queue scheduling circuit.

[0074] When the actual output result is different from the standard result, it means that a circuit design problem has been found in the current test scenario. The system will record specific error information, including the task number of the error, the type of error (such as scheduling order error, dependency violation, deadlock, etc.), and related context information. This error information is of great value to designers in locating and fixing problems. At the same time, the system will directly mark the verification result as a problem with the parallel queue scheduling circuit, and generate a detailed error report for designers to analyze and fix the problem. This strict verification mechanism ensures that circuit design problems can be discovered and solved in a timely manner.

[0075] In this embodiment, a parallel queue task set corresponding to the parallel queue scheduling circuit is generated according to preset parallel queue design requirements, wherein the parallel queue task set includes multiple parallel queue tasks; hardware signal conversion processing is performed on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set; the parallel queue scheduling circuit is run according to the hardware excitation signal set to obtain a corresponding output result, and the output result is compared with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit. The present invention can generate a more comprehensive parallel queue task set, and perform full coverage verification of the behavior of the parallel queue scheduling circuit based on these task sets, ensuring that the circuit can operate stably in various task scenarios, thereby improving the reliability and performance of the artificial intelligence chip.

[0076] The verification method of the parallel queue scheduling circuit in the embodiment of the present invention is described above. The verification device of the parallel queue scheduling circuit in the embodiment of the present invention is described below. Figure 2 , an embodiment of a verification device for a parallel queue scheduling circuit in an embodiment of the present invention includes:

[0077] The queue task generation module 201 is used to generate a parallel queue task set corresponding to the parallel queue scheduling circuit according to a preset parallel queue design requirement, wherein the parallel queue task set includes multiple parallel queue tasks;

[0078] The stimulus generation module 202 is used to perform hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware stimulus signal set;

[0079] The data comparison module 203 is used to run the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and compare the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit.

[0080] In an embodiment of the present invention, the verification device of the parallel queue scheduling circuit runs the verification method of the above-mentioned parallel queue scheduling circuit, and the verification device of the parallel queue scheduling circuit generates a parallel queue task set corresponding to the parallel queue scheduling circuit according to the preset parallel queue design requirements, wherein the parallel queue task set includes a plurality of parallel queue tasks; performs hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set; runs the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and compares the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit. The present invention can generate a more comprehensive parallel queue task set, and perform full coverage verification of the behavior of the parallel queue scheduling circuit according to these task sets, ensuring that the circuit can operate stably in various task scenarios, thereby improving the reliability and performance of the artificial intelligence chip.

[0081] above Figure 2 The verification device of the parallel queue scheduling circuit in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The verification device of the parallel queue scheduling circuit in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0082] Figure 3 : is a structural diagram of a verification device for a parallel queue scheduling circuit provided by an embodiment of the present invention. The verification device 300 for the parallel queue scheduling circuit may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 310 (for example, one or more processors) and a memory 320, and one or more storage media 330 (for example, one or more mass storage device terminals) storing application programs 333 or data 332. Among them, the memory 320 and the storage medium 330 may be short-term storage or permanent storage. The program stored in the storage medium 330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the verification device 300 for the parallel queue scheduling circuit. Furthermore, the processor 310 may be configured to communicate with the storage medium 330, and execute a series of instruction operations in the storage medium 330 on the verification device 300 for the parallel queue scheduling circuit to implement the steps of the verification method for the above-mentioned parallel queue scheduling circuit.

[0083] The verification device 300 of the parallel queue scheduling circuit may also include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input and output interfaces 360, and / or one or more operating systems 331, such as Windows Serve, Mac OS X, Unix, Linux, FreeBSD, etc. It will be appreciated by those skilled in the art that Figure 3 The structure of the verification device for the parallel queue scheduling circuit shown does not constitute a limitation on the verification device for the parallel queue scheduling circuit provided by the present invention, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0084] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the steps of the verification method of the parallel queue scheduling circuit.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device, or unit can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0086] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0087] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A verification method for a parallel queue scheduling circuit, characterized in that: The verification method of the parallel queue scheduling circuit includes: According to the preset parallel queue design requirements, a parallel queue task set corresponding to the parallel queue scheduling circuit is generated, wherein the parallel queue task set includes multiple parallel queue tasks; Performing hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set; The parallel queue scheduling circuit is run according to the hardware excitation signal set to obtain a corresponding output result, and the output result is compared with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit.

2. The verification method of the parallel queue scheduling circuit according to claim 1, characterized in that: The step of generating a parallel queue task set corresponding to the parallel queue scheduling circuit according to a preset parallel queue design requirement includes: According to the number of queues and queue depth parameters in the parallel queue design requirements, initial task generation processing is performed on each queue to obtain an initial task set; According to the initial task set and predefined dependency rules, dependency building processing is performed on tasks between different queues to obtain a task dependency set; According to the initial task set and the task dependency set, adjacent tasks in each queue are subjected to non-dependency task insertion processing to obtain a parallel queue task set.

3. The verification method of the parallel queue scheduling circuit according to claim 2, characterized in that: According to the initial task set and the predefined dependency rules, the tasks between different queues are subjected to dependency building processing to obtain a task dependency set including: Randomly generating a first task dependency relationship between different tasks in the initial task set; Filter the first task dependency according to the dependency rule to obtain a second task dependency; All second task dependencies are integrated into a task dependency set.

4. The verification method of the parallel queue scheduling circuit according to claim 3, characterized in that: After integrating all second task dependencies into a task dependency set, the method further includes: A circuit design attribute of the parallel queue scheduling circuit is obtained, and a second task dependency in the task dependency set is adjusted according to the circuit design attribute to obtain a new task dependency set.

5. The verification method of the parallel queue scheduling circuit according to claim 3, characterized in that: The filtering the first task dependency according to the dependency rule to obtain the second task dependency includes: Determine, according to the dependency rule, whether the first task dependency is a forward unidirectional task dependency or a front-to-back adjacent task dependency; The first task dependency relationships that are not forward unidirectional task dependency relationships or front-to-back adjacent task dependency relationships are screened out to obtain the second task dependency relationships.

6. The verification method of the parallel queue scheduling circuit according to claim 2, characterized in that: The process of inserting independent tasks into adjacent tasks in each queue according to the initial task set and the task dependency set to obtain a parallel queue task set includes: Randomly determine the positions to be inserted between adjacent tasks in the same queue in the initial task set; Perform random task generation processing at each to-be-inserted position to obtain an insertion task set, wherein the number, type, parameters and format of the insertion tasks in the insertion task set are all randomly generated; According to the inserted task set, the initial task set and the task dependency set, task integration processing is performed on each queue to obtain a parallel queue task set and standard results corresponding to each task in the parallel queue task set.

7. The verification method of the parallel queue scheduling circuit according to claim 6, characterized in that: The step of running the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and comparing the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit includes: Running the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and determining whether the output result corresponding to each task is the same as the corresponding standard result; If they are the same, determining whether all circuit design problems of the parallel queue scheduling circuit have been eliminated according to the circuit design properties of the parallel queue scheduling circuit; If all circuit design problems have not been eliminated, regenerate a parallel queue task set for verification until all circuit design problems of the parallel queue scheduling circuit are eliminated, and set the verification result as no problem with the parallel queue scheduling circuit; If they are different, the verification result is set as a problem with the parallel queue scheduling circuit.

8. A verification device for a parallel queue scheduling circuit, characterized in that: The verification device of the parallel queue scheduling circuit includes: A queue task generation module, used to generate a parallel queue task set corresponding to the parallel queue scheduling circuit according to a preset parallel queue design requirement, wherein the parallel queue task set includes multiple parallel queue tasks; An excitation generation module, used for performing hardware signal conversion processing on each parallel queue task in the parallel queue task set to obtain a hardware excitation signal set; The data comparison module is used to run the parallel queue scheduling circuit according to the hardware excitation signal set to obtain a corresponding output result, and compare the output result with the parallel queue task set to obtain a verification result of the parallel queue scheduling circuit.

9. A verification device for a parallel queue scheduling circuit, characterized in that: The verification device of the parallel queue scheduling circuit comprises: a memory and at least one processor, wherein the memory stores instructions; The at least one processor calls the instruction in the memory to enable the verification device of the parallel queue scheduling circuit to perform the steps of the verification method of the parallel queue scheduling circuit as described in any one of claims 1-7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by the processor, the steps of the verification method of the parallel queue scheduling circuit as described in any one of claims 1 to 7 are implemented.

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