Built-in self-test circuit, built-in self-test method and memory

Abstract

The invention provides a built-in self-test circuit, a built-in self-test method and a memory. The method comprises the following steps: generating initial test data through a data module; receiving a flipping signal through a flipping module, if the flipping signal is in a first state, performing negation processing on the initial test data, and generating and outputting target test data; and if the flip signal is in the second state, directly outputting the initial test data as target test data.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a built-in self-test circuit, a built-in self-test method and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements on the data transmission speed when manufacturing and using computers and other equipment. Taking Dynamic Random Access Memory (DRAM) as an example, in order to ensure the correctness of its storage function, the memory needs to be tested, such as memory built-in self-test (MBIST). However, the current built-in self-test has low flexibility and the test effect is not satisfactory. Summary of the invention

[0003] The present disclosure provides a built-in self-test circuit, a built-in self-test method and a memory.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a built-in self-test circuit, the built-in self-test circuit comprising:

[0006] A data module configured to output initial test data when the built-in self-test starts;

[0007] a flip module connected to the data module and configured to receive a flip signal and the initial test data; if the flip signal is in a first state, the initial test data is inverted to generate and output target test data; if the flip signal is in a second state, the initial test data is directly output as the target test data;

[0008] The transmission module is connected to the flip module and the storage array, and is configured to receive the target test data and transmit the target test data to corresponding storage units in the storage array.

[0009] In some embodiments, the initial test data includes N bits, the flip signal is only 1 bit, and the target test data includes N bits; the flip module includes N logic units, where N is a positive integer greater than 1;

[0010] The i-th logic unit is connected to the data module and is configured to directly output the i-th initial test data or invert the i-th initial test data and output it based on the state of the flip signal to obtain the i-th target test data, i≤N.

[0011] In some embodiments, the initial test data includes N bits, the flip signal includes N bits, and the target test data includes N bits; the flip module includes N logic units;

[0012] The i-th logic unit is connected to the data module and is configured to directly output the i-th initial test data or invert the i-th initial test data and output it based on the state of the i-th flip signal to obtain the i-th target test data, i≤N.

[0013] In some embodiments, the logic unit includes a tri-state transmission gate, a tri-state inverter, and a first inverter;

[0014] For the three-state transmission gate and the three-state inverter, their input ends are both used to receive the initial test data, their output ends are both connected to the input end of the first inverter, their control ends receive the flip signal, and the first inverter is used to output the target test data; wherein the three-state transmission gate is enabled based on the flip signal in the first state, and the three-state inverter is enabled based on the flip signal in the second state.

[0015] In some embodiments, the built-in self-test circuit further comprises:

[0016] The adjustment module is configured to invert the level state of the flip signal at every preset time interval to generate a new flip signal; and / or, receive a write operation command, and invert the level state of the flip signal at every first number of write operation commands to generate a new flip signal;

[0017] The transmission module is further configured to receive an address signal and the write operation command; and upon receiving the write operation command, transmit the N bits of the target test data to a storage unit indicated by the address signal.

[0018] In some embodiments, the built-in self-test circuit further comprises:

[0019] An address counter configured to generate the address signal; and

[0020] After the transmission module executes one of the write operation commands, the address signal is incremented by one; or after the transmission module executes a second number of the write operation commands, the address signal is incremented by one.

[0021] In some embodiments, when the first number is 1, the adjustment module includes a first sampler, a second inverter, and an output module;

[0022] The clock end of the first sampler receives the write operation command, the output end of the first sampler is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the first sampler, and the output end of the second inverter outputs a preprocessing signal;

[0023] The output module is configured to receive the preprocessing signal and the mode indication signal; when the mode indication signal is in an enabled state, output the flip signal based on the preprocessing signal; when the mode indication signal is in a disabled state, keep the flip signal unchanged in a second state; wherein, after the built-in self-test starts, the mode indication signal is in an enabled state.

[0024] In some embodiments, the adjustment module includes a plurality of cascaded second samplers, third inverters, and output modules;

[0025] The clock end of the first second sampler receives a write operation command, the clock ends of the remaining second samplers are connected to the inverting output end of the previous second sampler, the input end of each second sampler is connected to its own inverting output end, the output end of the last second sampler is connected to the input end of the third inverter, and the output end of the third inverter outputs a preprocessing signal;

[0026] The output module is configured to receive the preprocessing signal and the mode indication signal; when the mode indication signal is in an enabled state, output the flip signal based on the preprocessing signal; when the mode indication signal is in a disabled state, keep the flip signal unchanged in a second state; wherein, after the built-in self-test starts, the mode indication signal is in an enabled state.

[0027] In a second aspect, an embodiment of the present disclosure provides a built-in self-test method, the built-in self-test method comprising:

[0028] During built-in self-test, receiving a flip signal and initial test data;

[0029] If the flip signal is in the first state, the initial test data is inverted to generate target test data; or, if the flip signal is in the second state, the initial test data is determined as the target test data;

[0030] The target test data is transferred to a corresponding storage unit.

[0031] In a third aspect, an embodiment of the present disclosure provides a memory, wherein the memory includes the built-in self-test circuit described in the first aspect.

[0032] The embodiments of the present disclosure provide a built-in self-test circuit, a built-in self-test method and a memory, which can improve the flexibility of the built-in self-test and obtain better test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a built-in self-test circuit provided by an embodiment of the present disclosure;

[0034] Figure 2A A schematic diagram of the structure of a flip module provided in an embodiment of the present disclosure;

[0035] Figure 2B A signal timing diagram provided for an embodiment of the present disclosure;

[0036] Figure 3A A schematic diagram of the structure of another flip module provided in an embodiment of the present disclosure;

[0037] Figure 3B Another signal timing diagram provided for an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of a specific structure of a logic subunit provided in an embodiment of the present disclosure;

[0039] Figure 5 A schematic diagram of the structure of another built-in self-test circuit provided by an embodiment of the present disclosure;

[0040] Figure 6 A schematic diagram of the structure of an adjustment module provided in an embodiment of the present disclosure;

[0041] Figure 7 A schematic diagram of the structure of another adjustment module provided in an embodiment of the present disclosure;

[0042] Figure 8 A flow chart of a built-in self-test method provided in an embodiment of the present disclosure;

[0043] Fig. 9 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0045] The following are explanations of professional terms involved in the embodiments of the present disclosure and the corresponding relationships of some terms:

[0046] Synchronous Dynamic Random Access Memory (SDRAM);

[0047] Double Data Rate SDRAM (DDR);

[0048] Low Power DDR (LPDDR).

[0049] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the structure of a built-in self-test circuit 10 provided in an embodiment of the present disclosure. Figure 1 As shown, the built-in self-test circuit 10 includes:

[0051] The data module 11 is configured to output initial test data when the built-in self-test starts;

[0052] The flip module 12 is connected to the data module 11 and is configured to receive a flip signal and initial test data; if the flip signal is in the first state, the initial test data is inverted to generate and output target test data; if the flip signal is in the second state, the initial test data is directly output as the target test data;

[0053] The transmission module 13 is connected to the flip module 12 and the storage array 14 , and is configured to receive target test data and transmit the target test data to corresponding storage units in the storage array 14 .

[0054] It should be noted that the built-in self-test circuit 10 can be applied to various types of dynamic memories 10, such as DRAM, SDRAM, DDR, LPDDR, etc.

[0055] Here, the data module 11 can be embodied as a plurality of registers. In a specific embodiment, these registers store 32 bits of data for testing, and the 32 bits of test data are divided into 4 groups, each group including 8 bits of data; each time a built-in self-test (BIST) is performed, a group of data needs to be selected as the initial test data mentioned above. In the disclosed embodiment, after the initial test data is selected, it is also possible to determine whether the initial test data needs to be flipped by a flip signal, so as to use the initial test data or the inverted data of the initial test data for testing, which can improve the flexibility of the built-in self-test and achieve better test results.

[0056] It should be understood that, for a circuit, data can be embodied as 0 and 1. In the present disclosure, the negation process refers to inverting data 0 into data 1, and inverting data 1 into data 0.

[0057] In some embodiments, Figure 2A As shown, the initial test data includes N bits and can be expressed as Data<N-1:0> ; The flip signal ReverseEn is only 1 bit; The target test data includes N bits and can be expressed as BistData<N-1:0> ; N is a positive integer greater than 1.

[0058] Specifically, the flip module 12 includes N logic units 121; the i-th logic unit 121 is connected to the data module 11 and is configured to, based on the state of the flip signal ReverseEn, perform initial test data Data of the i-th bit. <i-1>Directly output or the initial test data Data of the i-th bit <i-1>After inversion, output to get the i-th target test data BistData <i-1>, i≤N.

[0059] It should be noted that, taking N=8 as an example, the reversal signal ReverseEn simultaneously controls whether to reverse the 8-bit initial test data. Figure 2B A signal timing diagram is provided. Figure 2B In the example, the test enable signal BistEn indicates whether to execute the built-in self-test; each write operation command (embodied as 1 pulse) indicates that the corresponding target test data BistData<7:0> is transmitted to the corresponding storage unit; a combination of the target test data BistData<7:0> is named Data_a (for example, 00001111), that is, Data_a includes 8 bits of data, and Data and ~Data_a (for example, 11110000) are inverted data. In other words, if Figure 2B As shown, for the first four write operation commands, the flip signal ReverseEn is in the second state ( Figure 2B Taking the low level as an example), Data_a is transmitted to the corresponding storage unit; for the last four write operation commands, the flip signal ReverseEn is in the first state ( Figure 2B Taking a high level as an example), ~Data_a is thus transmitted to the corresponding storage unit.

[0060] In other embodiments, N may also be other positive integers.

[0061] In other embodiments, Figure 3A As shown, the initial test data includes N bits and can be expressed as Data<N-1:0> ; The flip signal includes N bits and can be expressed as ReverseEn<N-1:0> ; The target test data consists of N bits and can be expressed as BistData<N-1:0> Accordingly, the flip module 12 includes N logic units 121; the i-th logic unit 121 is connected to the data module 11 and is configured to flip the i-th bit based on the signal ReverseEn <i-1>The state of the initial test data Data for the i-th bit <i-1>Directly output or the initial test data Data of the i-th bit <i-1>After inversion, output to get the i-th target test data BistData <i-1>, i≤N.

[0062] In this way, no matter what the value of N is, the flip signal can independently control whether to flip each bit of initial test data, thereby better improving the test flexibility.

[0063] It should be noted that Figure 3B A signal timing diagram is provided. Figure 3B In the target test data BistData<7:0>, each bit of data can be flexibly adjusted according to the flip signal ReverseEn<7:0>. For 8 different write operation commands, the flip signal ReverseEn<7:0> has 8 different combinations, Rev_a~Rev_h, and the corresponding target test data BistData<7:0> also has 8 different combinations, Data_a~Data_h. For example, Data_a is 00001111, Data_b is 11001111, Data_c is 01001111, Data_d is 01000011...

[0064] In other embodiments, N may also be other positive integers.

[0065] It should be noted that different logic units 121 all adopt the same structure.

[0066] In a first specific embodiment, Figure 4 As shown, the aforementioned logic unit 121 is structured as follows.

[0067] The logic unit 121 includes a three-state transmission gate 202, a three-state inverter 201 and a first inverter 203; for the three-state transmission gate 202 and the three-state inverter 201, their input ends are used to receive the initial test data Data, their output ends are connected to the input end of the first inverter 203, their control ends receive the flip signal, and the first inverter 203 is used to output the target test data BistData; wherein the three-state transmission gate 202 is enabled based on the flip signal of the first state, and the three-state inverter 201 is enabled based on the flip signal of the second state.

[0068] In this way, if the flip signal is in the first state, the three-state transmission gate 202 outputs the initial data signal Data, and the three-state inverter 201 shields the input terminal signal; the first inverter 203 inverts the initial data signal Data obtained from the three-state transmission gate 202, thereby outputting the inverted data of the initial data signal Data as the target test data BistData; on the contrary, if the flip signal is in the second state, the three-state transmission gate 202 shields the input terminal signal, and the three-state inverter 201 inverts and outputs the initial data signal Data; the first inverter 203 inverts the inverted data of the initial data signal Data obtained from the three-state inverter 201 again, thereby outputting the initial data signal Data as the target test data BistData.

[0069] In particular, such as Figure 4 As shown, the present disclosure is also provided with a complementary flip signal ReverseEnN of the flip signal, which realizes the control effect together with the flip signal ReverseEn. In some embodiments, the flip signal ReverseEn and the complementary flip signal ReverseEnN can be used as power switch signals of the tri-state transmission gate 202 and the tri-state inverter 201, so that the tri-state transmission gate 202 and the tri-state inverter 201 are connected to the corresponding power signal, thereby controlling them to realize their corresponding functions. The first state of the flip signal can specifically refer to the flip signal ReverseEn=1 and the complementary flip signal ReverseEnN=0, and the second state of the flip signal can specifically refer to the flip signal ReverseEn=0 and the complementary flip signal ReverseEnN=1; or, the first state of the flip signal can specifically refer to the flip signal ReverseEn=0 and the complementary flip signal ReverseEnN=1, and the second state of the flip signal can specifically refer to the flip signal ReverseEn=1 and the complementary flip signal ReverseEnN=0.

[0070] In some embodiments, Figure 5 As shown, the built-in self-test circuit 10 further includes:

[0071] The adjustment module 15 is configured to invert the level state of the flip signal at every preset time interval to generate a new flip signal; and / or, receive a write operation command, and invert the level state of the flip signal at every first number of write operation commands to generate a new flip signal;

[0072] The transmission module 13 is further configured to receive an address signal and a write operation command; and, upon receiving the write operation command, write the N-bit target test data to the storage unit indicated by the address signal.

[0073] In simple terms, in the first mode, the initial test data will be flipped once every first number (the specific value can be set by the user) of write operation commands. Taking the first number as 2 as an example, for the first and second write operation commands, write based on the initial test data; for the third and fourth write operation commands, write based on the inverted data of the initial test data; for the fifth and sixth write operation commands, write based on the initial test data...

[0074] In the second mode, the initial test data will be flipped once at every preset time interval. Similarly, the value of the preset time interval can be set by the user.

[0075] It should be noted that the built-in self-test circuit 10 may have only the first mode or the second mode mentioned above; of course, the built-in self-test circuit 10 may also have both of the above modes, and one of the modes is selected and enabled according to user instructions.

[0076] It should also be noted that, in a specific embodiment, the storage array 14 can be divided into 16 storage column planes or 32 storage column planes for management, and the N-bit target test data will be transmitted to each storage column plane. In other words, for each write operation command, there are actually (16×8)=128 storage cells to be written with data, or 32×8=256 storage cells to be written with data.

[0077] In some embodiments, the built-in self-test circuit 10 further includes:

[0078] The address counter is configured to generate an address signal; and, after the transmission module 13 executes a write operation command, the address signal is incremented by one; or, after the transmission module 13 executes a second number (which is a positive integer and can be set by the user) of write operation commands, the address signal is incremented by one.

[0079] In this way, in one case, for the first write operation command, the target test data is written based on the first address signal; for the second write operation command, the target test data is written based on the second address signal, that is, different write operation commands correspond to different write objects; in another case, the second number of write operation commands will correspond to the same write object, that is, the write object is written repeatedly.

[0080] Here, the second number is also useful for setting, and the second number may be the same as or different from the first number.

[0081] The following is a specific structural example of the adjustment module 15. Figure 6 , when the first number is 1, the adjustment module 15 includes a first sampler 1511, a second inverter 1512 and an output module 153;

[0082] The clock end of the first sampler 1511 receives a write operation command, the output end of the first sampler 1511 is connected to the input end of the second inverter 1512, the output end of the second inverter 1512 is connected to the input end of the first sampler 1511, and the output end of the second inverter 1512 outputs a preprocessing signal;

[0083] The output module 153 is configured to receive the preprocessing signal and the mode indication signal; when the mode indication signal is in the enabled state, the flip signal ReverseEn (and the complementary flip signal ReverseEnN) is output based on the preprocessing signal; when the mode indication signal is in the disabled state, the flip signal ReverseEn is kept in the second state (and the inverted flip signal ReverseEnN is kept in the first state). After the built-in self-test starts, the mode indication signal is in the enabled state.

[0084] Exemplarily, if the enable state of the mode indication signal is low level, the output module 153 may be embodied as an OR gate (eg Figure 6 Of course, there are other possibilities for the output module 153, such as an AND gate, an XOR gate, an XNOR gate, etc.

[0085] Another specific structural example of the adjustment module 15 is provided below. Figure 7 , the adjustment module 15 includes a plurality of cascaded second samplers 1521, a plurality of third inverters 1522 and an output module 153;

[0086] The clock end of the first second sampler 1521 receives the write operation command, the clock ends of the remaining second samplers 1521 are connected to the inverting output end of the previous second sampler 1521, the input end of each second sampler 1521 is connected to its own inverting output end, the output end of the previous second sampler 1521 is connected to the input end of the next second sampler 1521, the output end of the last second sampler 1521 is connected to the input end of the third inverter 1522, and the output end of the third inverter 1522 outputs the preprocessing signal;

[0087] The output module 153 is configured to receive the preprocessing signal and the mode indication signal; when the mode indication signal is in the enabled state, the flip signal ReverseEn (and the complementary flip signal ReverseEnN) are output based on the preprocessing signal; when the mode indication signal is in the disabled state, the flip signal ReverseEn is kept in the second state (and the inverted flip signal ReverseEnN is kept in the first state). Here, if the first number = 2 M-1 , then the number of the second samplers is M, where M is a positive integer greater than 1.

[0088] If, 2 M-1 ≤First quantity<2 M , then the number of the second samplers is M, and an additional decoding unit and reset logic (implemented by the reset signal RstN) need to be introduced. Here, the decoding unit can be composed of one or more of an AND gate, an OR gate, a NAND gate, an OR gate, and an XOR gate.

[0089] In addition, the adjustment module 15 may also include a timer. When the timing time of the timer reaches a preset time interval, the timer outputs a sampling pulse and performs a reset operation. The sampling pulse output by the sampler will replace Figure 6 By sampling the write operation command in the program, the flip signal can also be controlled.

[0090] Simply put, during the built-in self-test process, external commands can be considered invalid and cannot enter the circuit to participate in the work. The built-in self-test relies on the internal oscillation clock signal to decode the internal command, transfer the test data to the storage array, and implement the test of different types of test data. In the embodiment of the present disclosure, during the built-in self-test process, the data can still be flipped by controlling the flip signal, so that the same storage cell is in different data environments (that is, the adjacent cells of the storage cell all store data 0, some adjacent cells of the storage cell store data 1 and some adjacent cells store data 0... and so on). The same cell realizes different data environments, which can provide better test results. Specifically, data flipping can be achieved by counting the write operation command, and data flipping can also be achieved by timing.

[0091] In another embodiment of the present disclosure, see Figure 8 , which shows a built-in self-test method provided by an embodiment of the present disclosure, the built-in self-test method comprising:

[0092] S401: receiving a flip signal and initial test data during a built-in self-test process;

[0093] S402: if the flip signal is in the first state, inverting the initial test data to generate target test data; or, if the flip signal is in the second state, determining the initial test data as the target test data;

[0094] S403: Transmit the target test data to a corresponding storage unit.

[0095] In some embodiments, the initial test data includes N bits, the flip signal is only 1 bit, and the target test data includes N bits; S402 may specifically include:

[0096] Based on the state of the flip signal, the initial test data of the i-th bit is directly output or the initial test data of the i-th bit is inverted and then output to obtain the target test data of the i-th bit, i≤N.

[0097] In some other embodiments, the initial test data includes N bits, the flip signal includes N bits, and the target test data includes N bits; S402 may specifically include:

[0098] Based on the state of the i-th bit flip signal, the i-th bit initial test data is directly output or the i-th bit initial test data is inverted and then output to obtain the i-th bit target test data, i≤N.

[0099] In summary, the embodiments of the present disclosure provide a built-in self-test method, which improves test flexibility by flexibly transmitting initial test data or inverted data of the initial test data to a storage unit.

[0100] In another embodiment of the present disclosure, see Fig. 9 , which shows a memory 50 provided by an embodiment of the present disclosure, and the memory 50 at least includes the aforementioned built-in self-test circuit 10.

[0101] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the existence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A built-in self-test circuit, characterized in that: The built-in self-test circuit comprises: A data module configured to output initial test data when the built-in self-test starts; a flip module connected to the data module and configured to receive a flip signal and the initial test data; if the flip signal is in a first state, the initial test data is inverted to generate and output target test data; if the flip signal is in a second state, the initial test data is directly output as the target test data; The transmission module is connected to the flip module and the storage array, and is configured to receive the target test data and transmit the target test data to corresponding storage units in the storage array.

2. The circuit according to claim 1, characterized in that The initial test data includes N bits, the flip signal is only 1 bit, and the target test data includes N bits; the flip module includes N logic units, where N is a positive integer greater than 1; The i-th logic unit is connected to the data module and is configured to directly output the i-th initial test data or invert the i-th initial test data and output it based on the state of the flip signal to obtain the i-th target test data, i≤N.

3. The circuit according to claim 1, characterized in that The initial test data includes N bits, the flip signal includes N bits, and the target test data includes N bits; the flip module includes N logic units; The i-th logic unit is connected to the data module and is configured to directly output the i-th initial test data or invert the i-th initial test data and output it based on the state of the i-th flip signal to obtain the i-th target test data, i≤N.

4. The circuit according to claim 2 or 3, characterized in that The logic unit includes a tri-state transmission gate, a tri-state inverter and a first inverter; For the three-state transmission gate and the three-state inverter, their input ends are both used to receive the initial test data, their output ends are both connected to the input end of the first inverter, their control ends receive the flip signal, and the first inverter is used to output the target test data; wherein the three-state transmission gate is enabled based on the flip signal in the first state, and the three-state inverter is enabled based on the flip signal in the second state.

5. The circuit according to claim 4, characterized in that The built-in self-test circuit also includes: The adjustment module is configured to invert the level state of the flip signal at every preset time interval to generate a new flip signal; and / or, receive a write operation command, and invert the level state of the flip signal at every first number of write operation commands to generate a new flip signal; The transmission module is further configured to receive an address signal and the write operation command; and upon receiving the write operation command, transmit the N bits of the target test data to a storage unit indicated by the address signal.

6. The circuit according to claim 5, characterized in that The built-in self-test circuit also includes: An address counter configured to generate the address signal; and After the transmission module executes one of the write operation commands, the address signal is incremented by one; or after the transmission module executes a second number of the write operation commands, the address signal is incremented by one.

7. The circuit according to claim 5, characterized in that When the first number is 1, the adjustment module includes a first sampler, a second inverter and an output module; The clock end of the first sampler receives the write operation command, the output end of the first sampler is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the first sampler, and the output end of the second inverter outputs a preprocessing signal; The output module is configured to receive the preprocessing signal and the mode indication signal; When the mode indication signal is in an enabled state, the flip signal is output based on the preprocessing signal; when the mode indication signal is in a disabled state, the flip signal is kept in a second state unchanged; wherein, after the built-in self-test starts, the mode indication signal is in an enabled state.

8. The circuit according to claim 5, characterized in that The adjustment module includes a plurality of cascaded second samplers, a third inverter and an output module; The clock end of the first second sampler receives a write operation command, the clock ends of the remaining second samplers are connected to the inverting output end of the previous second sampler, the input end of each second sampler is connected to its own inverting output end, the output end of the last second sampler is connected to the input end of the third inverter, and the output end of the third inverter outputs a preprocessing signal; The output module is configured to receive the preprocessing signal and the mode indication signal; When the mode indication signal is in an enabled state, the flip signal is output based on the preprocessing signal; when the mode indication signal is in a disabled state, the flip signal is kept in a second state unchanged; wherein, after the built-in self-test starts, the mode indication signal is in an enabled state.

9. A built-in self-test method, characterized in that: The built-in self-test method comprises: During built-in self-test, receiving a flip signal and initial test data; If the flip signal is in the first state, the initial test data is inverted to generate target test data; or, if the flip signal is in the second state, the initial test data is determined as the target test data; The target test data is transferred to a corresponding storage unit.

10. A memory, characterized in that: The memory comprises a built-in self-test circuit as claimed in any one of claims 1-8.

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