Reliability evaluation method and system for side wall gate oxide process and electronic equipment thereof

Abstract

The invention discloses a method and a system for evaluating the reliability of a side wall gate oxide process and electronic equipment thereof. In the TDDB test structure, the gate length L of a single finger is adjusted by increasing or reducing the number of fingers, and then a reliability test is performed to obtain a TDDB test result; and performing data fitting by using L, a TDDB test result and a gate leakage current logarithm, and finally obtaining the TDDB life of the overlapping area of the LDD region and the gate and the quality of a gate oxide layer between the lower source and drain near the side wall and the gate. The invention provides a new calculation method which is used for making up the technical blank of reliability evaluation of part of gate oxide near a side wall in the prior art. According to the method, the TDDB service life of the overlap area Sov of the LDD region and the gate is evaluated more accurately, so that a process engineer is helped to deeply understand and control the manufacturing process of the gate oxide layer, especially in the side wall and the poly region, and the optimization of the manufacturing process of part of the gate oxide layer near the side wall is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a reliability evaluation method and system for a sidewall gate oxide process and electronic equipment thereof. Background Art

[0002] In the field of semiconductor manufacturing, especially in wafer testing, a test key refers to a test structure or area on the wafer that is specially designed to collect specific test data. These test structures are usually located in non-product areas on the wafer, such as scribe lines or scribe lanes on the edge of the wafer, so that the wafer can be tested before being cut into individual chips (dies). Figure 1 (a)-(c).

[0003] The main purpose of designing different Testkeys is to monitor various process parameters in the wafer manufacturing process, such as transistor performance, metal wire resistance, capacitance, contact resistance, etc. These test data (WAT data) are essential for evaluating whether the wafer meets the predetermined electrical specifications and help identify possible anomalies or problems in the manufacturing process. By designing the test structure in the Testkey, engineers can monitor every step of the wafer manufacturing process to ensure that the wafer product has the required performance and reliability. Since the Testkey does not occupy the area of ​​the product chip, they do not increase the cost of the chip.

[0004] In WAT testing, TDDB (Time-Dependent Dielectric Breakdown) testing is a common method for evaluating the electrical integrity of gate oxides. It is designed to detect potential defects in the gate oxide layer and monitor processes related to the gate oxide layer. ov There are more defects in the gate oxide, and the leakage is more serious. According to the results of many papers, the life of TDDB is closely related to factors such as the shape of the bottom of the side wall, the shape of the edge gate oxide layer, the gate length and the overlay accuracy, and these key factors are mainly concentrated near the side wall at the edge of the gate. Therefore, the current research work urgently needs a test method and a corresponding structure to correctly characterize the quality of this part of the gate oxide.

[0005] In existing TDDB tests, the Testkey used is usually Bulk and Transistor Array structures, such as Figure 2As shown. Bulk is a transistor composed of a large area of ​​gate and gate oxide, which is mainly used to evaluate the intrinsic life of a large area of ​​gate oxide. Transistor Array divides the entire block of gate oxide into multiple fingers to form multiple transistor arrays, which are mainly used to evaluate the gate edge gate oxide quality. In the Transistor Arry structure, the polysilicon gate (poly) adopts a multi-sided dense structure to characterize the impact of the poly edge gate oxide layer quality on dielectric breakdown. In the bulk structure, a complete MOSFET structure is tested, usually as Figure 3 As shown. The test process is carried out according to the JEDEC standard. During the test, the source (Source) and the drain (Drain) and the bulk (Bulk) are connected together as one terminal of the capacitor. The gate (Gate) is used as the other terminal of the capacitor, as shown in Figure 4 shown.

[0006] After TDDB testing on both Bulk and Transistor Array structures, the life expectancy under temperature and stress conditions is generally estimated based on reliability standards. Under normal procedures, once the TDDB life expectancy is obtained, the TDDB test ends here.

[0007] It can be seen that 1) it is difficult to estimate the lifetime of local gate oxide using existing methods. This is because the lifetime estimated by TDDB is the lifetime of the entire gate oxide. 2) Using Bulk or Transistor Array as Testkey also has defects: using bulk structure will make it difficult to effectively eliminate the potential impact of gate oxide on experimental results under large poly area; although Transistor Array can qualitatively evaluate the gate oxide quality at the gate edge, it is difficult to estimate the gate oxide quality except S ov 3) The existing reliability test transistor array size is small, so the correlation between the gate edge and the gate oxide quality is weak in the obtained data.

[0008] In order to more comprehensively and accurately evaluate the reliability of the sidewall gate oxide process and deeply study the S / D near the sidewall and the gate oxide quality and life span, the present invention proposes a novel reliability evaluation method for the sidewall gate oxide process. Summary of the invention

[0009] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a reliability evaluation method and system for a sidewall gate oxide process and an electronic device thereof. The present invention proposes to extrapolate the sensitivity of the gate oxide near the sidewall in TDDB based on the relationship between the ratio of the poly perimeter or area to the total poly area and TDDB.

[0010] In a first aspect, the present invention provides a reliability evaluation method for a novel sidewall gate oxide process, specifically: In the TDDB test structure, the gate length of a single finger is adjusted by increasing or decreasing the number of fingers, and then a reliability test is performed to obtain the TDDB test result; in the process of adjusting the gate length of a single finger, the total area S of the gate needs to be ensured. poly The total effective gate length L is unchanged eff become smaller; Use the gate length L of a single finger as the horizontal axis and the TDDB test result as the vertical axis to perform data fitting; extrapolate the TDDB test result corresponding to when L approaches zero, and use the TDDB test result as the overlap area S of the LDD region and the gate. ov TDDB lifetime; Using the gate length L of a single finger as the horizontal axis, the logarithm of the gate leakage current lg (I g ) as the ordinate to perform data fitting; extrapolate the corresponding gate leakage current logarithm lg (I g ), and the gate leakage current logarithm is used as the leakage current value between the lower source and drain near the side wall and the gate to characterize the quality of the gate oxide layer.

[0011] In a second aspect, the present invention provides a reliability evaluation system for a sidewall gate oxide process for implementing the method, comprising: The reliability test module is responsible for performing reliability test on the TDDB test structure after adjusting the gate length of a single finger and obtaining the TDDB test result; The TDDB lifetime calculation module for the overlapping area between the LDD region and the gate is responsible for fitting the data using the gate length L of a single finger as the horizontal coordinate and the TDDB test result as the vertical coordinate; extrapolating the TDDB test result corresponding to when L approaches zero, and using the TDDB test result as the overlapping area S between the LDD region and the gate. ov TDDB lifetime; The gate oxide quality calculation module between the lower source and drain near the side wall is responsible for using the gate length L of a single finger as the horizontal coordinate and the gate leakage current logarithm lg (I g ) as the ordinate to perform data fitting; extrapolate the corresponding gate leakage current logarithm lg (I g ), and the gate leakage current logarithm is used as the leakage current value between the lower source and drain near the sidewall and the gate to characterize the quality of the gate oxide layer.

[0012] In a third aspect, the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the method is implemented when the processor executes the program.

[0013] In a fourth aspect, the present invention provides a machine-readable storage medium having a computer program stored thereon, wherein the computer program implements the method when executed by a processor.

[0014] The beneficial effects of the present invention are: The present invention proposes that the overlap area S of the LDD region and the gate ov A new calculation method for the TDDB lifetime and the quality of the gate oxide layer between the source, drain and gate near the side wall is used to fill the technical gap in the reliability assessment of the gate oxide near the side wall in the existing technology and provide an effective solution.

[0015] The present invention more accurately evaluates the overlap area S of the LDD region and the gate. ov The TDDB lifetime helps process engineers deeply understand and control the manufacturing process of the gate oxide layer, especially in the sidewall and poly area. This helps to optimize the manufacturing process of the gate oxide layer near the sidewall, thereby improving the overall performance and reliability of semiconductor devices. Because it provides fast and accurate reliability evaluation, it speeds up the product development process, accelerates process improvement and product iteration, shortens the R&D cycle, and improves product market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 Schematic diagram of chip scribe grooves, where (a) is the chip on the whole wafer, (b) is the enlarged chip and scribe grooves, and (c) is the chip scribe grooves under a microscope; Figure 2 The following are schematic diagrams of the Bulk and Transistor Array testkey structures used in conventional TDDB testing, where (a) is a top view of the Bulk testkey structure, (b) is a side view of the Bulk testkey structure, (c) is a top view of the Transistor Array testkey structure, and (d) is a side view of the Transistor Array testkey structure. Figure 3 This is a schematic diagram of the Testkey structure (the red circle is the gate oxide that needs to be characterized); Figure 4 It is the gate oxide integrity test wiring; Figure 5 This is a partial testkey diagram used to characterize the gate oxide quality near the side wall. The total area of ​​the gate is S poly =25; (a)-(d) show the gate lengths of different single fingers, L=5, 1, 0.5, 0.25 respectively; Figure 6 is the principle of the lifetime extrapolation method, where (a) L in MOSFET ov Schematic diagram, (b) S in MOSFET ov Schematic diagram, (c) As N increases, L decreases, S ov Increase, (d) L and S ov Relationship, (e) L and L eff Relationship (cross-section diagram), (f) As N increases, L and L eff changes in (profile); Figure 7 It is the fitting and extrapolation of TDDB lifetime; Figure 8 is the fitting and extrapolation of leakage current; Fig. 9 This is the processing of the special size Testkey, where (a) is the case when L is larger, and (b) is the structural change of the testkey corresponding to the larger L. Reducing W to make S ov Keep unchanged, (c) is the case where L cannot be obtained very accurately, (d) is the case where the corresponding L cannot be obtained very accurately, and the actual L is used to replace it during fitting; Fig.10 This is a partial Testkey layout file used to characterize the gate oxide quality near the side wall, including (a) testkey when finger=1 (bulk), (b) testkey when finger=5, (c) testkey when finger=10, (d) testkey when finger=10, and (e) a single testkey after connecting to the pad; Fig.11 is the V-ramp test process, including (a) V-ramp test program flow chart, (b) step signal applied during V-ramp test, (c) graph of gate leakage current changing with time during test; Fig.12 The TDDB CVS test process includes (a) the TDDB test procedure flow and (b) the stress variation with time diagram. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0020] In the field of semiconductor manufacturing, the lifetime estimated by the TDDB test method is the lifetime of the entire gate oxide, and it is difficult to estimate the lifetime of the local gate oxide. In addition, using a bulk structure will make it difficult to effectively eliminate the potential impact of the gate oxide on the experimental results under a large poly area. Although the Transistor Array can qualitatively evaluate the gate oxide quality at the gate edge, it is difficult to estimate the lifetime of the local gate oxide. ov The gate oxide outside still occupies a larger area, and because the transistor array size is small, the correlation between the gate edge and the gate oxide quality in the obtained data is weak. Therefore, the existing technology has a technical gap in the reliability assessment of the partial gate oxide near the sidewall, and cannot solve the problem of calculating the life of the local gate oxide.

[0021] Based on this, the embodiment of the present invention provides a reliability assessment method and system for a sidewall gate oxide process and its electronic device, through which the technical gap in the reliability assessment of the partial gate oxide near the sidewall can be filled. The method of the present invention enables the test to capture the change in the gate oxide quality in the critical area of ​​the sidewall edge, which is crucial to improving the overall reliability of semiconductor devices. This improvement in local sensitivity is not obvious, because it breaks through the limitations of traditional overall assessment and provides the possibility for accurately locating and improving reliability problems. Based on the life estimation method, the present invention is equipped with a series of Testkeys with different finger numbers and gate widths, so that they are strongly correlated with the gate oxide quality near the sidewall. The enhancement of this inherent correlation makes the test results more reflective of the device performance under actual working conditions. The present invention solves the problem that the key local gate oxide cannot be evaluated in the existing TDDB test, and provides a new perspective and method for the reliability assessment of semiconductor devices. With the increasing demand for local reliability assessment, the present invention helps to promote the reliability assessment system to a higher precision and more comprehensive progress.

[0022] The embodiment of the present invention provides a novel reliability evaluation method for a sidewall gate oxide process, specifically: In the TDDB test structure, the gate length of a single finger is adjusted by increasing or decreasing the number of fingers, and then a reliability test is performed to obtain the TDDB test result; in the process of adjusting the gate length of a single finger, the total area S of the gate needs to be ensured. poly The total effective gate length L is unchanged eff become smaller; Use the gate length L of a single finger as the horizontal axis and the TDDB test result as the vertical axis to perform data fitting; extrapolate the TDDB test result corresponding to when L approaches zero, and use the TDDB test result as the overlap area S of the LDD region and the gate. ov TDDB lifetime; Using the gate length L of a single finger as the horizontal axis, the logarithm of the gate leakage current lg (I g ) as the ordinate to perform data fitting; extrapolate the corresponding gate leakage current logarithm lg (I g ), and the gate leakage current logarithm is used as the leakage current value between the lower source and drain near the side wall and the gate to characterize the quality of the gate oxide layer.

[0023] The present invention also provides a reliability evaluation system for a sidewall gate oxide process for implementing the method, comprising: The reliability test module is responsible for performing reliability test on the TDDB test structure after adjusting the gate length of a single finger and obtaining the TDDB test result; The TDDB lifetime calculation module for the overlapping area between the LDD region and the gate is responsible for fitting the data using the gate length L of a single finger as the horizontal coordinate and the TDDB test result as the vertical coordinate; extrapolating the TDDB test result corresponding to when L approaches zero, and using the TDDB test result as the overlapping area S between the LDD region and the gate. ov TDDB lifetime; The gate oxide quality calculation module between the lower source and drain near the side wall is responsible for using the gate length L of a single finger as the horizontal coordinate and the gate leakage current logarithm lg (I g ) as the ordinate to perform data fitting; extrapolate the corresponding gate leakage current logarithm lg (I g ), and the gate leakage current logarithm is used as the leakage current value between the lower source and drain near the side wall and the gate to characterize the quality of the gate oxide layer.

[0024] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0025] Embodiment 1: Prepare a set of N-type and P-type transistor array samples with different numbers of fingers (N) such as Figure 5 (a)-5(d), where the gate width W = 5um. Keep the total gate area S poly (S poly= The gate width W×gate length L×number of fingers N) remains unchanged, and the gate length of a single finger is adjusted by increasing or decreasing the number of fingers.

[0026] By reducing the gate length L and increasing the number of ploys, the total area between the gate and the substrate capacitor remains unchanged. As the number of gates increases, the total length L remains unchanged, but the total L eff (effective gate length) becomes smaller, such as Figure 6 As shown in (e)-(f).

[0027] The geometric dimensions of the capacitor structure between the gate and S / D (source / drain) are relatively fixed during the manufacturing process. As N increases, the total L eff It tends to zero more and more, and can better characterize the gate oxide between the gate and S / D.

[0028] Gate oxide reliability test (GOI) and time-dependent breakdown (TDDB) test were performed on each sample, and V-ramp test was performed to record the leakage current (I g ) data. Apply stress voltage to perform CVS test, record TDDB time data under stress conditions, and extrapolate 125℃ and 1.1V OP TDDB life (denoted as T 0.1% ), the calculated TDDB T 0.1% The leakage current data is organized into the following form:

[0029] L and T 0.1% : Calculate L, where L is the gate length of a single finger, S poly is the total gate area. For each number of fingers (N), L and T 0.1% Similarly, L and the logarithm of the leakage current lg(I g ) to form another data set. Using L as the horizontal axis, T 0.1% As the ordinate, the data is fitted. Common fitting methods are linear fitting or exponential fitting. Extrapolate T when L approaches zero 0.1% Value, i.e. L eff TDDB lifetime T when (effective gate length) approaches zero 0.1% , can be obtained by observing the y-intercept (L=0), see Figure 7 .

[0030] L and lg(I g ): Use L as the horizontal axis, lg(I g ) as the ordinate to perform data fitting. Common fitting methods are also linear fitting or exponential fitting. Extrapolate the logarithm of the leakage current lg (I g ), obtained by observing the y-intercept (L=0), see Figure 8 .

[0031] L obtained by data fitting and extrapolation eff The TDDB lifetime approaches zero. This value reflects the lifetime of the gate oxide layer between the lower S / D and the gate near the sidewall. The L eff The logarithmic change of the leakage current when it approaches zero is normalized by N to lg(l g ), and obtain the S / D and gate leakage current.

[0032] In addition to the above four sizes of devices with L=5, 1, 0.5, and 0.25, there are also devices with L=0.28, 0.35, 0.6, and 15. For these devices, it is not possible to poly = divisible by 25 (N is not an integer), you can use Fig. 9 (a)-(d) Methods. The principles to be followed are: ① Ensure that the overlap area S of L and LDD region-gate of all devices under test is ov Become the same functional relationship to ensure the accuracy of the data to be fitted, S ov =W×L ov (See Figure 6 (a),L ov is the length where the source drain intersects the gate); ② and S poly =25 unchanged, because as the area increases, the TDDB lifetime decreases. L and S ov Inversely proportional relationship, such as Figure 6 As shown in (a)-(d).

[0033] Embodiment 2: 1. Draw the layout like Fig.10 (a)-(d) are four types of MOSCAP and transistor arrytestkeys with L=5, L=1, L=0.5, and L=0.25. There are two types, P-type and N-type, and both are 1.2V devices.

[0034] The TDDB test is performed by applying voltage to the gate while grounding the source / drain and body. The G (Gate), S / D (Source / Drain) and B (Bulk) pads are connected to the SMU (Source Measure Unit) respectively. Fig.10 (e) shows one of the devices.

[0035] The following process is performed according to JEDEC standards: 2. Conduct GOI test to obtain I g and V bd V-ramp test process see Fig.11 (a)-(c): 1) First perform a pre-test to test the output voltage V use is applied to the capacitor and the oxide layer leakage current I is measured at the operating voltage of the corresponding component. use If I use Greater than the set breakdown current I bd , then the capacitor is considered to have initial failure.

[0036] 2) If I use Less than I bd , then start the ramp test, the voltage from V use It starts to ramp up at a uniform pace until oxide breakdown is detected or the set maximum voltage V is reached. max stop.

[0037] 3) Finally, pass the post-test (also called V use ) is used to verify whether the oxide layer is broken down.

[0038] 3. Perform TDDB test TDDB CVS test process: The same voltage stress is applied to the test keys with different structures at 125°C. The TDDB is tested using the constant voltage method (CVS). Fig.12 (a)-(b) show:

[0039] 1) Apply a voltage on the gate for a duration of t int Constant compressive stress V stress , and monitor the gate current; 2) Interrupt stress and apply stress induced leakage current (SILC) measurement voltage V on the gate SILC , waiting time t wait After that, record the gate current I SILC .

[0040] 3) Repeat steps 1 and 2 until the breakdown criterion is reached.

[0041] 4) After the test, sweep the gate voltage to V meas , and measure the gate current; When a sudden increase in gate current or an increase in low voltage stress induced leakage current (SILC) is detected during CVS, it is considered a breakdown and the corresponding time is recorded.

[0042] After the test is completed, the breakdown time under different testkey structure conditions is obtained. Through the above process, the reliability of MOSFET under different stress conditions can be systematically evaluated and its life under actual working conditions can be extrapolated.

[0043] IV. TDDB Lifetime Extrapolation According to the breakdown time of the sample, the failure time T when the cumulative failure rate is 63.5% is extrapolated by Weibull distribution. 63% Then, use T 63% Fit the E model (anode hole injection model) to obtain the electric field acceleration factor. Extrapolate the E model to obtain the lifetime at an operating voltage of 1.1V. Fit all extrapolated lifetimes according to the Weibull distribution and calculate the lifetime when the cumulative failure rate is 0.1%. Finally, combined with the area scaling factor, the TDDB lifetime under a specific area is obtained, which is the final TBBD lifetime T 0.1% .

[0044] 4. Extrapolating gate oxide lifetime under S / D Different TDDB lifetime / leakage current logarithmic data are used as y-axis data, L as x-axis data, and the TDDB lifetime or lg(I g ) is fitted and the gate oxide characteristics between S / D and the gate (under the sidewall) are extrapolated.

[0045] An embodiment of the present invention provides an electronic device. Specifically, the electronic device includes a memory and a processor. The memory stores executable code. When the processor executes the executable code, the method described in any one of the implementation modes is implemented.

[0046] The memory may include high-speed random access memory (RAM), and may also include non-volatile memory (Non-volatile Memory), such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0047] The bus may be an ISA bus, a PCI bus or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0048] Among them, the memory is used to store the program, and the processor executes the program after receiving the execution instruction. The method executed by the device for flow process definition disclosed in any embodiment of the above-mentioned embodiment of the present invention can be applied to the processor or implemented by the processor.

[0049] The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0050] The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the methods described in the previous method embodiments. The specific implementation can be referred to the previous method embodiments, which will not be repeated here.

[0051] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0052] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A new reliability evaluation method for sidewall gate oxide process, characterized in that The method is specifically: Adjust the gate length L of a single finger in the TDDB test structure, and then perform a reliability test to obtain the TDDB test result; Use the gate length L of a single finger as the horizontal axis and the TDDB test result as the vertical axis to perform data fitting; extrapolate the TDDB test result corresponding to when L approaches zero, and use the TDDB test result as the overlap area S of the LDD region and the gate. ov TDDB lifetime; Using the gate length L of a single finger as the horizontal axis, the logarithm of the gate leakage current lg (I g ) as the ordinate to perform data fitting; extrapolate the corresponding gate leakage current logarithm lg (I g ), and the gate leakage current logarithm is used as the leakage current value between the lower source and drain near the side wall and the gate to characterize the quality of the gate oxide layer.

2. The method according to claim 1, characterized in that The gate length of a single finger is adjusted by increasing or decreasing the number of fingers.

3. The method according to claim 1, characterized in that When adjusting the gate length of a single finger, the total gate area S must be guaranteed. poly The total effective gate length L is unchanged eff Become smaller.

4. A reliability evaluation system for a sidewall gate oxide process implementing the method according to any one of claims 1 to 3, characterized in that include: The reliability test module is responsible for performing reliability test on the TDDB test structure after adjusting the gate length of a single finger and obtaining the TDDB test result; The TDDB lifetime calculation module for the overlapping area between the LDD region and the gate is responsible for fitting the data using the gate length L of a single finger as the horizontal coordinate and the TDDB test result as the vertical coordinate; extrapolating the TDDB test result corresponding to when L approaches zero, and using the TDDB test result as the overlapping area S between the LDD region and the gate. ov TDDB lifetime; The gate oxide quality calculation module between the lower source and drain near the side wall is responsible for using the gate length L of a single finger as the horizontal coordinate and the gate leakage current logarithm lg (I g ) as the ordinate to perform data fitting; extrapolate the corresponding gate leakage current logarithm lg (I g ), and the gate leakage current logarithm is used as the leakage current value between the lower source and drain near the side wall and the gate to characterize the quality of the gate oxide layer.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method according to any one of claims 1 to 3 is implemented.

6. A machine-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 3 is implemented.

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