Three-dimensional memory and manufacturing method thereof
By using three-dimensional structure conductive bumps in the memory as the lower electrode and the continuous coverage storage layer, the problem of reducing the effective area of the traditional two-dimensional memory and high manufacturing difficulty is solved, the storage performance and manufacturing yield are improved, and the use is extended life.
Patent Information
- Application Number
- CN202411441049.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-10
AI Technical Summary
The effective area of the memory in traditional two-dimensional structures is reduced after the size is reduced, which limits the improvement of storage performance. At the same time, the manufacturing process of TiN materials is high, which increases manufacturing cost and difficulty.
By adopting a three-dimensional memory manufacturing method, by forming a conductive bump as a lower electrode on the first dielectric layer, and continuously covering the side wall and top surface of the conductive bump, increasing the polarization area, simplifying the manufacturing process, and reducing manufacturing costs.
Increase the polarization area of the storage structure under the same plane area, improve storage performance, simplify manufacturing processes, improve manufacturing yield, extend service life, and improve the sensitivity and reliability of the storage structure.
Smart Images
Figure CN119300360A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a manufacturing method thereof. Background Art
[0002] Phase change memory or ferroelectric memory (FeRAM) and other memories are devices that integrate memory cells (Cells) in the back end of line (BEOL), and are structures in which the memory cells are inserted between two adjacent metal layers. The memory cell is generally composed of an upper and lower electrode layer and a ferroelectric memory layer in the middle. The storage performance of the ferroelectric memory is proportional to the effective area of the ferroelectric memory layer and the electrode layer in the memory cell. The traditional two-dimensional structure memory is composed of a vertically stacked upper electrode layer, a lower electrode layer, and a ferroelectric material layer or a phase change material layer located between the upper electrode layer and the lower electrode layer. However, as the size of the memory continues to shrink, the effective area of the storage structure in the traditional two-dimensional structure memory continues to shrink, thereby limiting the further improvement of the memory performance. Moreover, the upper electrode and lower electrode materials in the traditional storage structure are mostly TiN materials. When the storage structure performs operations such as reading and writing, the TiN material needs to be polarized, for example, from a cubic lattice to an oblique cubic lattice. In order to ensure the storage performance of the storage structure, the manufacturing process of the TiN material is required to be high, thereby increasing the difficulty and manufacturing cost of the memory manufacturing process.
[0003] Therefore, how to increase the effective area of the storage structure while reducing the difficulty and manufacturing cost of the storage structure manufacturing process, thereby improving the performance and manufacturing yield of the memory, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a three-dimensional memory and a manufacturing method thereof, which are used to increase the effective area of the memory structure while reducing the difficulty and manufacturing cost of the memory structure manufacturing process, thereby improving the performance and manufacturing yield of the memory.
[0005] According to some embodiments, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps:
[0006] Forming a substrate, the substrate comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, the substrate comprising a top surface and a bottom surface that are relatively distributed, and the first direction perpendicularly intersects with the top surface of the substrate;
[0007] Depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive bump electrically connected to the first contact structure, and using the conductive bump as a lower electrode;
[0008] forming a storage layer that continuously covers the sidewalls and top surface of the conductive bump;
[0009] A second metal material or a polysilicon material is deposited on the substrate to form an upper electrode covering the storage layer. The lower electrode, the storage layer and the upper electrode together constitute a storage structure.
[0010] In some embodiments, the specific steps of forming the substrate include:
[0011] Providing a substrate, wherein the substrate includes an active region, and the substrate includes a top surface and a bottom surface that are relatively distributed;
[0012] forming a first dielectric layer on the top surface of the substrate;
[0013] The first contact structure is formed along a first direction penetrating the first dielectric layer and electrically connected to the active region in the substrate, wherein the first direction intersects perpendicularly with the top surface of the substrate.
[0014] In some embodiments, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction, the substrate includes a first contact structure penetrating the first dielectric layer and electrically connected to the drain region and a second contact structure penetrating the first dielectric layer and electrically connected to the source region, and the second direction is parallel to the top surface of the substrate; depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive bump electrically connected to the first contact structure, and using the conductive bump as a lower electrode, the specific steps include:
[0015] A first metal material or a polysilicon material is deposited on the first dielectric layer to form two conductive bumps electrically connected to the first contact structure and the second contact structure one by one, and each conductive bump is used as a lower electrode.
[0016] In some embodiments, the specific steps of depositing a first metal material or a polysilicon material on the first dielectric layer to form two conductive bumps electrically connected to the first contact structure and the second contact structure include:
[0017] Depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive layer continuously covering the first dielectric layer, the first contact structure and the second contact structure;
[0018] The conductive layer is planarized by a chemical mechanical polishing process;
[0019] The conductive layer is etched to form two conductive bumps electrically connected to the first contact structure and the second contact structure one by one.
[0020] In some embodiments, the substrate includes a plurality of storage units arranged along the second direction, the storage unit includes the active area and the first contact structure and the second contact structure electrically connected to the active area; the specific steps of forming a storage layer that continuously covers the sidewalls and top surfaces of the conductive bumps include:
[0021] Phase change material or ferroelectric material is deposited on the substrate to form the storage layer which continuously covers the top surface of the first dielectric layer and the sidewalls and top surfaces of the conductive bumps in the plurality of storage cells.
[0022] In some embodiments, after depositing a second metal material or a polysilicon material on the substrate to form an upper electrode covering the storage layer, the following steps are further included:
[0023] At least the memory layer and the upper electrode between adjacent memory cells are removed.
[0024] In some embodiments, the storage layer in the storage unit continuously covers the two conductive bumps, and the upper electrode continuously covers the storage layer on the surfaces of the two conductive bumps; after forming the upper electrode covering the storage layer, the following steps are further included:
[0025] A lead-out structure is formed above the substrate and electrically connected to the upper electrode.
[0026] In some embodiments, the first metal material and the second metal material are both metal tungsten.
[0027] According to some other embodiments, the present invention further provides a three-dimensional memory, comprising:
[0028] A base, comprising a substrate, a first dielectric layer located above the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, wherein the substrate comprises a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly;
[0029] A storage structure is located on the first dielectric layer along the first direction, the storage structure includes a lower electrode, a storage layer and an upper electrode, the lower electrode is a conductive bump located on the first dielectric layer and electrically connected to the first contact structure, the storage layer continuously covers the sidewalls and top surfaces of the conductive bump, the material of the lower electrode is a first metal material or a polysilicon material, and the material of the upper electrode is a second metal material or a polysilicon material.
[0030] In some embodiments, the substrate includes a plurality of memory cells arranged along a second direction, the memory cells include an active region, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along the second direction, the memory cells include a first contact structure penetrating the first dielectric layer and electrically connected to the drain region, and a second contact structure penetrating the first dielectric layer and electrically connected to the source region, and the second direction is parallel to the top surface of the substrate;
[0031] The storage unit further includes two conductive bumps electrically connected to the first contact structure and the second contact structure in a one-to-one correspondence.
[0032] In some embodiments, the memory cell further includes the memory layer continuously covering sidewalls and top surfaces of the two conductive bumps and the upper electrode of the memory layer continuously covering surfaces of the two conductive bumps.
[0033] In some embodiments, the first metal material and the second metal material are both metal tungsten.
[0034] The three-dimensional memory and its manufacturing method provided by the present invention use the conductive bump located on the top surface of the first dielectric layer as the lower electrode of the storage structure, and make the storage layer continuously cover the side wall and top surface of the conductive bump, so that the polarization area of the storage structure is increased under the same plane area, so that the storage structure can store more polarized charges under the same voltage, thereby forming a memory of a three-dimensional structure and effectively improving the storage performance of the three-dimensional memory. At the same time, the present invention uses the conductive bump as the lower electrode, and does not need to perform the etching process of the storage hole, which simplifies the manufacturing process of the three-dimensional memory and improves the manufacturing yield of the three-dimensional memory. Moreover, the present invention sets the material of the lower electrode to the first metal material or polysilicon material, and sets the material of the upper electrode to the second metal material or polysilicon material, which not only increases the etching selectivity when the lead-out hole is subsequently formed, thereby avoiding damage to the storage structure when the lead-out hole is formed, but also can greatly improve the sensitivity, stability and reliability of the storage structure, and prolong the service life of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 is a flow chart of a method for manufacturing a three-dimensional memory in a specific embodiment of the present invention;
[0036] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;
[0037] Figure 3 is a schematic diagram of the structure after a conductive layer is formed in a specific embodiment of the present invention;
[0038] Figure 4 is a schematic diagram of the structure after the conductive bump is formed in a specific embodiment of the present invention;
[0039] Figure 5 is a schematic diagram of the structure after forming a storage layer and an upper electrode in a specific embodiment of the present invention;
[0040] Figure 6 is a schematic diagram of the structure after adjacent storage units are separated in a specific implementation manner of the present invention;
[0041] Figure 7 is a schematic diagram of the structure after the second dielectric layer and the third dielectric layer are formed in a specific embodiment of the present invention;
[0042] Figure 8 is a schematic diagram of a structure after a lead-out structure is formed in a specific embodiment of the present invention;
[0043] Fig. 9 It is a schematic diagram of the structure after the conductive connection pad is formed in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0044] The specific implementation of the three-dimensional memory and the manufacturing method thereof provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0045] This specific embodiment provides a method for manufacturing a three-dimensional memory. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the three-dimensional memory comprises the following steps:
[0046] Step S11, forming a base, the base comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, the substrate comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly;
[0047] Step S12, depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive bump electrically connected to the first contact structure, and using the conductive bump as a lower electrode;
[0048] Step S13, forming a storage layer that continuously covers the sidewalls and top surface of the conductive bump;
[0049] Step S14, depositing a second metal material or a polysilicon material on the substrate to form an upper electrode covering the storage layer, wherein the lower electrode, the storage layer and the upper electrode together constitute a storage structure.
[0050] Figure 2Schematic diagram of the structure of the substrate in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the substrate include:
[0051] Providing a substrate 20, wherein the substrate 20 includes an active region, and the substrate 20 includes a top surface and a bottom surface that are relatively distributed;
[0052] forming a first dielectric layer 21 on the top surface of the substrate 20;
[0053] The first contact structure 25 is formed along a first direction D1 that penetrates the first dielectric layer 21 and is electrically connected to the active region in the substrate 20. The first direction D1 intersects the top surface of the substrate 20 perpendicularly. Figure 2 shown.
[0054] Figure 3 is a schematic diagram of the structure after the conductive layer is formed in a specific embodiment of the present invention, Figure 4 : is a schematic diagram of the structure after the conductive bump is formed in a specific embodiment of the present invention. In some embodiments, the active area includes a channel area and a source area and a drain area located on opposite sides of the channel area along the second direction D2, the substrate includes the first contact structure 25 that penetrates the first dielectric layer 21 and is electrically connected to the drain area, and the second contact structure 26 that penetrates the first dielectric layer 21 and is electrically connected to the source area, and the second direction is parallel to the top surface of the substrate; depositing a first metal material or a polysilicon material on the first dielectric layer 21 to form a conductive bump 40 that is electrically connected to the first contact structure 25, and using the conductive bump 40 as the lower electrode. The specific steps include:
[0055] A first metal material or a polysilicon material is deposited on the first dielectric layer 21 to form two conductive bumps 40 electrically connected to the first contact structure 25 and the second contact structure 26, and each conductive bump 40 is used as a lower electrode. Figure 4 shown.
[0056] In some embodiments, the specific steps of depositing a first metal material or a polysilicon material on the first dielectric layer 21 to form two conductive bumps 40 electrically connected to the first contact structure 25 and the second contact structure 26 include:
[0057] A first metal material or a polysilicon material is deposited on the first dielectric layer 21 to form a conductive layer 30 that continuously covers the first dielectric layer 21, the first contact structure 25, and the second contact structure 26. Figure 3 As shown;
[0058] The conductive layer 30 is planarized by chemical mechanical polishing process;
[0059] The conductive layer 30 is etched to form two conductive bumps 40 electrically connected to the first contact structure 25 and the second contact structure 26 .
[0060] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. The substrate 20 at least includes a plurality of active regions spaced apart along the second direction D2 and a shallow trench isolation region between adjacent active regions. The active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along the second direction D2. The base also includes a gate structure located on the substrate 20, the gate structure including a gate dielectric layer 22 located above the channel region, a gate conductive layer 23 covering the surface of the gate dielectric layer 22, and an isolation sidewall 24 covering the sidewalls of the gate dielectric layer 22 and the sidewalls of the gate conductive layer 23, as shown in FIG. Figure 2 As shown. The first dielectric layer 21 covers the top surface of the substrate 20 and the gate structure. The material of the first dielectric layer 21 can be an oxide material, such as silicon dioxide. In one example, the first contact structure 25 penetrates the first dielectric layer 21 along the first direction D1 and is electrically connected to the drain region, and the second contact structure 26 penetrates the first dielectric layer 21 along the first direction D1 and is electrically connected to the source region.
[0061] The first metal material or polysilicon material may be deposited on the top surface of the first dielectric layer 21 by an atomic layer deposition process to form the conductive layer 30 covering the first dielectric layer 21. Figure 3 As shown. The conductive layer 30 is planarized by a chemical mechanical polishing process, and the conductive layer 30 is reduced to a desired thickness. Then, a hard mask material such as silicon oxynitride is deposited on the conductive layer 30 to form a first mask layer. The first mask layer is patterned to form a first etching window exposing the conductive layer 30. The conductive layer 30 is etched downward along the first etching window to form at least two independent conductive bumps 40, and the two conductive bumps 40 are electrically connected to the first contact structure 25 and the second contact structure 26 in a one-to-one correspondence, as shown. Figure 4In one example, the width of the conductive bump 40 (e.g., the width of the conductive bump 40 along the second direction D2) is greater than the width of the first contact structure 25 (e.g., the width of the first contact structure 25 along the second direction D2) and greater than the width of the second contact structure 26 (e.g., the width of the second contact structure 26 along the second direction D2), thereby ensuring a stable electrical connection between the conductive bump 40 and the first contact structure 25 and the second contact structure 26, and further increasing the area of the lower electrode to further improve the storage capacity of the storage structure formed subsequently.
[0062] Figure 5 is a schematic diagram of the structure after forming the storage layer and the upper electrode in a specific embodiment of the present invention. In some embodiments, the substrate includes a plurality of storage cells arranged along the second direction D2, and the storage cells include the active area and the first contact structure 25 and the second contact structure 26 electrically connected to the active area; the specific steps of forming the storage layer 50 that continuously covers the sidewall and top surface of the conductive bump 40 include:
[0063] A phase change material or a ferroelectric material is deposited on the substrate to form the storage layer 50 which continuously covers the top surface of the first dielectric layer 21 and the sidewalls and top surfaces of the conductive bumps 40 in the plurality of storage cells.
[0064] Figure 6 Schematic diagram of the structure after separating adjacent storage units in a specific embodiment of the present invention. In some embodiments, after depositing a second metal material or polysilicon material on the substrate to form an upper electrode 51 covering the storage layer 50, the following steps are also included:
[0065] At least the storage layer 50 and the upper electrode 51 between adjacent storage cells are removed. Figure 6 shown.
[0066] For example, the substrate includes a plurality of memory cells arranged along the second direction D2, and each of the memory cells includes the active region and the first contact structure 25 and the second contact structure 26 electrically connected to the active region. After forming the conductive bump 40 electrically connected to the first contact structure 25 and the second contact structure 26 in each of the memory cells, a phase change material or a ferroelectric material is deposited on the substrate to form the memory layer 50 that continuously covers the top surface of the first dielectric layer 21 and the sidewalls and top surfaces of the conductive bumps 40 in the plurality of memory cells. Next, a second metal material or a polysilicon material is deposited on the substrate to form the upper electrode 51 that continuously covers the entire memory layer 50, as shown in FIG. Figure 5As shown. Next, a hard mask material such as silicon oxynitride is deposited on the substrate to form a second mask layer 52 covering the upper electrode 51. The second mask layer 52 is patterned to form a second etching window exposing the upper electrode 51. The upper electrode 51 and the storage layer 50 are etched downward along the second etching window to form an opening 60 that penetrates the upper electrode 51 and the storage layer 50 along the first direction D1 and exposes the first dielectric layer 21, and the connection between the storage structures in the adjacent storage cells is disconnected through the opening 60, as shown. Figure 6 After the opening 60 is formed, the storage structure in each of the storage cells includes the two conductive bumps 40 electrically connected to the first contact structure 25 and the second contact structure 26, respectively, the storage layer 50 continuously covering the sidewalls and top surfaces of the two conductive bumps 40, and the upper electrode 51 of the storage layer 50 continuously covering the surfaces of the two conductive bumps 40 (see Figure 6 ) to form a storage unit with a 2T2C structure, thereby further expanding the function of the three-dimensional memory and expanding the application field of the three-dimensional memory.
[0067] Figure 7 is a schematic diagram of the structure after the second dielectric layer and the third dielectric layer are formed in a specific embodiment of the present invention, Figure 8 is a schematic diagram of a structure after a lead-out structure is formed in a specific embodiment of the present invention, Fig. 9 1 is a schematic diagram of the structure after the conductive connection pad is formed in a specific embodiment of the present invention. In some embodiments, the storage layer 50 in the storage unit continuously covers the two conductive bumps 40, and the upper electrode 51 continuously covers the storage layer 50 on the surface of the two conductive bumps 40; after the upper electrode 51 covering the storage layer 50 is formed, the following steps are also included:
[0068] A lead-out structure 80 is formed above the substrate and electrically connected to the upper electrode 50 .
[0069] For example, a silicon nitride material is deposited on the substrate to form a second dielectric layer 70 that continuously covers the top surface of the first dielectric layer 21 and the upper electrode 51. Next, a silicon dioxide material is deposited on the substrate to form a third dielectric layer 71 that covers the second dielectric layer 70. Figure 7As shown. A hard mask material such as silicon oxynitride is deposited on the substrate to form a third mask layer 72 covering the third dielectric layer 71. The third mask layer 72 is patterned to form a third etching window exposing the third dielectric layer 71. The third dielectric layer 71 and the second dielectric layer 70 are etched downward along the third etching window to form an extraction hole exposing the upper electrode 51. A metal material is deposited into the extraction hole to form an extraction structure 80 electrically connected to the upper electrode 51, as shown. Figure 8 Afterwards, a conductive material such as copper metal is deposited on the third dielectric layer 71 to form a conductive connection pad 90 electrically connected to the lead-out structure 80, as shown in FIG. Fig. 9 As shown. Since the upper electrode 51 continuously covers the storage layer 50 on the surfaces of the two conductive bumps 40, it can not only expand the process window for forming the lead-out hole, further simplify the manufacturing process of the three-dimensional memory, but also increase the distance between the lead-out hole and the storage layer 50 along the first direction D1 by setting the projection of the lead-out hole between the two conductive bumps 40, thereby further avoiding damage to the storage layer 50 caused by the process of etching to form the lead-out hole, thereby ensuring the performance stability of the storage structure.
[0070] In some embodiments, the first metal material and the second metal material are both metal tungsten, so that the process of forming the lead-out hole can be further avoided from causing damage to the storage structure by increasing the etching selectivity, and the sensitivity, stability and reliability of the storage structure can be greatly improved, and the service life of the three-dimensional memory can be extended.
[0071] This specific embodiment also provides a three-dimensional memory. The structural schematic diagram of the three-dimensional memory provided in this specific embodiment can be seen in Fig. 9 The three-dimensional memory provided in this specific embodiment can be used as follows Figure 1-Figure 9 The three-dimensional memory is formed by the manufacturing method shown in FIG. Figure 1-Figure 9 As shown, the three-dimensional memory includes:
[0072] A base, comprising a substrate 20, a first dielectric layer 21 located above the substrate 20, and a first contact structure 25 penetrating the first dielectric layer 21 along a first direction D1, wherein the substrate 20 comprises a top surface and a bottom surface that are relatively distributed, and the first direction D1 intersects the top surface of the substrate 20 vertically;
[0073] A storage structure is located on the first dielectric layer 21 along the first direction D1, and the storage structure includes a lower electrode, a storage layer 50 and an upper electrode 51. The lower electrode is a conductive bump 40 located on the first dielectric layer 21 and electrically connected to the first contact structure 25. The storage layer 50 continuously covers the side wall and top surface of the conductive bump 40. The material of the lower electrode is a first metal material or a polysilicon material, and the material of the upper electrode 51 is a second metal material or a polysilicon material.
[0074] This specific embodiment adopts the conductive bump 40 as the lower electrode, and makes the storage layer continuously cover the side wall and top surface of the conductive bump, so that the polarization area of the storage structure is increased under the same plane area, so that the storage structure can store more polarization charges under the same voltage, thereby forming a three-dimensional structure memory and effectively improving the storage performance of the three-dimensional memory. At the same time, by adopting the first metal material or polysilicon material as the material of the lower electrode, and using the second metal material or polysilicon material as the material of the upper electrode 51, the damage to the storage structure caused by the process of forming the lead-out structure can be reduced, so as to simplify the manufacturing process of the three-dimensional memory, and can greatly improve the sensitivity, stability and reliability of the storage structure, and extend the service life of the three-dimensional memory.
[0075] In order to form a 2T2C structure to further expand the function of the three-dimensional memory and expand the application field of the three-dimensional memory, in some embodiments, the substrate includes a plurality of memory cells arranged along a second direction D2, the memory cell includes an active region, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along the second direction D2, the memory cell includes a first contact structure 25 that penetrates the first dielectric layer 21 and is electrically connected to the drain region, and a second contact structure 26 that penetrates the first dielectric layer 21 and is electrically connected to the source region, and the second direction D2 is parallel to the top surface of the substrate 20;
[0076] The memory cell further includes two conductive bumps 40 electrically connected to the first contact structure 25 and the second contact structure 26 in a one-to-one correspondence.
[0077] In some embodiments, the memory cell further includes the memory layer 50 continuously covering the sidewalls and top surfaces of the two conductive bumps 40 and the upper electrode 51 of the memory layer 50 continuously covering the surfaces of the two conductive bumps 40 .
[0078] In some embodiments, the first metal material and the second metal material are both metal tungsten.
[0079] The three-dimensional memory and its manufacturing method provided in this specific embodiment use the conductive bump located on the top surface of the first dielectric layer as the lower electrode of the storage structure, and make the storage layer continuously cover the side wall and top surface of the conductive bump, so that the polarization area of the storage structure is increased under the same plane area, so that the storage structure can store more polarized charges under the same voltage, thereby forming a three-dimensional structure memory and effectively improving the storage performance of the three-dimensional memory. At the same time, this specific embodiment uses the conductive bump as the lower electrode, and there is no need to perform the etching process of the storage hole, which simplifies the manufacturing process of the three-dimensional memory and improves the manufacturing yield of the three-dimensional memory. Moreover, this specific embodiment sets the material of the lower electrode to the first metal material or polysilicon material, and sets the material of the upper electrode to the second metal material or polysilicon material, which not only increases the etching selectivity when the lead-out hole is subsequently formed, thereby avoiding damage to the storage structure when the lead-out hole is formed, but also can greatly improve the sensitivity, stability and reliability of the storage structure, and extend the service life of the three-dimensional memory.
[0080] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for manufacturing a three-dimensional memory, characterized in that: The steps include: Forming a substrate, the substrate comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, the substrate comprising a top surface and a bottom surface that are relatively distributed, and the first direction perpendicularly intersects with the top surface of the substrate; Depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive bump electrically connected to the first contact structure, and using the conductive bump as a lower electrode; forming a storage layer that continuously covers the sidewalls and top surface of the conductive bump; A second metal material or a polysilicon material is deposited on the substrate to form an upper electrode covering the storage layer. The lower electrode, the storage layer and the upper electrode together constitute a storage structure.
2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The specific steps of forming the substrate include: Providing a substrate, wherein the substrate includes an active region; forming a first dielectric layer on the top surface of the substrate; A first contact structure is formed that penetrates the first dielectric layer along a first direction and is electrically connected to the active area in the substrate.
3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that: The active region includes a channel region and a source region and a drain region located at opposite sides of the channel region along a second direction, the substrate includes a first contact structure penetrating the first dielectric layer and electrically connected to the drain region and a second contact structure penetrating the first dielectric layer and electrically connected to the source region, and the second direction is parallel to the top surface of the substrate; The specific steps of depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive bump electrically connected to the first contact structure, and using the conductive bump as a lower electrode include: A first metal material or a polysilicon material is deposited on the first dielectric layer to form two conductive bumps electrically connected to the first contact structure and the second contact structure one by one, and each conductive bump is used as a lower electrode.
4. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that: The specific steps of depositing a first metal material or a polysilicon material on the first dielectric layer to form two conductive bumps electrically connected to the first contact structure and the second contact structure include: Depositing a first metal material or a polysilicon material on the first dielectric layer to form a conductive layer continuously covering the first dielectric layer, the first contact structure and the second contact structure; The conductive layer is planarized by a chemical mechanical polishing process; The conductive layer is etched to form two conductive bumps electrically connected to the first contact structure and the second contact structure one by one.
5. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that: The substrate includes a plurality of memory cells arranged along the second direction, wherein the memory cells include the active area and the first contact structure and the second contact structure electrically connected to the active area; The specific steps of forming a storage layer that continuously covers the sidewalls and top surface of the conductive bump include: Phase change material or ferroelectric material is deposited on the substrate to form the storage layer which continuously covers the top surface of the first dielectric layer and the sidewalls and top surfaces of the conductive bumps in the plurality of storage cells.
6. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that: After depositing a second metal material or a polysilicon material on the substrate to form an upper electrode covering the storage layer, the following steps are also included: At least the memory layer and the upper electrode between adjacent memory cells are removed.
7. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that: The storage layer in the storage unit continuously covers the two conductive bumps, and the upper electrode continuously covers the storage layer on the surfaces of the two conductive bumps; after forming the upper electrode covering the storage layer, the following steps are also included: A lead-out structure is formed above the substrate and electrically connected to the upper electrode.
8. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The first metal material and the second metal material are both metal tungsten.
9. A three-dimensional memory, characterized in that: include: A base, comprising a substrate, a first dielectric layer located above the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, wherein the substrate comprises a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly; A storage structure is located on the first dielectric layer along the first direction, the storage structure includes a lower electrode, a storage layer and an upper electrode, the lower electrode is a conductive bump located on the first dielectric layer and electrically connected to the first contact structure, the storage layer continuously covers the sidewalls and top surfaces of the conductive bump, the material of the lower electrode is a first metal material or a polysilicon material, and the material of the upper electrode is a second metal material or a polysilicon material.
10. The three-dimensional memory according to claim 9, characterized in that: The substrate includes a plurality of memory cells arranged along a second direction, the memory cells include an active region, the active region includes a channel region and a source region and a drain region located at opposite sides of the channel region along the second direction, the memory cells include a first contact structure penetrating the first dielectric layer and electrically connected to the drain region, and a second contact structure penetrating the first dielectric layer and electrically connected to the source region, and the second direction is parallel to the top surface of the substrate; The storage unit further includes two conductive bumps electrically connected to the first contact structure and the second contact structure in a one-to-one correspondence.
11. The three-dimensional memory according to claim 10, characterized in that: The memory cell further includes the memory layer continuously covering side walls and top surfaces of the two conductive bumps and the upper electrode of the memory layer continuously covering surfaces of the two conductive bumps.
12. The three-dimensional memory according to claim 9, characterized in that: The first metal material and the second metal material are both metal tungsten.