Power semiconductor preparation method and power semiconductor structure

Abstract

The embodiment of the invention provides a power semiconductor preparation method and a power semiconductor structure, and the semiconductor preparation method comprises the steps: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching to remove the second N-type epitaxial layer in the target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a groove; only epitaxial layers with medium doping concentration are arranged at the upper part and the middle part of the outer side of the outermost groove of the terminal region, so that the space charge region is diffused at the outer side of the outermost terminal groove, the electric field intensity at the position is reduced, and the withstand voltage of the terminal structure is improved; under the condition that the withstand voltage of the terminal is ensured without increasing the thickness of an oxide layer at the bottom of the trench of the separated gate trench MOSFET, the size of a primitive cell is reduced, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The embodiments of the present specification relate to the field of semiconductor technology, and in particular to a method for preparing a power semiconductor and a power semiconductor structure. Background Art

[0002] Split Gate Trench MOSFET (SGT MOS) is particularly suitable for low power consumption power supply systems due to its low on-resistance and high switching speed characteristics.

[0003] In the prior art, a three-layer epitaxy is usually used to form the drift region of the device to optimize the electric field distribution at the bottom of the device cell trench and the drift region between the trenches to achieve low on-resistance and high blocking voltage. In the scheme of forming the drift region by three-layer epitaxy, a middle outer layer with a high impurity concentration is generally set in the middle of the trench to reduce the on-resistance of the drift region, but this will cause the space charge region of the outermost trench of the device terminal structure in the middle high-doping layer area to be compressed, and breakdown will occur when the electric field exceeds the near-breakdown electric field strength. In order to reduce the electric field strength in the middle of the outermost trench of the terminal structure, it is necessary to increase the thickness of the oxide layer at the bottom of the trench of the split-gate trench MOSFET. The scheme of increasing the thickness of the oxide layer will cause the cell size to increase, so that the on-resistance of the device increases, and the conduction loss increases.

[0004] Therefore, a better solution is urgently needed. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a semiconductor manufacturing method. One or more embodiments of this specification also relate to a semiconductor to solve the technical defects existing in the prior art.

[0006] According to a first aspect of an embodiment of this specification, a method for preparing a power semiconductor is provided, comprising:

[0007] Depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; wherein the doping concentration of the first N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer;

[0008] Etching and removing the second N-type epitaxial layer in the target area, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target area; wherein the doping concentration of the third N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer;

[0009] Etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form trenches; wherein the trenches include active area trenches and terminal area trenches;

[0010] A bottom oxide layer is formed in the trench by thermal growth and deposition, polysilicon is deposited on the surface of the bottom oxide layer, and the polysilicon is etched to form a polycrystalline structure;

[0011] Forming an intermediate oxide layer on the polycrystalline structure of the active area trench, forming a gate oxide layer structure on the sidewall of the active area trench, filling polysilicon in the active area trench to form a gate polysilicon structure, and forming a shielding oxide layer on the gate polysilicon structure;

[0012] Performing ion implantation on the third N-type epitaxial layer to form a base region, and annealing the base region, and forming an implantation shielding layer between the active region trench and the terminal region trench; performing ion implantation on the third N-type epitaxial layer to form a source region, and annealing the source region, forming a dielectric oxide layer on the source region, forming a metal electrode contact hole on the dielectric oxide layer, performing contact region implantation and annealing on the metal electrode contact hole, and forming a source electrode, a gate electrode, and a cutoff electrode on the metal electrode contact hole;

[0013] A passivation structure is formed on the electrode structure, and a drain electrode is formed below the silicon substrate.

[0014] In a possible implementation, the doping concentration of the first N-type epitaxial layer ranges from 1.0E15 to 7.5E15 cm -3 ;

[0015] The doping concentration of the second N-type epitaxial layer ranges from 2.0E16 cm to 7.5E16 cm -3 ;

[0016] The doping concentration of the third N-type epitaxial layer ranges from 5.0E16 cm to 2.5E16 cm -3 .

[0017] In a possible implementation, the depth of the groove is 3 to 7 mm;

[0018] The width of the groove is 0.5 to 2.0 mm;

[0019] The thickness of the bottom oxide layer is 0.4 to 0.9 mm;

[0020] The thickness of the middle oxide layer is 0.3 to 0.6 mm;

[0021] The thickness of the gate oxide structure is 0.04 to 0.09 mm;

[0022] The thickness of the shielding oxide layer is 0.05 to 0.1 mm.

[0023] In a possible implementation, ion implantation is performed on the third N-type epitaxial layer to form a base region, and the base region is annealed, including:

[0024] The implantation energy for ion implantation is 60 to 150 KeV, and the implantation dosage is 0.6E13 to 1.5E13;

[0025] The annealing temperature is 1000-1150°C, and the annealing time is 30-120min.

[0026] In a possible implementation, ion implantation is performed on the third N-type epitaxial layer to form a source region, and the source region is annealed to form a dielectric oxide layer on the source region, including:

[0027] The ion implantation is arsenic ion implantation;

[0028] The annealing temperature is 950-1000°C, and the annealing time is 90-120min.

[0029] In a possible implementation, performing contact region implantation and annealing on the metal electrode contact hole includes:

[0030] BF2 is injected into the metal electrode contact hole; the injection energy of BF2 injection is 60-80 KeV, and the injection dose is 3E14-5E14;

[0031] The annealing temperature is 900-1000°C, and the annealing time is 20-30min.

[0032] In a possible implementation, forming a source electrode, a gate electrode, and a cutoff electrode on the metal electrode contact hole includes:

[0033] An AlSiCu metal layer is deposited on the metal electrode contact hole, and a source electrode, a gate electrode and a cutoff electrode are formed by photolithography and etching processes; wherein the thickness of the AlSiCu metal layer is 4 to 6 μm.

[0034] In a possible implementation manner, forming a passivation structure on the electrode structure and forming a drain electrode under the silicon substrate includes:

[0035] Depositing a passivation layer on the electrode structure and forming a passivation structure by photolithography and etching processes;

[0036] A metal layer is evaporated under the silicon substrate to form a drain electrode; wherein the metal layer includes any one of Ti, Ni and Ag.

[0037] According to a second aspect of an embodiment of this specification, there is provided a power semiconductor structure, comprising: a substrate, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer;

[0038] A first epitaxial layer is disposed on a substrate;

[0039] The second epitaxial layer is disposed on the first epitaxial layer, and the width of the second epitaxial layer is smaller than that of the first epitaxial layer;

[0040] A third epitaxial layer is disposed on the first epitaxial layer and the second epitaxial layer;

[0041] Grooves are formed on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer;

[0042] An electrode structure is arranged on the groove.

[0043] In a possible implementation, the trench includes an active region trench and a terminal region trench;

[0044] Active area trenches are opened on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer;

[0045] The termination region trench is opened on the first epitaxial layer and the third epitaxial layer;

[0046] The doping concentration of the first epitaxial layer is lower than the doping concentration of the second epitaxial layer;

[0047] The doping concentration of the third epitaxial layer is higher than the doping concentration of the first epitaxial layer.

[0048] The embodiments of the present specification provide a power semiconductor manufacturing method and a power semiconductor structure, wherein the semiconductor manufacturing method includes: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching and removing the second N-type epitaxial layer in a target area, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and in the target area; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a groove; by only arranging an epitaxial layer with a medium doping concentration on the upper and middle parts of the outer side of the outermost trench in the terminal area, the space charge region is diffused outside the outermost terminal trench, the electric field strength therein is reduced, the terminal structure withstand voltage is improved, and the unit cell size is reduced without increasing the thickness of the oxide layer at the bottom of the trench of the separated gate trench MOSFET to ensure the terminal withstand voltage, thereby reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a flow chart of a method for preparing a power semiconductor provided by one embodiment of this specification;

[0050] Figure 2 It is a first structural schematic diagram of a power semiconductor manufacturing method provided by an embodiment of this specification;

[0051] Figure 3 It is a second structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0052] Figure 4 It is a third structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0053] Figure 5 It is a fourth structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0054] Figure 6 It is a fifth structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0055] Figure 7 It is a sixth structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0056] Figure 8 It is a seventh structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0057] Fig. 9 It is an eighth structural schematic diagram of a method for preparing a power semiconductor provided by an embodiment of this specification;

[0058] Fig.10 It is a schematic diagram of the structure of a semiconductor provided by an embodiment of this specification. DETAILED DESCRIPTION

[0059] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0060] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0061] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0062] First, the terms involved in one or more embodiments of this specification are explained.

[0063] Substrate is the basic material used to support and construct other functional layers in the semiconductor device manufacturing process.

[0064] Epitaxy refers to the process of growing a new single crystal on a single crystal substrate that has been carefully processed by cutting, grinding, polishing, etc. The new single crystal can be made of the same material as the substrate or a different material.

[0065] In this specification, a semiconductor preparation method is provided. This specification also relates to a semiconductor, which is described in detail one by one in the following embodiments.

[0066] See also Figure 1 , Figure 1 A flow chart of a method for preparing a power semiconductor provided according to an embodiment of the present specification is shown, which specifically includes the following steps.

[0067] Step 101: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; wherein the doping concentration of the first N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer.

[0068] In a possible implementation, the doping concentration of the first N-type epitaxial layer ranges from 1.0E15 to 7.5E15 cm -3 ; The doping concentration of the second N-type epitaxial layer ranges from 2.0E16 to 7.5E16 cm -3 .

[0069] In practical applications, see Figure 2 , select an N+ type silicon substrate 1, and sequentially deposit a first N-type epitaxial layer 21 with a low doping concentration and a second N-type epitaxial layer 22 with a high doping concentration on the N+ type silicon substrate; the impurity doping concentration of the first N-type epitaxial layer with a low doping concentration is 1.0E15-7.5E15 cm -3 The impurity doping concentration of the second N-type epitaxial layer with high doping concentration is 2.0E16~7.5E16cm -3 .

[0070] Step 102: etching and removing the second N-type epitaxial layer in the target area, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and in the target area; wherein the doping concentration of the third N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer.

[0071] The doping concentration of the third N-type epitaxial layer ranges from 5.0E16 cm to 2.5E16 cm -3 .

[0072] In practical applications, see Figure 3 , through photolithography pattern definition, using photolithography etching technology, and adopting dry etching process, the second N-type epitaxial layer with high doping concentration in the outer area of ​​the outermost trench of the terminal area is etched away, so that only the first N-type epitaxial layer with low doping concentration is retained in the outer area of ​​the outermost trench of the terminal area; on the second N-type epitaxial layer with high doping concentration on the inner side of the outermost trench of the terminal area and the first N-type epitaxial layer with low doping concentration at the bottom of the trench outside the outermost trench of the terminal area, a third N-type epitaxial layer 23 with medium doping concentration is deposited, and the impurity doping concentration of the third N-type epitaxial layer with medium doping concentration is 5.0E16~2.5E16

[0073] cm -3 .

[0074] The embodiments of this specification use a selective photolithography method to realize different epitaxial layer structures in the inner and outer regions of the outermost trench of the terminal structure, that is, three layers of epitaxy are formed on the inner side of the outermost trench of the terminal area and two layers of epitaxy are formed on the outer side, thereby reducing the electric field strength outside the outermost trench of the terminal structure and improving the blocking voltage of the device terminal structure. It is not necessary to increase the withstand voltage of the terminal structure by increasing the thickness of the oxide layer at the bottom of the trench of the split-gate trench MOSFET primitive cell, and a smaller primitive cell unit size can be achieved, thereby reducing the on-resistance of the device.

[0075] Step 103: etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form trenches; wherein the trenches include active area trenches and terminal area trenches.

[0076] In a possible implementation, the depth of the groove is 3 to 7 mm; the width of the groove is 0.5 to 2.0 mm.

[0077] In practical applications, see Figure 4 The first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer are subjected to photolithography and etching processes to form active region primary cell trenches 31 and terminal region trenches 32 with a depth of 3 to 7 mm and a width of 0.5 to 2.0 mm.

[0078] Step 104: forming a bottom oxide layer in the trench by thermal growth and deposition, depositing polysilicon on the surface of the bottom oxide layer, and etching the polysilicon to form a polycrystalline structure.

[0079] In a possible implementation, the thickness of the bottom oxide layer is 0.4-0.9 mm.

[0080] In practical applications, see Figure 5, a bottom oxide layer 4 with a thickness of 0.4 to 0.9 mm is formed in the groove by thermal growth and deposition processes in sequence; polysilicon is deposited on the surface of the wafer where the bottom oxide layer is formed to fill the groove structure, and the polysilicon in the active area groove is subjected to photolithography and etching processes to form the active area original cell polycrystalline structure 51 and the terminal area polycrystalline structure 52 respectively.

[0081] Step 105: forming an intermediate oxide layer on the polycrystalline structure of the active area trench, forming a gate oxide layer structure on the sidewall of the active area trench, filling polysilicon in the active area trench to form a gate polysilicon structure, and forming a shielding oxide layer on the gate polysilicon structure.

[0082] In a possible implementation, the thickness of the intermediate oxide layer is 0.3-0.6 mm; the thickness of the gate oxide layer structure is 0.04-0.09 mm; and the thickness of the shielding oxide layer is 0.05-0.1 mm.

[0083] In practical applications, see Figure 6 The trench structure is filled again using an oxide layer deposition process to remove excess oxide layer on the silicon surface, and the deposited oxide layer in the active area original cell trench is photolithographically and etched to form an intermediate oxide layer 6 with a thickness of 0.3 to 0.6 mm on the active area original cell polycrystalline structure 51.

[0084] For further information, see Figure 7 , a dry oxygen oxidation process is used to thermally grow an oxide layer on the side wall of the active area cell trench to form a gate oxide layer structure 7 with a thickness of 0.04 to 0.09 mm; then polysilicon deposition is performed to fill the active area cell trench to form a gate polysilicon structure 8; dry oxygen oxidation is performed again to form a shielding oxide layer 9 with a thickness of 0.05 to 0.1 mm on the top of the gate polysilicon.

[0085] Step 106: performing ion implantation on the third N-type epitaxial layer to form a base region, and annealing the base region, forming an implantation shielding layer between the active region trench and the terminal region trench; performing ion implantation on the third N-type epitaxial layer to form a source region, and annealing the source region, forming a dielectric oxide layer on the source region, forming a metal electrode contact hole on the dielectric oxide layer, performing contact region implantation and annealing on the metal electrode contact hole, and forming a source electrode, a gate electrode, and a cutoff electrode on the metal electrode contact hole.

[0086] The cut-off electrode may be a cut-off ring.

[0087] In a possible implementation, ion implantation is performed on the third N-type epitaxial layer to form a base region, and the base region is annealed, including: the implantation energy of the ion implantation is 60-150 KeV, the implantation dosage is 0.6E13-1.5E13; the annealing temperature of the annealing is 1000-1150° C., and the annealing time is 30-120 min.

[0088] In practical applications, see Figure 8 , the silicon surface is globally implanted, the implantation energy is 60~150KeV, the implantation dose is 0.6E13~1.5E13; after completing the P base region 10 ion implantation, the base region implantation is annealed, the annealing temperature is 1000~1150℃, and the annealing time is 30~120min.

[0089] In a possible implementation, ion implantation is performed on the third N-type epitaxial layer to form a source region, and the source region is annealed to form a dielectric oxide layer on the source region, including: the ion implantation is arsenic ion implantation; the annealing temperature is 950-1000° C., and the annealing time is 90-120 minutes.

[0090] In practical applications, see Figure 8 , using a photolithography process, an injection shielding layer is formed between the active area and the outermost terminal trench, and N+ type source region arsenic ions are implanted into the outer side of the active area and the outermost terminal trench; after the source region arsenic ion implantation, annealing is performed, the annealing temperature is 950-1000°C, and the annealing time is 90-120min to form an N+ type source region 11, and a dielectric oxide layer with a thickness of 1.0-1.5mm is deposited on the wafer with the N+ type source region formed.

[0091] In a possible implementation, the metal electrode contact hole is implanted with contact area and annealed, including: BF2 is implanted into the metal electrode contact hole; the BF2 implantation energy is 60-80KeV, the implantation dose is 3E14-5E14; the annealing temperature is 900-1000°C, and the annealing time is 20-30min.

[0092] In practical applications, see Figure 8 After forming the dielectric oxide layer, a metal electrode contact hole is formed on the dielectric oxide layer by a photolithography process; a BF2 injection process is performed in the source electrode contact area through the metal electrode contact hole, and annealing is performed after the injection, wherein the injection energy is 60 to 80 KeV, the injection dose is 3E14 to 5E14, the annealing temperature is 900 to 1000°C, and the annealing time is 20 to 30 minutes.

[0093] In a possible implementation, a source electrode, a gate electrode, and a cutoff electrode are formed on the metal electrode contact hole, including: depositing an AlSiCu metal layer on the metal electrode contact hole, and forming the source electrode, the gate electrode, and the cutoff electrode through photolithography and etching processes; wherein the thickness of the AlSiCu metal layer is 4 to 6 μm.

[0094] For details, see Figure 8An AlSiCu metal layer with a thickness of 4 to 6 μm is deposited on the upper surface of the wafer of the electrode contact hole, and a source electrode 12, a gate electrode 13 and a Ring (cut-off ring) electrode 14 are formed by photolithography and etching processes.

[0095] Step 107: forming a passivation structure on the electrode structure, and forming a drain electrode under the silicon substrate.

[0096] The electrode structure may include a source electrode, a gate electrode and a ring electrode.

[0097] In one possible implementation, a passivation structure is formed on the electrode structure, and a drain electrode is formed under the silicon substrate, including: depositing a passivation layer on the electrode structure, and forming the passivation structure through photolithography and etching processes; evaporating a metal layer under the silicon substrate to form a drain electrode; wherein the metal layer includes any one of Ti, Ni and Ag.

[0098] In practical applications, see Fig. 9 , a passivation layer is deposited on the electrode structure, and a passivation structure 15 is formed by photolithography and etching processes; a Ti / Ni / Ag metal layer is evaporated on the lower surface of the silicon substrate 1 to form a drain electrode 16, completing the preparation of the separated gate trench MOSFET structure.

[0099] The embodiments of the present specification provide a power semiconductor manufacturing method and a power semiconductor structure, wherein the semiconductor manufacturing method includes: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching and removing the second N-type epitaxial layer in a target area, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and in the target area; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a groove; by only arranging an epitaxial layer with a medium doping concentration on the upper and middle parts of the outer side of the outermost trench in the terminal area, the space charge region is diffused outside the outermost terminal trench, the electric field strength therein is reduced, the terminal structure withstand voltage is improved, and the unit cell size is reduced without increasing the thickness of the oxide layer at the bottom of the trench of the separated gate trench MOSFET to ensure the terminal withstand voltage, thereby reducing the on-resistance of the device.

[0100] See also Fig.10 , Fig.10 A structural diagram of a power semiconductor manufacturing method provided according to an embodiment of the present specification is shown, wherein the power semiconductor structure comprises: a semiconductor manufactured by the above semiconductor manufacturing method, specifically comprising a substrate, a first epitaxial layer, a second epitaxial layer and a third epitaxial layer;

[0101] The first epitaxial layer is arranged on the substrate; the second epitaxial layer is arranged on the first epitaxial layer, and the width of the second epitaxial layer is smaller than that of the first epitaxial layer; the third epitaxial layer is arranged on the first epitaxial layer and the second epitaxial layer; grooves are opened on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; and an electrode structure is arranged on the grooves.

[0102] In a possible implementation, the trench includes an active area trench and a terminal area trench; the active area trench is opened on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; the terminal area trench is opened on the first epitaxial layer and the third epitaxial layer; the doping concentration of the first epitaxial layer is lower than the doping concentration of the second epitaxial layer; the doping concentration of the third epitaxial layer is higher than the doping concentration of the first epitaxial layer.

[0103] Specifically, the semiconductor may be a MOSFET semiconductor, see Fig.10 The structure of the MOSFET semiconductor includes a substrate 1, a first epitaxial layer 21, a second epitaxial layer 22, a third epitaxial layer 23, an active region cell trench 31, a terminal region trench 32, a bottom oxide layer 4, a polycrystalline structure 5, an intermediate oxide layer 6, a gate oxide layer 7, a gate polysilicon structure 8, a base region 10, a source region 11, a source electrode 12, a gate electrode 13, a cut-off electrode 14, a passivation structure 15 and a drain electrode 16.

[0104] The polycrystalline structure 5 includes an active region unit cell polycrystalline structure and a terminal region polycrystalline structure. The active region unit cell polycrystalline structure is arranged in the active region unit cell trench 31 , and the terminal region polycrystalline structure is arranged in the terminal region trench 32 .

[0105] Compared with the existing SGT MOS structure that uses a three-layer epitaxial process to form a drift region: the structure of the separated gate trench MOSFET of the present invention forms a low-doping concentration epitaxial layer at the bottom of the trench and a high-doping concentration epitaxial layer in the middle of the trench on the surface of the substrate wafer, and then, through photolithography pattern definition, photolithography etching technology is used to remove the high-doping concentration epitaxial layer in the middle of the trench in the outermost area of ​​the device terminal region by dry etching, so that only the low-doping concentration epitaxial layer at the bottom of the trench is retained in the outermost area of ​​the terminal region; then, a medium-doping concentration epitaxial layer is deposited on the high-doping concentration epitaxial layer in the middle of the trench on the inner side of the outermost trench in the terminal region and the low-doping concentration epitaxial layer at the bottom of the trench on the outer side of the outermost trench in the terminal region, so that the device forms three-layer and two-layer epitaxial layer drift regions on the inner and outer sides of the outermost trench in the terminal region, respectively.

[0106] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0107] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, according to the content of the embodiments of this specification, many modifications and changes can be made. It is also possible to continue to add multiple epitaxial layers on the third epitaxial layer, and remove the redundant epitaxial layers in the target area by etching. Structurally, it is necessary to keep the drift zone of the two epitaxial layers outside the outermost trench of the terminal area, which can reduce the electric field strength here, improve the withstand voltage of the terminal structure, reduce the size of the unit cell, and reduce the on-resistance of the device.

[0109] The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present specification, so that those skilled in the art can well understand and use the present specification. The present specification is limited only by the claims and their full scope and equivalents.

Claims

1. A method for preparing a power semiconductor, characterized in that: include: Depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; wherein the doping concentration of the first N-type epitaxial layer is lower than the doping concentration of the second N-type epitaxial layer; Etching and removing the second N-type epitaxial layer in the target area, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target area; wherein the doping concentration of the third N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer; Etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form trenches; wherein the trenches include active area trenches and terminal area trenches; forming a bottom oxide layer in the trench by thermal growth and deposition, depositing polysilicon on the surface of the bottom oxide layer, and etching the polysilicon to form a polycrystalline structure; Forming an intermediate oxide layer on the polycrystalline structure of the active area trench, forming a gate oxide layer structure on the sidewall of the active area trench, filling polysilicon in the active area trench to form a gate polysilicon structure, and forming a shielding oxide layer on the gate polysilicon structure; Performing ion implantation on the third N-type epitaxial layer to form a base region, and annealing the base region, and forming an implantation shielding layer between the active region trench and the terminal region trench; performing ion implantation on the third N-type epitaxial layer to form a source region, and annealing the source region, forming a dielectric oxide layer on the source region, forming a metal electrode contact hole on the dielectric oxide layer, performing contact region implantation and annealing on the metal electrode contact hole, and forming a source electrode, a gate electrode, and a cutoff electrode on the metal electrode contact hole; A passivation structure is formed on the electrode structure, and a drain electrode is formed under the silicon substrate.

2. The method according to claim 1, characterized in that The doping concentration of the first N-type epitaxial layer is in the range of 1.0E15 to 7.5E15 cm -3 ; The doping concentration of the second N-type epitaxial layer is in the range of 2.0E16 to 7.5E16 cm -3 ; The doping concentration of the third N-type epitaxial layer is in the range of 5.0E16 to 2.5E16 cm -3 .

3. The method according to claim 1, characterized in that The depth of the groove is 3 to 7 mm; The width of the groove is 0.5 to 2.0 mm; The thickness of the bottom oxide layer is 0.4 to 0.9 mm; The thickness of the intermediate oxide layer is 0.3 to 0.6 mm; The thickness of the gate oxide layer structure is 0.04 to 0.09 mm; The thickness of the shielding oxide layer is 0.05 to 0.1 mm.

4. The method according to claim 1, characterized in that: Performing ion implantation on the third N-type epitaxial layer to form a base region, and annealing the base region, comprising: The ion implantation energy is 60-150 KeV, and the implantation dosage is 0.6E13-1.5E13; The annealing temperature of the annealing is 1000-1150° C., and the annealing time is 30-120 minutes.

5. The method according to claim 1, characterized in that Performing ion implantation on the third N-type epitaxial layer to form a source region, and annealing the source region to form a dielectric oxide layer on the source region, including: The ion implantation is arsenic ion implantation; The annealing temperature of the annealing is 950-1000° C., and the annealing time is 90-120 minutes.

6. The method according to claim 1, characterized in that Performing contact region implantation and annealing on the metal electrode contact hole comprises: BF2 is injected into the metal electrode contact hole; the injection energy of the BF2 injection is 60-80 KeV, and the injection dose is 3E14-5E14; The annealing temperature of the annealing is 900-1000° C., and the annealing time is 20-30 minutes.

7. The method according to claim 1, characterized in that Forming a source electrode, a gate electrode and a cutoff electrode on the metal electrode contact hole, comprising: An AlSiCu metal layer is deposited on the metal electrode contact hole, and a source electrode, a gate electrode and a cutoff electrode are formed by photolithography and etching processes; wherein the thickness of the AlSiCu metal layer is 4-6 μm.

8. The method according to claim 1, characterized in that Forming a passivation structure on the electrode structure and forming a drain electrode under the silicon substrate, comprising: Depositing a passivation layer on the electrode structure and forming a passivation structure by photolithography and etching processes; A metal layer is evaporated under the silicon substrate to form a drain electrode; wherein the metal layer includes any one of Ti, Ni and Ag.

9. A power semiconductor structure, characterized in that: include: A substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer; The first epitaxial layer is disposed on the substrate; The second epitaxial layer is disposed on the first epitaxial layer, and a width of the second epitaxial layer is smaller than that of the first epitaxial layer; The third epitaxial layer is disposed on the first epitaxial layer and the second epitaxial layer; A groove is formed on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; An electrode structure is arranged on the groove.

10. The power semiconductor structure according to claim 9, characterized in that: The trenches include active area trenches and terminal area trenches; The active area trench is opened on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; The termination region trench is opened on the first epitaxial layer and the third epitaxial layer; The doping concentration of the first epitaxial layer is lower than the doping concentration of the second epitaxial layer; The doping concentration of the third epitaxial layer is higher than the doping concentration of the first epitaxial layer.

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