An integrated high-performance LDMOS device and its preparation method

Abstract

The invention discloses an integrated high-performance LDMOS device and a preparation method thereof. The invention forms a first polysilicon layer on a second well region, a third well region and one side of an oxide layer, forms a second polysilicon layer on the other side of the oxide layer, forms a resistive field plate between the first polysilicon layer and the second polysilicon layer and arranged at intervals on the oxide layer, and forms an equipotential ring between the resistive field plates. The resistive field plate and the equipotential ring are arranged at intervals between the gate and drain of the LDMOS device. Only a thin silicon dioxide film layer is spaced between the surface of the drift region of the device and the resistive field plate. One side of the resistive field plate is connected to a high potential of the drain, and the source is connected to a minimum potential. When the device is reverse biased, there is a weak leakage current between the source and the drain through the resistive field plate, so that the surface electric field distribution between the gate and the drain of the device is more uniform, the peak electric field near the gate and the drain is greatly weakened, the voltage resistance performance of the device is improved, and the HTRB reliability of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuits, and in particular relates to an integrated high-performance LDMOS device and a preparation method thereof. Background Art

[0002] LDMOS is a power device with a double diffusion structure. This technology involves two injections into the same source / drain region, one with a higher concentration and the other with a lower concentration. After the injection, a high-temperature push process is performed to form a channel with a concentration gradient. The length of the channel is determined by the difference in the distance between the two lateral diffusions. In order to increase the breakdown voltage, there is a drift region between the active region and the drain region. The drift region in LDMOS is the key to the design of this type of device, and the impurity concentration in the drift region is relatively low. When LDMOS is connected to high voltage, it can withstand higher voltages because the drift region is high-resistance. Because LDMOS is compatible with CMOS processes, it has more applications in CMOS circuits. However, ultra-high voltage LDMOS usually refers to LDMOS devices with a withstand voltage of more than 500V. In order to ensure the withstand voltage of the device, it is necessary to carefully design the field plate, the junction depth of the drift region, the size of the drift region, the drift region concentration matching, and many other places to reduce the surface electric field strength of the device. Ultra-high voltage LDMOS tubes can replace traditional discrete high-voltage MOS tubes in integrated circuits and exist in the form of switch tubes in AC-DC circuits. In the field of low-power LED lighting drivers, compared with discrete high-voltage tubes combined with low-voltage CMOS components, it has higher integration, better reliability and lower production costs.

[0003] like Figure 1 It is a typical epitaxial ultra-high voltage LDMOS structure. Due to the presence of a relatively concentrated BP buried layer, the substrate parasitic effect of the epitaxial high voltage LDMOS is relatively weak. When the device is working at a large current, latch-up is not likely to occur. The device has a strong surge resistance. However, compared with the non-epitaxial LDMOS structure, it also has the following weaknesses:

[0004] The HVNW drift region has a shallow junction depth, and the device surface electric field is easily affected by the Si-SiO2 interface charge and the movable charge of the oxide layer, which makes its reverse breakdown voltage unstable; it is difficult to increase the withstand voltage; in order to ensure the increase in withstand voltage, the length of the HVNW drift region has to be lengthened, which greatly increases the size of the device, reduces the device integration, and increases the device manufacturing cost;

[0005] When the device is reverse biased, the electric field distribution on the surface of the drift region of the device is uneven, and there are peak electric fields near the source and drain. The electric fields in these two areas are much higher than the electric fields in the drift region in the middle, and breakdown is more likely to occur prematurely.

[0006] Since the HVNW junction is shallow, it is easily affected by interface charge and movable charge, so that during the use of the device, the reverse breakdown voltage will gradually degrade, the withstand voltage will gradually decrease, and eventually fail; the reliability of the device's HTRB (high temperature reverse bias test) is not as good as the non-epitaxial LDMOS structure in the deep drift region.

[0007] Therefore, there is an urgent need to provide an integrated high-performance LDMOS device and a preparation method thereof to solve the above-mentioned shortcomings of the epitaxial high-voltage LDMOS. Summary of the invention

[0008] In view of this, the present invention provides a method for preparing an integrated high-performance LDMOS device that can reduce the peak electric field on the drain side, improve the LDMOS withstand voltage and device reliability, to solve the above-mentioned technical problems, and specifically adopts the following technical solutions to achieve this.

[0009] In a first aspect, the present invention provides an integrated high-performance LDMOS device, comprising:

[0010] a substrate of a first conductivity type;

[0011] An epitaxial layer of a first conductivity type formed on the substrate, a buried layer of the first conductivity type formed on one side of the epitaxial layer and partially located in the substrate, and a first well region of a second conductivity type formed on the other side of the epitaxial layer and partially located in the substrate;

[0012] a second well region of the first conductivity type formed on the buried layer and connected to the epitaxial layer, a third well region of the second conductivity type formed on the epitaxial layer and the first well region, and a fourth well region of the second conductivity type formed on the first well region and connected to the third well region;

[0013] forming an oxide layer on the third well region and the fourth well region;

[0014] a first implantation region of the first conductivity type, a second implantation region of the second conductivity type, which are located in the second well region and arranged at intervals, and a third implantation region of the second conductivity type, which is formed on the fourth well region and connected to the oxide layer;

[0015] A first polysilicon layer formed on one side of the second well region, the third well region and the oxide layer, a second polysilicon layer formed on the other side of the oxide layer, a resistive field plate located between the first polysilicon layer and the second polysilicon layer and arranged at intervals on the oxide layer, and an equipotential ring formed between the resistive field plates and arranged at intervals on the oxide layer;

[0016] a dielectric layer formed on the second well region, the first polysilicon layer, the resistive field plate, the equipotential ring, the second polysilicon layer, the oxide layer and the third implantation region;

[0017] A first contact hole and a second contact hole penetrating the dielectric layer and respectively located on the first injection region and the second injection region, a third contact hole penetrating the dielectric layer and located on the first polysilicon layer on the oxide layer, a fourth contact hole penetrating the dielectric layer and located on the second polysilicon layer, and a fifth contact hole located on the third injection region;

[0018] A first metal layer is formed in the first contact hole, the second contact hole and located on the dielectric layer, a second metal layer is formed in the third contact hole and located on the dielectric layer, and a third metal layer is formed in the fourth contact hole, the fifth contact hole and located on the dielectric layer.

[0019] As a preferred embodiment of the above technical solution, the first conductivity type is P type, the second conductivity type is N type, and the third well region is a drift region.

[0020] As a preferred embodiment of the above technical solution, the doping concentration of the second well region is greater than the doping concentration of the third well region, and the junction depth of the epitaxial layer is less than the junction depth of the first well region.

[0021] In a second aspect, the present invention further provides a method for preparing an integrated high-performance LDMOS device, comprising the following steps:

[0022] providing a substrate of a first conductivity type;

[0023] forming a first well region of the second conductivity type on one side of the substrate, forming a buried layer of the first conductivity type on the other side of the substrate, and forming an epitaxial layer of the first conductivity type on the substrate between the first well region and the buried layer;

[0024] forming a third well region of the second conductivity type on the epitaxial layer and the first well region, forming a second well region of the first conductivity type connected to the epitaxial layer on the buried layer, a fourth well region of the second conductivity type located on the first well region, and forming an oxide layer on the third well region and the fourth well region;

[0025] Growing polysilicon on the second well region, the third well region, the oxide layer and the fourth well region, and injecting second conductivity type impurities into the polysilicon to form a polysilicon thin film;

[0026] The polysilicon film above the oxide layer is photolithographically processed and second conductive type impurities are implanted to form equipotential rings and resistive field plates arranged at intervals, and the polysilicon on the second well region and the fourth well region is etched to correspondingly form a first polysilicon layer located on the second well region and the oxide layer and a second polysilicon layer located above the fourth well region, the resistive field plate is located between the first polysilicon layer and the second polysilicon layer, and the equipotential rings are located between the resistive field plates;

[0027] Performing first conductive type ion implantation and second conductive type ion implantation into the second well region respectively to form a first implantation region and a second implantation region located in the second well region and arranged at intervals, and implanting second conductive type ions into the fourth well region to form a third implantation region connected to the oxide layer;

[0028] Forming a dielectric layer on the second well region, the first polysilicon layer, the resistive field plate, the equipotential ring, the second polysilicon layer, the oxide layer and the third injection region, and performing photolithography on the first injection region, the second injection region, the first polysilicon layer on the oxide layer, the second polysilicon layer, and the dielectric layer corresponding to the third injection region to form a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole, respectively;

[0029] A first metal layer is formed on the dielectric layer in the first contact hole, the second contact hole and above the second well region, a second metal layer is formed on the third contact hole and the dielectric layer corresponding to the third contact hole, and a third metal layer is formed on the dielectric layer in the fourth contact hole, the fifth contact hole and above the fourth well region.

[0030] As a preferred embodiment of the above technical solution, the first conductivity type is P type, the second conductivity type is N type, the second conductivity type impurities and the second conductivity type ions both include N type phosphorus or arsenic, and the first conductivity type ions include boron or aluminum.

[0031] As a preferred embodiment of the above technical solution, the thickness of the oxide layer is 100~500Å, and the thickness of the polysilicon film is 3000~5000Å.

[0032] As a preferred embodiment of the above technical solution, photolithography and implantation of second conductivity type impurities into the polysilicon film above the oxide layer include:

[0033] Firstly, second conductivity type impurities are injected into the polysilicon for the first time, and thermal annealing is performed to form a polysilicon thin film;

[0034] The polysilicon film above the oxide layer is subjected to photolithography and second-conductivity-type impurities are implanted for a second time to form the equipotential ring and the resistive field plate.

[0035] As a preferred embodiment of the above technical solution, the first implantation dose of the second conductive type impurity is between 1E12 and 2E13, the annealing temperature for preparing the polycrystalline silicon film is between 800 and 1100°C, the time is between 20 and 120s, and the square resistance of the polycrystalline silicon film after annealing is above 100Mohm.

[0036] As a preferred embodiment of the above technical solution, the second implantation dosage of the second conductive type impurity is between 5E15-2E16, the square resistance of the equipotential ring is between 10-30ohm, and the square resistance of the resistive field plate is between 100M-1Gohm.

[0037] As a preferred embodiment of the above technical solution, the resistivities of the first polysilicon layer, the equipotential ring and the second polysilicon layer are equal, and the third well region is a drift region.

[0038] The present invention provides an integrated high-performance LDMOS device and a preparation method thereof. The first polysilicon layer is formed on a second well region, a third well region and one side of an oxide layer, the second polysilicon layer is formed on the other side of the oxide layer, a resistive field plate is formed between the first polysilicon layer and the second polysilicon layer and arranged at intervals on the oxide layer, and an equipotential ring is formed between the resistive field plates and arranged at intervals on the oxide layer. The resistive field plate and the equipotential ring are arranged at intervals between the gate and drain of the LDMOS device. Only a thin silicon dioxide film layer is spaced between the surface of the drift region of the device and the resistive field plate. One side of the resistive field plate is connected to a high potential of the drain, and the source is connected to a minimum potential. When the device is reverse biased, there is a weak leakage current between the source and the drain through the resistive field plate, so that the surface electric field distribution between the gate and the drain of the device is more uniform, and the peak electric field near the gate and the drain can be greatly weakened, thereby greatly improving the withstand voltage performance and withstand voltage stability of the device, and also improving the HTRB reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 This is a schematic diagram of the current typical epitaxial ultra-high voltage LDMOS structure;

[0041] Figure 2 The integrated high-performance LDMOS device provided by the present invention is from A to Schematic cross-sectional view of ;

[0042] Figure 3 A schematic diagram of the planar layout of the integrated high-performance LDMOS device provided by the present invention;

[0043] Figure 4 A flow chart of a method for preparing an integrated high-performance LDMOS device provided by the present invention;

[0044] Figure 5 A functional area distribution diagram on the polysilicon corresponding to the gate electrode and the drain electrode provided by the present invention;

[0045] Figure 6 A potential distribution diagram of a polysilicon thin film provided by the present invention;

[0046] Figures 7 to 11 A diagram of the preparation process of the integrated high-performance LDMOS device provided by the present invention.

[0047] The main component symbols are described as follows:

[0048] 1-integrated high-performance LDMOS device; 10-substrate; 11-epitaxial layer; 12-buried layer; 13-first well region; 14-second well region; 15-third well region; 16-fourth well region; 20-oxide layer; 21-first injection region; 22-second injection region; 23-third injection region; 30-first polysilicon layer; 31-second polysilicon layer; 32-resistive field plate; 33-equipotential ring; 40-dielectric layer; 41-first contact hole; 42-second contact hole; 43-third contact hole; 44-fourth contact hole; 45-fifth contact hole; 50-first metal layer; 51-second metal layer; 52-third metal layer. DETAILED DESCRIPTION

[0049] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0050] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may also be a centered element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a centered element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0051] In order to solve the above problems, the present invention provides a new non-epitaxial LDMOS structure, in which a resistive field plate and an equipotential ring are arranged between the gate and drain of the LDMOS, so that the surface electric field between the gate and drain of the device is distributed more evenly, which can greatly weaken the peak electric field near the gate and the drain, thereby greatly improving the withstand voltage of the device and the withstand voltage stability of the device. In addition, the HTRB reliability of the device is improved, solving the shortcomings of the above-mentioned epitaxial high-voltage LDMOS.

[0052] See also Figure 2 and Figure 3 The present invention provides an integrated high-performance LDMOS device 1, comprising:

[0053] A substrate 10 of a first conductivity type;

[0054] An epitaxial layer 11 of a first conductivity type formed on the substrate 10, a buried layer 12 of a first conductivity type formed on one side of the epitaxial layer 11 and partially located in the substrate 10, and a first well region 13 of a second conductivity type formed on the other side of the epitaxial layer 11 and partially located in the substrate 10;

[0055] a second well region 14 of the first conductivity type formed on the buried layer 12 and connected to the epitaxial layer 11, a third well region 15 of the second conductivity type formed on the epitaxial layer 11 and the first well region 13, and a fourth well region 16 of the second conductivity type formed on the first well region 13 and connected to the third well region 15;

[0056] An oxide layer 20 formed on the third well region 15 and the fourth well region 16;

[0057] A first implantation region 21 of the first conductivity type, a second implantation region 22 of the second conductivity type, which are located in the second well region 14 and are arranged at intervals, and a third implantation region 23 of the second conductivity type, which is formed on the fourth well region 16 and connected to the oxide layer 20;

[0058] A first polysilicon layer 30 formed on one side of the second well region 14, the third well region 15 and the oxide layer 20, a second polysilicon layer 31 formed on the other side of the oxide layer 20, a resistive field plate 32 located between the first polysilicon layer 30 and the second polysilicon layer 31 and arranged at intervals on the oxide layer 20, and an equipotential ring 33 formed between the resistive field plates 32 and arranged at intervals on the oxide layer 20;

[0059] A dielectric layer 40 formed on the second well region 14, the first polysilicon layer 30, the resistive field plate 32, the equipotential ring 33, the second polysilicon layer 31, the oxide layer 20 and the third implantation region 23;

[0060] A first contact hole 41 and a second contact hole 42 penetrating the dielectric layer 40 and respectively located on the first injection region 21 and the second injection region 22, a third contact hole 43 penetrating the dielectric layer 40 and located on the first polysilicon layer 30 on the oxide layer 20, a fourth contact hole 44 penetrating the dielectric layer 40 and located on the second polysilicon layer 31, and a fifth contact hole 45 located on the third injection region 23;

[0061] A first metal layer 50 is formed in the first contact hole 41, the second contact hole 42 and located on the dielectric layer 40, a second metal layer 51 is formed in the third contact hole 43 and located on the dielectric layer 40, and a third metal layer 52 is formed in the fourth contact hole 44, the fifth contact hole 45 and located on the dielectric layer 40.

[0062] In this embodiment, the first conductivity type is P type, the second conductivity type is N type, the third well region 15 is a drift region, the doping concentration of the second well region 14 is greater than the doping concentration of the third well region 15, the junction depth of the epitaxial layer 11 is less than the junction depth of the first well region 13, and the buried layer 12 is a layer of specific material embedded in the semiconductor material to change or increase the characteristics and performance of the semiconductor device. It can not only provide an effective isolation layer, adjust the band structure and increase the electron mobility, but also provide certain improvements and enhancements for the stability, reliability and adaptability to the working environment of the semiconductor device. It has a wide range of applications and can be used in the preparation of various types of semiconductor devices. It plays an important role in promoting the development and application of semiconductor technology. In other words, the buried layer 12 has an important influence on the performance of semiconductor devices. By rationally designing and selecting the buried layer material, the resistance and capacitance can be reduced, the thermal characteristics can be improved, the isolation performance can be improved, and the field effect and electron mobility can be optimized. Figure 1 As shown, Psub represents a substrate of the first conductivity type, i.e., P substrate; DNW represents a deep well region of the second conductivity type, i.e., a deep N well; BP represents a buried layer of the first conductivity type, i.e., a P buried layer; PW represents a well region of the first conductivity type, i.e., a P well; P+ represents an injection region of the first conductivity type, i.e., a P+ injection region; N+ represents an injection region of the second conductivity type, i.e., an N+ injection region; ILD represents a dielectric layer; HVNW represents a well region of the second conductivity type, i.e., an N well, and the junction depth of the drift region is shallow. The first metal layer is the LDMOS source and the first metal layer is connected to the body region. A PN junction is formed between the LDMOS source and the body region. This PN junction is equivalent to a diode, i.e., a body diode. The PN junction is composed of a first injection region and a second injection region of different conductivity types in the second well region; the second metal layer is the LDMOS gate, and the third metal layer is the LDMOS drain.

[0063] It should be noted that in the resistive field plate technology, there is only a thin silicon dioxide film layer between the surface of the drift region of the device and the resistive field plate, and one side of the resistive field plate is connected to the high potential of the drain, and the source is connected to the lowest potential. When the device is reverse biased, there is a weak leakage current (usually at the microampere level) between the source and the drain through the resistive field plate. Because the current-voltage curve of the resistive field plate presents a linear resistance characteristic, the uniformly distributed electric field in the resistive field plate can make the electric field of the entire drift region of the device uniformly distributed, which not only reduces the peak electric field on the surface, but also increases the lateral electric field in the middle of the drift region, thereby increasing the breakdown voltage of the device. In semiconductor technology, the most common resistive field plate is made of semi-insulating polycrystalline silicon. During the growth of polycrystalline silicon, a certain amount of oxygen is introduced so that the polycrystalline silicon contains a certain amount of silicon dioxide, thereby obtaining semi-insulating electrical properties. Usually, the square resistance of this semi-insulating film can reach more than 100Mohm. HVNW is an HV LDMOS device with a biased gate structure and a drift region in which the source region is formed by boron-phosphorus double diffusion. Different high voltage (high voltage N-well) drift regions can be obtained by changing the length, width, junction depth and doping concentration of the drift region.

[0064] In addition, if Figure 3 As shown in the figure, the entire drift region between the drain and the source is covered by polysilicon, with the drain inside and the source and body region outside. Due to the difference in electrical properties, polysilicon is They respectively constitute the gate, resistive field plate, equipotential ring, resistive field plate, equipotential ring, resistive field plate, and drain field plate. Among them, the drift region is located between the source and the drain. When it is turned on, the current mainly flows in the channel; but when the MOS tube is turned off, due to the accumulation of charge, a reverse bias voltage will be generated in the drift region; this reverse bias voltage will cause electrons to flow from the source to the drift region, and finally reach a dynamic equilibrium state; the main function of the drift region is that when the MOS tube is turned off, the drift region carries most of the charge and helps maintain the reverse bias voltage of the MOS tube. HTRB (High Temperature Reverse Bias) means high temperature reverse bias test, which is the most important test item for the reliability of discrete devices, that is, when a certain specification of reverse voltage is continuously supplied at high temperature and operated for a long time, the reverse leakage current of the tested sample is required to be stable within the range value, simulating the tolerance of the device under long-term operating conditions to infer the life and stress size of the device in actual use.

[0065] It should be understood that the equipotential rings 33 and the resistive field plates 32 are alternately arranged at intervals, so that the electric field distribution in the resistive field plate 32 area between the equipotential rings 33 is completely uniform, and the electric field of the resistive field plate 32 itself can have a positive impact on the surface electric field of the drift region below. Compared with the traditional epitaxial LDMOS structure, the main difference lies in the difference in polysilicon and the difference in metal field plates, so that the polysilicon is continuous from the gate to the source, and different areas and functions are formed according to the huge difference in square resistance. By forming a first polysilicon layer 30 on one side of the second well region 14, the third well region 15 and the oxide layer 20, forming a second polysilicon layer 31 on the other side of the oxide layer 20, forming a resistive field plate 32 between the first polysilicon layer 30 and the second polysilicon layer 31 and arranged at intervals on the oxide layer 20, and forming equipotential rings 33 between the resistive field plates 32 and arranged at intervals on the oxide layer 20, that is, the resistive field plates 32 and the equipotential rings 33 are arranged at intervals between the gate and the drain of the integrated high-performance LDMOS device 1, the device There is only a thin silicon dioxide film layer between the surface of the drift region and the resistive field plate 32, and one side of the resistive field plate 32 is connected to the high potential of the drain, and the source is connected to the lowest potential. When the device is reverse biased, there is a weak leakage current between the source and the drain through the resistive field plate 32, which makes the surface electric field distribution between the gate and the drain of the device more uniform, and can greatly weaken the peak electric field near the gate and the drain, thereby greatly improving the voltage resistance performance and voltage resistance stability of the device, and also improving the HTRB reliability of the device.

[0066] See also Figure 4 The present invention also provides a method for preparing an integrated high-performance LDMOS device, comprising the following steps:

[0067] S1: providing a substrate 10 of a first conductivity type;

[0068] In this embodiment, the material of the substrate 10 can be silicon or germanium. High-purity silicon is selected as the material of the substrate 10, which is easy to implement and can also reduce the manufacturing cost.

[0069] S2: forming a first well region 13 of the second conductivity type on one side of the substrate 10, forming a buried layer 12 of the first conductivity type on the other side of the substrate 10, and forming an epitaxial layer 11 of the first conductivity type on the substrate 10 between the first well region 13 and the buried layer 12;

[0070] In this embodiment, semiconductors can generally be divided into intrinsic semiconductors, N-type semiconductors and P-type semiconductors, which represent no impurity doping, doping with N-type impurities and doping with P-type impurities, respectively. If a P-type region is diffused on an N-type substrate, it is a P-well region, and if an N-type region is diffused on a P-type substrate, it is an N-well region. The first conductivity type is P-type, and the second conductivity type is N-type, that is, an N-type first well region is made on a P-type substrate, and a P-type buried layer is formed on the other side of the substrate 10, and a P-type epitaxial layer is formed on the substrate 10 between the first well region 13 and the buried layer 12. Epitaxial growth includes low-pressure homoepitaxial growth and heteroepitaxial growth. Low-pressure homoepitaxial growth refers to the process of growing a single crystal thin film on a single crystal substrate according to the crystal orientation of the substrate. The grown epitaxial layer and the substrate are made of the same material, and the process is simple but the cost is high. The thin film material of heteroepitaxial growth is completely different from the epitaxial layer of the substrate. The corresponding process is called heteroepitaxial growth. This type of process is complex and has a low cost. An epitaxial layer of a certain thickness that meets the requirements can be obtained, which is convenient for subsequent preparation processes.

[0071] S3: forming a third well region 15 of the second conductivity type on the epitaxial layer 11 and the first well region 13, forming a second well region 14 of the first conductivity type connected to the epitaxial layer 11 on the buried layer 12, a fourth well region 16 of the second conductivity type located on the first well region 13, and forming an oxide layer 20 on the third well region 15 and the fourth well region 16;

[0072] In this embodiment, refer to Figure 7 and Figure 1 , as with the conventional epitaxial LDMOS process, firstly, a photolithography implantation is made on a P-type substrate to form a DNW, then a photolithography implantation is made to form a BP, and then a P-type epitaxial layer P-EPI is grown; then, a HVNW drift region, a low-voltage NW and a PW are made on the P-type epitaxial layer; then, a field oxide layer FOX is formed in the drift region on the surface of the wafer, and an extremely thin gate oxide layer is grown in the region outside the FOX. The oxide layer 20 is usually between 100 and 500 Å thick, wherein the first well region 13 is a DNW, the second well region 14 is a PW, the third well region 15 is a HVNW drift region, and the fourth well region 16 is a NW. The first well region 13 has the function of isolating noise and being more voltage-resistant. Since the gate oxide layer is too thin, it is not shown in the cross-sectional view.

[0073] S4: growing polysilicon on the second well region 14, the third well region 15, the oxide layer 20 and the fourth well region 16, and injecting second conductivity type impurities into the polysilicon to form a polysilicon thin film;

[0074] In this embodiment, refer to Figure 8, undoped polysilicon is deposited on the surface of the wafer, and ultra-high resistance implantation and annealing are performed on the polysilicon film. Polysilicon is grown using LPCVD (Low Pressure Chemical Vapor Deposition). The thickness of the polysilicon film is usually between 3000 and 5000Å. At this time, there are no impurities in the polysilicon and it is non-conductive and insulated. Among them, in chip manufacturing, low-pressure chemical vapor deposition (LPCVD) is widely used to create various thin films, which have different uses. LPCVD can be used to deposit silicon oxide and silicon nitride, and can also be used to make doped films to change the conductivity of silicon.

[0075] S5: performing photolithography on the polysilicon film above the oxide layer 20 and implanting second conductive type impurities to form spaced equipotential rings 33 and resistive field plates 32, and etching the polysilicon on the second well region 14 and the fourth well region 16 to correspondingly form a first polysilicon layer 30 located on the second well region 14 and the oxide layer 20, and a second polysilicon layer 31 located above the fourth well region 16, the resistive field plate 32 is located between the first polysilicon layer 30 and the second polysilicon layer 31, and the equipotential rings 33 are located between the resistive field plates 32;

[0076] In this embodiment, refer to Fig. 9 and Fig.10 , performing photolithography on the polysilicon film above the oxide layer 20 and injecting second conductive type impurities, including: first injecting second conductive type impurities into the polysilicon for the first time, and performing thermal annealing to form a polysilicon film; performing photolithography on the polysilicon film above the oxide layer 20 and injecting second conductive type impurities for a second time to form the equipotential ring 33 and the resistive field plate 32. The first implantation dose of the second conductive type impurity is between 1E12 and 2E13, the annealing temperature for preparing the polysilicon film is between 800 and 1100°C, the time is between 20 and 120s, and the sheet resistance of the polysilicon film after annealing is above 100Mohm; the second implantation dose of the second conductive type impurity is between 5E15 and 2E16, the sheet resistance of the equipotential ring 33 is between 10 and 30ohm, the sheet resistance of the resistive field plate 32 is between 100M and 1Gohm, and the resistivities of the first polysilicon layer 30, the equipotential ring 33 and the second polysilicon layer 31 are equal.

[0077] It should be noted that the element injected into the ultra-high resistance is an N-type impurity, usually P or As, and the injection dose is usually between 1E12-2E13. The injection dose here must not be too large, otherwise the polysilicon resistance will drop rapidly. The annealing temperature is between 800~1100℃, and the time is between 20S-120S; after annealing, the polysilicon thin film block resistance can reach more than 100Mohm. Low-resistance area lithography and low-resistance injection, except for the ultra-high resistance area to be retained, all other areas of polysilicon are heavily doped, and the doping element is an N-type impurity, usually P or As, and the injection dose is usually between 5E15-2E16; after the injection is completed, the block resistance of the low-resistance area is usually between 10-30ohm. After that, polysilicon etching is carried out. The polysilicon in the drain area above PW and on the left is etched, and the polysilicon in other areas is completely retained. In this way, a polycrystalline thin film structure of staggered low-resistance, high-resistance, low-resistance, and high-resistance stepped resistive field plates and equipotential rings is completed, which balances the electric field in the LDMOS drift region and improves the LDMOS voltage resistance and device reliability.

[0078] S6: performing first conductive type ion implantation and second conductive type ion implantation into the second well region 14 to form a first implantation region 21 and a second implantation region 22 located in the second well region 14 and arranged at intervals, and implanting second conductive type ions into the fourth well region 16 to form a third implantation region 23 connected to the oxide layer 20;

[0079] In this embodiment, refer to Fig.11 , with the same conventional process, the first injection region 21 and the second injection region 22 of different conductivity types are formed in the second well region 14 by using photolithography technology. The first injection region 21 is a P+ region, that is, BF2 is injected to form the P+ contact of the body region of the device, and the second injection region 22 is an N+ region, that is, As is injected to form the N+ contact of the source and drain of the LDMOS. Similarly, the third injection region 23 is formed in the fourth well region 16 by using photolithography technology. The third injection region 23 is an N+ region, that is, the N+ contact of the drain, and the third injection region 23 is connected to the oxide layer 20. The oxide layer 20 is a gate oxide layer, which can effectively suppress the short channel effect and maintain a good subthreshold slope. The thickness of the gate oxide layer should decrease at the same ratio as the channel length. Among them, the junction depths of the first injection region 21, the second injection region 22 and the third injection region 23 can be the same.

[0080] S7: forming a dielectric layer 40 on the second well region 14, the first polysilicon layer 30, the resistive field plate 32, the equipotential ring 33, the second polysilicon layer 31, the oxide layer 20 and the third injection region 23, and performing photolithography on the first polysilicon layer 30, the second polysilicon layer 31 and the dielectric layer 40 corresponding to the third injection region 23 located on the first injection region 21, the second injection region 22 and the oxide layer 20 to form a first contact hole 41, a second contact hole 42, a third contact hole 43, a fourth contact hole 44 and a fifth contact hole 45;

[0081] In this embodiment, a dielectric layer 40 is grown on the surface of the wafer, and then a plurality of contact holes are formed on the dielectric layer 40. The dielectric layer 40 covers the second well region 14, the first polysilicon layer 30, the resistive field plate 32, the equipotential ring 33, the second polysilicon layer 31, the oxide layer 20 and the third injection region 23. The first contact hole 41, the second contact hole 42, the third contact hole 43, the fourth contact hole 44 and the fifth contact hole 45 are formed on the first injection region 21, the second injection region 22, the first polysilicon layer 30 on the oxide layer 20, the second polysilicon layer 31 and the third injection region 23 by using photolithography technology to facilitate subsequent metal filling.

[0082] S8: Form a first metal layer 50 on the dielectric layer 40 in the first contact hole 41, the second contact hole 42 and above the second well region 14, form a second metal layer 51 on the third contact hole 43 and the dielectric layer 40 corresponding to the third contact hole 43, and form a third metal layer 52 on the dielectric layer 40 in the fourth contact hole 44, the fifth contact hole 45 and above the fourth well region 16.

[0083] In this embodiment, the first conductivity type is P type, the second conductivity type is N type, the second conductivity type impurities and the second conductivity type ions both include N type phosphorus or arsenic, and the first conductivity type ions include boron or aluminum. The metal is filled in each contact hole by magnetron sputtering technology, that is, the metal is filled in the first contact hole 41 and the second contact hole 42, and the metal is covered on the dielectric layer 40 above the first contact hole 41 and the second contact hole 42 to form a "π"-shaped first metal layer 50, and the metal is filled in the third contact hole 43 and the dielectric layer 40 above the third contact hole 43 is covered with the metal to form a "T"-shaped second metal layer 51. Similarly, the metal is filled in the fourth contact hole 44 and the fifth contact hole 45, and the metal is covered on the dielectric layer 40 above the fourth contact hole 44 and the fifth contact hole 45 to form a " The first metal layer 50 is the LDMOS source connection region, which is recorded as LDMOS source & body, the second metal layer 51 is the LDMOS gate of the device, which is recorded as LDMOS gate, and the third metal layer 52 is the drain of the device, which is recorded as LDMOS drain.

[0084] It should be noted that, again, Figure 5 and Figure 6 , low-resistance polysilicon gate: consistent with the traditional process, extending to the top of the field oxide layer to form a gate field plate, which can significantly reduce the peak electric field at the bird's mouth on the left side of the field oxide layer; forming "resistance field plate à equipotential ring à resistance field plate à equipotential ring...", forming a stepped potential distribution in a cycle; drain end low-resistance field plate: the equipotential ring 33 and the first polysilicon layer 30, i.e., the low-resistance polysilicon gate, have the same resistivity, and the drain metal and the second polysilicon layer 31 form a drain field plate, i.e., a drain end low-resistance field plate, which can reduce the peak electric field at the edge of the drain NW. Among them, the equipotential ring 33 is also called a low-resistance equipotential field ring, the oxide layer 20 is also called a field oxide layer or a gate oxide layer, D represents the drain, G represents the gate, and S represents the source.

[0085] It should be understood that after forming multiple contact holes, metal is used to fill each contact hole and form each electrode of LDMOS. What is different from the traditional process here is that a contact hole, namely the fourth contact hole 44, needs to be led out on the rightmost side of the polysilicon to short-circuit the drain of LDMOS. In this way, the low-resistance region on the right side of the polysilicon and the drain metal extending to the left together constitute the drain field plate of LDMOS, which can effectively reduce the peak electric field on the drain side and also improve the voltage resistance and reliability of the device.

[0086] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0087] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0088] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An integrated high-performance LDMOS device, characterized in that: include: a substrate of a first conductivity type; An epitaxial layer of a first conductivity type formed on the substrate, a buried layer of the first conductivity type formed on one side of the epitaxial layer and partially located in the substrate, and a first well region of a second conductivity type formed on the other side of the epitaxial layer and partially located in the substrate; a second well region of the first conductivity type formed on the buried layer and connected to the epitaxial layer, a third well region of the second conductivity type formed on the epitaxial layer and the first well region, and a fourth well region of the second conductivity type formed on the first well region and connected to the third well region; forming an oxide layer on the third well region and the fourth well region; a first implantation region of the first conductivity type, a second implantation region of the second conductivity type, which are located in the second well region and arranged at intervals, and a third implantation region of the second conductivity type, which is formed on the fourth well region and connected to the oxide layer; A first polysilicon layer formed on one side of the second well region, the third well region and the oxide layer, a second polysilicon layer formed on the other side of the oxide layer, a resistive field plate located between the first polysilicon layer and the second polysilicon layer and arranged at intervals on the oxide layer, and an equipotential ring formed between the resistive field plates and arranged at intervals on the oxide layer; a dielectric layer formed on the second well region, the first polysilicon layer, the resistive field plate, the equipotential ring, the second polysilicon layer, the oxide layer and the third implantation region; A first contact hole and a second contact hole penetrating the dielectric layer and respectively located on the first injection region and the second injection region, a third contact hole penetrating the dielectric layer and located on the first polysilicon layer on the oxide layer, a fourth contact hole penetrating the dielectric layer and located on the second polysilicon layer, and a fifth contact hole located on the third injection region; A first metal layer is formed in the first contact hole, the second contact hole and located on the dielectric layer, a second metal layer is formed in the third contact hole and located on the dielectric layer, and a third metal layer is formed in the fourth contact hole, the fifth contact hole and located on the dielectric layer.

2. The integrated high-performance LDMOS device according to claim 1, characterized in that: The first conductivity type is P type, the second conductivity type is N type, and the third well region is a drift region.

3. The integrated high-performance LDMOS device according to claim 1, characterized in that: The doping concentration of the second well region is greater than the doping concentration of the third well region, and the junction depth of the epitaxial layer is less than the junction depth of the first well region.

4. A method for preparing an integrated high-performance LDMOS device, characterized in that: The following steps are involved: providing a substrate of a first conductivity type; forming a first well region of the second conductivity type on one side of the substrate, forming a buried layer of the first conductivity type on the other side of the substrate, and forming an epitaxial layer of the first conductivity type on the substrate between the first well region and the buried layer; forming a third well region of the second conductivity type on the epitaxial layer and the first well region, forming a second well region of the first conductivity type connected to the epitaxial layer on the buried layer, a fourth well region of the second conductivity type located on the first well region, and forming an oxide layer on the third well region and the fourth well region; Growing polysilicon on the second well region, the third well region, the oxide layer and the fourth well region, and injecting second conductivity type impurities into the polysilicon to form a polysilicon thin film; The polysilicon film above the oxide layer is photolithographically processed and second conductive type impurities are implanted to form equipotential rings and resistive field plates arranged at intervals, and the polysilicon on the second well region and the fourth well region is etched to correspondingly form a first polysilicon layer located on the second well region and the oxide layer and a second polysilicon layer located above the fourth well region, the resistive field plate is located between the first polysilicon layer and the second polysilicon layer, and the equipotential rings are located between the resistive field plates; Performing first conductive type ion implantation and second conductive type ion implantation into the second well region respectively to form a first implantation region and a second implantation region located in the second well region and arranged at intervals, and implanting second conductive type ions into the fourth well region to form a third implantation region connected to the oxide layer; Forming a dielectric layer on the second well region, the first polysilicon layer, the resistive field plate, the equipotential ring, the second polysilicon layer, the oxide layer and the third injection region, and performing photolithography on the first injection region, the second injection region, the first polysilicon layer on the oxide layer, the second polysilicon layer, and the dielectric layer corresponding to the third injection region to form a first contact hole, a second contact hole, a third contact hole, a fourth contact hole and a fifth contact hole, respectively; A first metal layer is formed on the dielectric layer in the first contact hole, the second contact hole and above the second well region, a second metal layer is formed on the third contact hole and the dielectric layer corresponding to the third contact hole, and a third metal layer is formed on the dielectric layer in the fourth contact hole, the fifth contact hole and above the fourth well region.

5. The method for preparing an integrated high-performance LDMOS device according to claim 4, characterized in that: The first conductivity type is P type, the second conductivity type is N type, the second conductivity type impurities and the second conductivity type ions both include N type phosphorus or arsenic, and the first conductivity type ions include boron or aluminum.

6. The method for preparing an integrated high-performance LDMOS device according to claim 5, characterized in that: The thickness of the oxide layer is between 100 and 500 Å, and the thickness of the polysilicon film is between 3000 and 5000 Å.

7. The method for preparing an integrated high-performance LDMOS device according to claim 4, characterized in that: The polysilicon film above the oxide layer is subjected to photolithography and second conductivity type impurities are implanted, comprising: Firstly, second conductivity type impurities are injected into the polysilicon for the first time, and thermal annealing is performed to form a polysilicon thin film; The polysilicon film above the oxide layer is subjected to photolithography and second-conductivity-type impurities are implanted for a second time to form the equipotential ring and the resistive field plate.

8. The method for preparing an integrated high-performance LDMOS device according to claim 7, characterized in that: The first implantation dose of the second conductive type impurity is between 1E12 and 2E13, the annealing temperature for preparing the polysilicon film is between 800 and 1100° C., the time is between 20 and 120 seconds, and the square resistance of the polysilicon film after annealing is above 100 Mohm.

9. The method for preparing an integrated high-performance LDMOS device according to claim 7, characterized in that: The second implantation dosage of the second conductive type impurity is between 5E15 and 2E16, the square resistance of the equipotential ring is between 10 and 30 ohms, and the square resistance of the resistive field plate is between 100 M and 1 Gohm.

10. The method for preparing an integrated high-performance LDMOS device according to claim 4, characterized in that: The resistivities of the first polysilicon layer, the equipotential ring and the second polysilicon layer are equal, and the third well region is a drift region.

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