Power device

Abstract

The invention discloses a power device which comprises a plurality of device units connected in parallel. The device unit comprises a gate structure channel region, a source region and a drift region, and the channel region is located between the source region and the drift region. In a first region of the device cell, a channel region and a drift region are in direct contact in a channel length direction, a coverage of the gate structure extending from the channel region into the drift region. In the second region of the device unit, the channel region is in direct contact with the gate capacitance adjusting region in the channel length direction, the coverage area of the gate structure extends from the channel region to the gate capacitance adjusting region, and the gate capacitance adjusting region outside the coverage area of the gate structure enables a conductive path between the source region and the drift region to be disconnected. And the channel region, the source region and the gate capacitance adjusting region are connected to a source electrode consisting of the front metal layer. According to the invention, Cgd can be reduced and Cgs can be increased at the same time, so that the peak voltage can be reduced, and the peak voltage of the device can be reduced to an acceptable range while the switching loss of the device is reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a power device. Background Art

[0002] Power devices are widely used in switching power conversion circuits as switch tubes to control output current and voltage. It is usually hoped that the switching speed of power devices is as fast as possible, so that the switching loss is low, the device can operate at a higher operating frequency, and the size of passive devices required in the circuit can be reduced. However, the increase in switching speed, especially the increase in shutdown speed, will lead to an increase in peak voltage during the shutdown process, which will increase the stress of the device and even bring the risk of device damage in severe cases.

[0003] Therefore, in power devices, how to ensure that the peak voltage of the device is within an acceptable range while reducing the switching loss of the device is an important issue. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a power device that can reduce the gate-drain capacitance (Cgd) of the device and increase the gate-source capacitance (Cgs) of the device at the same time, and reduce the peak voltage by simultaneously adjusting the gate-drain capacitance and the gate-source capacitance, thereby reducing the peak voltage of the device to an acceptable range while reducing the switching loss of the device.

[0005] In order to solve the above technical problem, the power device provided by the present invention includes a plurality of device units connected in parallel.

[0006] The device unit comprises a gate structure and a channel region doped with a second conductivity type, a source region heavily doped with a first conductivity type, and a drift region doped with the first conductivity type, wherein the channel region is located between the source region and the drift region, the source region is formed in a surface region of the channel region and is self-aligned with a side surface of the corresponding gate structure; the drift region is formed on a semiconductor substrate;

[0007] In the first area of ​​the device unit, in the channel length direction, the channel region and the drift region are in direct contact, the coverage range of the gate structure extends from the channel region to the drift region, and the surface of the channel region covered by the gate structure is used to form a conductive channel connecting the source region and the drift region.

[0008] In the second area of ​​the device unit, in the channel length direction, the channel region is in direct contact with the gate capacitance adjustment region doped with the second conductive type, and the coverage of the gate structure extends from the channel region to the gate capacitance adjustment region, and the gate capacitance adjustment region outside the coverage of the gate structure disconnects the conductive path between the source region and the drift region.

[0009] The channel region, the source region and the gate capacitance adjustment region are all connected to a source electrode composed of a front metal layer.

[0010] A further improvement is that the gate structure is a trench gate.

[0011] The gate structure includes a gate dielectric layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench.

[0012] The gate trench vertically passes through the channel region.

[0013] In the second region, the gate capacitance adjustment region is an ion implantation region which is at the bottom of the gate trench and covers the bottom of the gate trench.

[0014] A further improvement is that the gate structure is a strip-shaped structure, and in the device unit area, each of the gate structures is arranged in parallel.

[0015] A further improvement is that each of the device units includes a plurality of the second regions.

[0016] In the arrangement direction of the gate structure, the second regions of the device units at the same position are aligned.

[0017] A further improvement is that, in the arrangement direction of the gate structure, the gate capacitance adjustment regions in the second regions of the device units aligned with each other are connected into a strip.

[0018] A further improvement is that, in the device unit area, the gate structures are all in strip shape.

[0019] The gate structure includes a first gate structure extending along a first direction and a second gate structure extending along a second direction, and the first direction and the second direction are perpendicular to each other.

[0020] The first gate structures are arranged in parallel along the second direction, and the second gate structures are arranged in parallel along the first direction.

[0021] One device unit is formed in a region intersected and surrounded by two adjacent first gate structures and two adjacent second gate structures, and the device unit is in a square shape.

[0022] The second region of the device unit is located at corresponding intersection regions of the first gate structure and the second gate structure at four corners of the square of the device unit.

[0023] A further improvement is that the second region at each corner of each device unit is shared by four adjacent device units.

[0024] The implanted ions in the gate capacitance adjustment region of the second region at each corner of each device unit also extend into the channel region of the first region of each adjacent device unit to increase the threshold voltage at the adjacent position of each device unit.

[0025] A further improvement is that the gate structure is a planar gate.

[0026] The gate structure includes a gate dielectric layer and a gate conductive material layer formed on a top surface of the gate dielectric layer.

[0027] In the first region of the device unit, the gate dielectric layer is formed on the top surface of the channel region and extends to the top surface of the drift region adjacent to the channel region.

[0028] In the second region of the device unit, the gate dielectric layer is formed on the top surface of the channel region and extends to the top surface of the gate capacitance adjustment region adjacent to the channel region.

[0029] A further improvement is that one gate structure is shared by two device units.

[0030] In the first region of the device unit, the gate structure covers the channel regions of two of the device units and the drift region between the channel regions of the two device units.

[0031] In the second region of the device unit, the gate structure covers the channel regions of two of the device units and the gate capacitance adjustment region between the channel regions of the two device units.

[0032] A further improvement is that, in the second area of ​​the device unit, the process structure of the gate capacitance adjustment region between the channel regions of two device units is independent of the channel region; or, the gate capacitance adjustment region between the channel regions of two device units is formed by extending the channel region.

[0033] A further improvement is that two sides of the gate structure overlap with the source regions of the device units at two sides respectively.

[0034] A further improvement is that the formation area of ​​the channel region is defined by a photoresist or by self-alignment of the side surfaces of the corresponding gate structure.

[0035] A further improvement is that each of the gate structures is in a strip shape and arranged in parallel.

[0036] A further improvement is that the power devices include power MOSFETs and power IGBTs;

[0037] The power device includes a split gate power device.

[0038] A further improvement is that the material of the semiconductor substrate includes silicon and silicon carbide.

[0039] A further improvement is that the power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0040] The present invention further divides the device unit into a first region where a conductive channel can be realized and a second region where a conductive channel cannot be realized. In the second region, the gate structure is covered by the gate capacitance adjustment region to extend to the outside of the channel region. In this way, the gate capacitance adjustment region not covered by the gate structure cannot form an inversion layer, so a conductive channel connecting the source region and the drift region cannot be formed in the second region. The gate capacitance adjustment region is in contact with the channel region and is connected to the source electrode together with the source region. In this way, the capacitance formed between the gate structure in the second region and the overlapping channel region and the gate capacitance electrode region is the gate-source capacitance. Obviously, the gate capacitance is By increasing the gate capacitance adjustment area, the gate-source capacitance of the device can be increased; the portion of the gate structure covering the drift region will form a gate-drain capacitance, so after increasing the gate capacitance adjustment area, the gate-drain capacitance can be reduced at the same time; therefore, the present invention can reduce the gate-drain capacitance of the device and increase the gate-source capacitance of the device at the same time; in the switching process of the power device, the reduction of the gate-drain capacitance can increase the dv / dt when turning off, and the increase of the gate-source capacitance can reduce the di / dt. By increasing the dv / dt and reducing the di / dt, the peak voltage can be reduced. Therefore, the present invention can reduce the switching loss of the device while reducing the peak voltage of the device to an acceptable range. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0042] Figure 1A is a top view of the power device according to the first embodiment of the present invention;

[0043] Figure 1B is along Figure 1A Schematic diagram of the cross-sectional structure of line aa;

[0044] Figure 1C is along Figure 1A Schematic diagram of the cross-sectional structure of the bb line;

[0045] Figure 2 is a top view of a power device according to a second embodiment of the present invention;

[0046] Figure 3Ais a schematic cross-sectional structure diagram of a first region of a device unit of a power device according to a third embodiment of the present invention;

[0047] Figure 3B is a schematic cross-sectional structure diagram of a second region of a device unit of a power device according to a third embodiment of the present invention;

[0048] Figure 4 is a schematic cross-sectional structure diagram of a second region of a device unit of a power device according to a fourth embodiment of the present invention;

[0049] Figure 5 It is a schematic cross-sectional structure diagram of the second region of the device unit of the power device according to the fifth embodiment of the present invention. DETAILED DESCRIPTION

[0050] like Figure 1A , which is a top view of the power device according to the first embodiment of the present invention; Figure 1B is along Figure 1A Schematic diagram of the cross-sectional structure of line aa; Figure 1C is along Figure 1A A schematic cross-sectional structure diagram of line bb; the power device of the embodiment of the present invention includes a plurality of device units connected in parallel.

[0051] like Figure 1B As shown, the device unit includes a gate structure, a channel region 5 doped with a second conductivity type, a source region 6 heavily doped with a first conductivity type, and a drift region 2 doped with a first conductivity type, wherein the channel region 5 is located between the source region 6 and the drift region 2, and the source region 6 is formed in the surface region of the channel region 5 and self-aligned with the side of the corresponding gate structure. The drift region 2 is formed on a semiconductor substrate 1.

[0052] In the first embodiment of the present invention, the semiconductor substrate 1 is used to provide mechanical support. The higher the doping concentration of the semiconductor substrate 1, the better. The thinner the thickness of the semiconductor substrate 1, the better.

[0053] The drift region 2 is composed of an epitaxial layer formed on the semiconductor substrate 1. The doping concentration and thickness of the epitaxial layer determine the breakdown voltage of the device. The higher the breakdown voltage required by the device, the thicker the epitaxial layer and the lower the doping concentration of the epitaxial layer.

[0054] The doping concentration of the channel region 5 determines the threshold voltage of the device.

[0055] In the first region of the device unit, the channel region 5 and the drift region 2 are in direct contact in the channel length direction, the coverage of the gate structure extends from the channel region 5 to the drift region 2, and the surface of the channel region 5 covered by the gate structure is used to form a conductive channel connecting the source region 6 and the drift region 2. Figure 1BAs shown, at the bottom of the channel region 5, the gate structure directly contacts the drift region 2. Therefore, after the gate voltage is applied to the gate structure, the inversion layer formed in the channel region 5 can connect the source region 6 and the drift region 2, so a conductive channel can be formed, and the device unit will be turned on in the first region.

[0056] like Figure 1C As shown, in the second region of the device unit, in the channel length direction, the channel region 5 and the gate capacitance adjustment region 11 doped with the second conductivity type are in direct contact, and the coverage of the gate structure extends from the channel region 5 to the gate capacitance adjustment region 11, and the gate capacitance adjustment region 11 outside the coverage of the gate structure disconnects the conductive path between the source region 6 and the drift region 2. Figure 1C As shown, at the bottom of the channel region 5, the gate structure will be covered by the gate capacitance adjustment region 11, so that it will not contact the drift region 2. Therefore, after the gate voltage is applied to the gate structure, the channel region 5 on the side of the gate structure will form an inversion layer, but the gate capacitance adjustment region 11 at the bottom of the gate structure will not form an inversion layer, so a conductive channel connecting the source region 6 and the drift region 2 will not be formed, and the device unit will not be conductive in the second region.

[0057] The channel region 5, the source region 6 and the gate capacitance adjustment region 11 are all connected to the source electrode 9 composed of the front metal layer. The source electrode 9 will achieve ohmic contact with the source region 6 at the bottom through the through hole 8 that passes through the interlayer film. The through hole 8 will also pass through the source region 6 and contact the channel region 5 at the bottom. Usually, a through hole injection region 7 heavily doped with the second conductivity type is formed at the bottom of the through hole 8, and an ohmic contact is achieved between the through hole injection region 7 and the through hole 8. Taking the N-type device as an example, the through hole injection region 7 is usually BF2 injected, and the injection dose is usually 1e14cm -2 ~1e16cm -2 The energy is usually between 15 and 40 keV.

[0058] Depend on Figure 1C As shown, the gate capacitance adjustment region 11 will contact the channel region 5 and finally be connected to the source 9. Since the gate capacitance adjustment region 11 is connected to the source 9, the parasitic capacitance formed by the contact between the gate structure and the bottom gate capacitance adjustment region 11 is the gate-source capacitance, so the gate-source capacitance will be increased after the gate capacitance adjustment region 11 is set.

[0059] like Figure 1B As shown, the parasitic capacitance formed by the contact between the gate structure and the drift region 2 at the bottom is the gate-drain capacitance. Therefore, after the gate capacitance adjustment region 11 is set, the contact area between the gate structure and the drift region 2 at the bottom will be reduced, thereby reducing the gate-drain capacitance. Figure 1A As shown, at the same time, the gate capacitance adjustment region 11 will also deplete the drift region 2 in the y direction, which can reduce the Cgd of the bb cross section.

[0060] like Figure 1B As shown, in the first embodiment of the present invention, the gate structure is a trench gate.

[0061] The gate structure includes a gate dielectric layer 3 formed on the inner surface of the gate trench and a gate conductive material layer 4 filled in the gate trench. In some embodiments, the gate dielectric layer 3 is a gate oxide layer, i.e., gate oxide, and the gate conductive material layer 4 is a polysilicon gate. The thickness of the oxide layer of the gate dielectric layer 3 determines the breakdown voltage of the gate oxide.

[0062] The gate trench passes through the channel region 5 vertically.

[0063] In the second region, the gate capacitance adjustment region 11 is an ion implantation region that covers the bottom of the gate trench, that is, the gate capacitance adjustment region 11 is formed by an ion implantation process.

[0064] like Figure 1A As shown, the gate structure is a strip-shaped structure, and in the device unit area, each gate structure is arranged in parallel. Figure 1A A partial area of ​​the device unit region is shown. The X direction is the width direction of the gate structure, that is, the arrangement direction, and the Y direction is the length direction of the gate structure, that is, the extension direction. Figure 1A In the figure, the gate conductive material layer 4 is directly used to represent the gate structure.

[0065] Figure 1A In the present invention, a gate structure and a spacer region between the gate structures are regarded as a formation region of a device unit.

[0066] Each device unit includes a plurality of second regions.

[0067] In the arrangement direction of the gate structures, the second regions of the device units at the same position are aligned. Figure 1A In FIG. 1 , region 11a is a region where second regions in the same row are connected.

[0068] In the first embodiment of the present invention, in the arrangement direction of the gate structure, the gate capacitance adjustment regions 11 in the second regions of the mutually aligned device units are connected into a strip. In other embodiments, the gate capacitance adjustment regions 11 in the second regions of the mutually aligned device units may not be connected together. In the first embodiment of the present invention, the gate capacitance adjustment region 11 is formed by ion implantation. The ion implantation can be formed after the gate trench is formed and before the gate conductive material layer 4 is formed. Before the ion implantation of the gate capacitance adjustment region 11, it is necessary to Figure 1AThe region 11a in the gate capacitance adjustment region is opened, which requires an additional mask; then the gate capacitance adjustment region 11 is ion implanted, and the implantation energy is relatively small, for example, 40keV to 100keV. In the region 11a, the implanted ions cannot penetrate the layers outside the gate trench, so the gate capacitance adjustment region 11 is only formed in the bottom region of the gate trench. Taking the N-type device as an example, the implanted impurity of the ion implantation of the gate capacitance adjustment region 11 is boron, and the implantation dose is 1e12cm -2 ~5e13cm -2 between.

[0069] In some embodiments, the ion implantation can be performed after the gate conductive material layer 4 is formed, and before the ion implantation of the gate capacitance adjustment region 11, Figure 1A The region 11a in the gate is opened, and then ion implantation of the gate capacitance adjustment region 11 is performed. The implanted ions need to pass through the gate conductive material layer 4. At this time, the implantation energy is relatively large, for example, 200keV~2MeV. In the region 11a, the implanted ions may also penetrate the various layers of structure outside the gate trench. At this time, the gate capacitance adjustment regions 11 formed in the bottom area of ​​the gate trench may be connected together.

[0070] In some embodiments, Figure 1A As shown, in the Y direction, the width of the gate capacitance adjustment region 11, that is, the width of the region 11a, is 5 μm, and the spacing (Space) between the gate capacitance adjustment regions 11 is also 5 μm.

[0071] In the first embodiment of the present invention, the power device is a power MOSFET. The semiconductor substrate 1 is heavily doped with the first conductivity type, and the thinned semiconductor substrate 1 serves as a drain region; a drain electrode composed of a back metal layer is also formed on the back of the drain region.

[0072] In other embodiments, the power device may be a power IGBT. In this case, the drain region needs to be replaced by a collector region heavily doped with the second conductivity type.

[0073] In the first embodiment of the present invention, the gate structure of the power device is an integrated structure. In other embodiments, the power device may include a split-gate power device, the gate structure may also include a shielding gate conductive material layer isolated from the gate conductive material layer, and a shielding gate dielectric layer may be provided between the shielding gate conductive material layer and the gate trench.

[0074] In the first embodiment of the present invention, the material of the semiconductor substrate 1 is silicon, and the power device is a silicon-based device. In other embodiments, the material of the semiconductor substrate 1 is silicon carbide, and the power device is a SiC-based device.

[0075] In the first embodiment of the present invention, the power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the power device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0076] The first embodiment of the present invention further divides the device unit into a first region where a conductive channel can be realized and a second region where a conductive channel cannot be realized. In the second region, the gate structure is covered by the gate capacitance adjustment region 11, which extends to the outside of the channel region 5. In this way, the gate capacitance adjustment region 11 not covered by the gate structure cannot form an inversion layer, so a conductive channel connecting the source region 6 and the drift region 2 cannot be formed in the second region. The gate capacitance adjustment region 11 is in contact with the channel region 5 and is connected to the source electrode 9 together with the source region 6. In this way, the capacitance formed between the gate structure in the second region and the overlapping channel region 5 and the gate capacitance electrode region is the gate-source capacitance. Obviously, By adding a gate capacitance adjustment region 11, the gate-source capacitance of the device can be increased; the portion of the gate structure covering the drift region 2 will form a gate-drain capacitance, so after adding the gate capacitance adjustment region 11, the gate-drain capacitance can be reduced at the same time; therefore, the first embodiment of the present invention can reduce the gate-drain capacitance of the device and increase the gate-source capacitance of the device at the same time; in the switching process of the power device, the reduction of the gate-drain capacitance at shutdown can increase dv / dt, and the increase of the gate-source capacitance can reduce di / dt. By increasing dv / dt and reducing di / dt, the peak voltage can be reduced. Therefore, the first embodiment of the present invention can reduce the switching loss of the device while reducing the peak voltage of the device to an acceptable range.

[0077] The principle of reducing the peak voltage by reducing the gate-drain capacitance of the device and increasing the gate-source capacitance of the device in the first embodiment of the present invention is further described as follows:

[0078] During the switching process of power devices, the load is usually an inductive load. When the device is turned off, the relationship between the current and voltage between the drain (Drai) and the source (Source) is that the voltage rises first, and when the switching voltage reaches Vdd, the current drops. The faster the current drops, the faster the voltage spike of the MOSFET is, and this voltage spike is roughly equal to Vdd+Lpar*di / dt; Lpar is the parasitic inductance in the line.

[0079] In order to reduce the turn-off loss of the device and keep the overshoot within an acceptable range, a feasible approach is to increase the speed of voltage rise, that is, to increase dv / dt; and reduce di / dt.

[0080] The dv / dt of the device is inversely proportional to Cgd, while the di / dt of the device is inversely proportional to Cgs. Therefore, the first embodiment of the present invention achieves both reduction of Cgd and increase of Cgs, thereby reducing the turn-off loss of the device while keeping the overshoot within an acceptable range.

[0081] like Figure 2 , which is a top view of a power device according to a second embodiment of the present invention; the difference between the power device according to the second embodiment of the present invention and the power device according to the first embodiment of the present invention is that in the power device according to the second embodiment of the present invention:

[0082] In the device unit area, the gate structures are all in the shape of strips.

[0083] The gate structure includes a first gate structure 4a extending along a first direction and a second gate structure 4b extending along a second direction, and the first direction and the second direction are perpendicular to each other. Figure 2 , the first direction is the Y direction and the second direction is the X direction.

[0084] The first gate structures 4 a are arranged in parallel along the second direction, and the second gate structures 4 b are arranged in parallel along the first direction.

[0085] A device unit is formed in a region such as region 12 which is surrounded by two adjacent first gate structures 4a and two adjacent second gate structures 4b, and the device unit is in a square shape.

[0086] The second region of the device unit is located at the intersection of the first gate structure 4a and the second gate structure 4b corresponding to the four corners of the square of the device unit. Figure 2 In FIG. 1 , the second area is marked with a mark 11b.

[0087] The second region at each corner of each device unit is shared by four adjacent device units.

[0088] In some embodiments, the implanted ions in the gate capacitance adjustment region 11 in the second region at each corner of each device unit also extend into the channel region 5 in the first region of each adjacent device unit to increase the threshold voltage at the adjacent position of each device unit. The implanted ions in the gate capacitance adjustment region 11 that also extend into the channel region 5 in the first region of each adjacent device unit can be adjusted by implantation dose and implantation energy;

[0089] The cross-sectional structure of the device unit in the first region of the power device of the second embodiment of the present invention is the same as the cross-sectional structure of the device unit in the first region of the power device of the first embodiment of the present invention, and the cross-sectional structure of the device unit in the second region of the power device of the second embodiment of the present invention is the same as the cross-sectional structure of the device unit in the second region of the power device of the first embodiment of the present invention, and will not be described in detail again.

[0090] In the second embodiment of the present invention, the density of the grooves can be increased by using square primitive cells, i.e., device units. For square primitive cells, at the junction of the square primitive cells, the channel region will be inverted by the trench gates on both sides at the same time, and the threshold voltage here will usually be relatively low, which will cause the primitive cells to not be turned on at the same time during the device opening process. In order to solve this problem, in the second embodiment of the present invention, a gate capacitance adjustment region 11 is added to the second region 11a, which can not only reduce Cgd and increase Cgs; but also increase the channel doping concentration at the junction of the primitive cells by adjusting the injection dose and energy of the gate capacitance adjustment region 11, thereby increasing the threshold voltage here.

[0091] like Figure 3A , which is a schematic cross-sectional structure diagram of a first region of a device unit of a power device according to a third embodiment of the present invention; Figure 3B FIG. 1 is a schematic diagram of a cross-sectional structure of a device unit at a second region of a power device according to a third embodiment of the present invention; the difference between the power device according to the third embodiment of the present invention and the power device according to the first embodiment of the present invention is that in the power device according to the third embodiment of the present invention:

[0092] like Figure 3A As shown, the gate structure is a planar gate.

[0093] The gate structure includes a gate dielectric layer 23 and a gate conductive material layer 24 formed on the top surface of the gate dielectric layer 23 .

[0094] In the first region of the device cell, the gate dielectric layer 23 is formed on the top surface of the channel region 25 and extends to the top surface of the drift region 22 adjacent to the channel region 25 .

[0095] like Figure 3B As shown, in the second region of the device unit, the gate dielectric layer 23 is formed on the top surface of the channel region 25 and extends to the top surface of the gate capacitance adjustment region 31 adjacent to the channel region 25 .

[0096] In the third embodiment of the present invention, one gate structure is shared by two device units.

[0097] In the first region of the device unit, the gate structure covers the channel regions 25 of the two device units and the drift region 22 between the channel regions 25 of the two device units. A source region 26 is formed on both sides of the gate structure in alignment. A through hole 28 is formed on the top of the source region 26 and is connected to a source 29 composed of a front metal layer. A through hole injection region 27 is also formed at the bottom of the through hole 28.

[0098] In the second region of the device unit, the gate structure covers the channel regions 25 of the two device units and the gate capacitance adjustment region 31 between the channel regions 25 of the two device units.

[0099] Two sides of the gate structure overlap with the source regions 26 of the device units on both sides respectively.

[0100] The formation area of ​​the channel region 25 is defined by a photoresist or by self-alignment of the side of the corresponding gate structure.

[0101] Each gate structure is in strip shape and arranged in parallel. The arrangement structure can refer to Figure 1A shown.

[0102] In the third embodiment of the present invention, in the second region of the device unit, the process structure of the gate capacitance adjustment region 31 between the channel regions 25 of the two device units is independent of the channel region 25. The gate capacitance adjustment region 31 needs to be defined separately by using a photolithography process. Figure 3B In the embodiment, the depth of the gate capacitance adjustment region 31 is greater than the depth of the channel region 25. In other embodiments, the depth of the gate capacitance adjustment region 31 can be less than or equal to the depth of the channel region 25.

[0103] In the third embodiment of the present invention, the power device is a power MOSFET, the semiconductor substrate 21 is heavily doped with the first conductivity type, and the thinned semiconductor substrate 21 serves as a drain region; a drain electrode composed of a back metal layer is also formed on the back of the drain region.

[0104] like Figure 4 , which is a schematic diagram of the cross-sectional structure of the second region of the device unit of the power device of the fourth embodiment of the present invention; the difference between the power device of the fourth embodiment of the present invention and the power device of the third embodiment of the present invention is that in the power device of the fourth embodiment of the present invention:

[0105] The gate capacitance adjustment region 31 a between the channel regions 25 of the two device units is formed by extending the channel region 25 .

[0106] The formation area of ​​the channel region 25 is defined by a photoresist. Through the photoresist of the channel region 25, the channel region 25 is a continuous structure in the second region. In the first region, the channel region 25 remains Figure 3A The structure shown, that is, Figure 4 The structure of the gate capacitance adjustment region 31a is removed.

[0107] For the planar gate structure, its trench gate is different. The formation of the channel region 25 of the planar gate is usually with a photomask; therefore, the formation of the gate capacitance adjustment region 31 structure can also adopt different schemes; such as a typical structure, the width of the gate structure is 3μm, and the channel region 26 and the gate conductive material layer 24 have an overlap of 0.75μm; 31, the fourth embodiment of the present invention uses the photomask of the channel region 26 to allow the channel region 26 to completely wrap the gate.

[0108] like Figure 5, which is a schematic diagram of the cross-sectional structure of the second region of the device unit of the fifth embodiment of the present invention; the difference between the power device of the fifth embodiment of the present invention and the power device of the fourth embodiment of the present invention is that in the power device of the fifth embodiment of the present invention:

[0109] The formation area of ​​the channel region 25 is defined by the side self-alignment of the corresponding gate structure. The channel region 25 needs to be annealed and diffused to the bottom of the gate structure after ion implantation using the side self-alignment of the gate structure. In this structure, the source region 26 is also annealed and diffused to the bottom of the gate structure after the side self-alignment implantation using the gate structure. However, the diffusion lengths of the channel region 25 and the source region 26 are different, and there is a distance between the edges of the two. In this structure, the overlap area between the source region 26 and the gate structure is relatively large. Figure 4 The structure shown in is large.

[0110] In some structures corresponding to the fifth embodiment of the present invention, the channel region 26 is formed in a self-aligned manner, and the distance between the channel region 26 and the source region 26 is fixed, such as 0.5 μm; at this time, the channel region 26 will also cover more with the gate conductive material layer 24.

[0111] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A power device, characterized in that: comprising a plurality of device units connected in parallel; The device unit comprises a gate structure and a channel region doped with a second conductivity type, a source region heavily doped with a first conductivity type, and a drift region doped with the first conductivity type, wherein the channel region is located between the source region and the drift region, and the source region is formed in a surface region of the channel region and self-aligned with a side surface of the corresponding gate structure; A drift region is formed on a semiconductor substrate; In the first region of the device unit, in the channel length direction, the channel region and the drift region are in direct contact, the coverage of the gate structure extends from the channel region to the drift region, and the surface of the channel region covered by the gate structure is used to form a conductive channel connecting the source region and the drift region; In the second region of the device unit, in the channel length direction, the channel region is in direct contact with the gate capacitance adjustment region doped with the second conductivity type, and the coverage of the gate structure extends from the channel region to the gate capacitance adjustment region, and the gate capacitance adjustment region outside the coverage of the gate structure disconnects the conductive path between the source region and the drift region; The channel region, the source region and the gate capacitance adjustment region are all connected to a source electrode composed of a front metal layer.

2. The power device according to claim 1, characterized in that: The gate structure is a trench gate; The gate structure includes a gate dielectric layer formed on the inner surface of the gate trench and a gate conductive material layer filled in the gate trench; The gate trench passes through the channel region longitudinally; In the second region, the gate capacitance adjustment region is an ion implantation region which is at the bottom of the gate trench and covers the bottom of the gate trench.

3. The power device according to claim 2, characterized in that: The gate structures are in the form of strips, and in the device unit area, the gate structures are arranged in parallel.

4. The power device according to claim 3, characterized in that: Each of the device units includes a plurality of the second regions; In the arrangement direction of the gate structure, the second regions of the device units at the same position are aligned.

5. The power device according to claim 4, characterized in that: In the arrangement direction of the gate structures, the gate capacitance adjustment regions in the second regions of the device units aligned with each other are connected into a line.

6. The power device according to claim 2, characterized in that: In the device unit area, the gate structures are all in strip shape; The gate structure includes a first gate structure extending along a first direction and a second gate structure extending along a second direction, the first direction and the second direction being perpendicular to each other; The first gate structures are arranged in parallel along the second direction, and the second gate structures are arranged in parallel along the first direction; A device unit is formed in an area intersected and surrounded by two adjacent first gate structures and two adjacent second gate structures, and the device unit is square; The second region of the device unit is located at corresponding intersection regions of the first gate structure and the second gate structure at four corners of the square of the device unit.

7. The power device according to claim 6, characterized in that: The second region at each corner of each device unit is shared by four adjacent device units; The implanted ions in the gate capacitance adjustment region of the second region at each corner of each device unit also extend into the channel region of the first region of each adjacent device unit to increase the threshold voltage at the adjacent position of each device unit.

8. The power device according to claim 1, characterized in that: The gate structure is a planar gate; The gate structure includes a gate dielectric layer and a gate conductive material layer formed on the top surface of the gate dielectric layer; In the first region of the device unit, the gate dielectric layer is formed on the top surface of the channel region and extends to the top surface of the drift region adjacent to the channel region; In the second region of the device unit, the gate dielectric layer is formed on the top surface of the channel region and extends to the top surface of the gate capacitance adjustment region adjacent to the channel region.

9. The power device according to claim 8, characterized in that: One of the gate structures is shared by two of the device units; In the first region of the device unit, the gate structure covers the channel regions of two device units and the drift region between the channel regions of the two device units; In the second region of the device unit, the gate structure covers the channel regions of two of the device units and the gate capacitance adjustment region between the channel regions of the two device units.

10. The power device according to claim 9, characterized in that: In the second region of the device unit, the process structure of the gate capacitance adjustment region between the channel regions of two device units is independent of the channel region; or, the gate capacitance adjustment region between the channel regions of two device units is formed by extending the channel region.

11. The power device according to claim 10, characterized in that: Two sides of the gate structure overlap with the source regions of the device units at two sides respectively.

12. The power device according to claim 10, characterized in that: The formation area of ​​the channel region is defined by a photoresist or by self-alignment of the side surface of the corresponding gate structure.

13. The power device according to claim 9, characterized in that: Each of the gate structures is in a strip shape and is arranged in parallel.

14. The power device according to any one of claims 1 to 13, characterized in that: Power devices include power MOSFET and power IGBT; The power device comprises a split-gate power device.

15. The power device according to any one of claims 1 to 13, characterized in that: The material of the semiconductor substrate includes silicon and silicon carbide.

16. The power device according to any one of claims 1 to 13, characterized in that: The power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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