Semiconductor structure of image sensor and manufacturing method thereof
By providing a partially overlapping first contact diffusion region and a metal plug layer in the dielectric layer in the CMOS sensor, the problem of mutual constraints on the performance of the photosensitive device and the logic circuit is solved, and pixel size is reduced and transistor working efficiency is improved.
Patent Information
- Application Number
- CN202310789426.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2025-01-10
AI Technical Summary
In the existing CMOS sensor process, the mutual constraints between the performance of photosensitive devices and the performance of peripheral logic circuits lead to the inability to achieve the best image sensor performance, especially when the pixel unit size is miniaturized, ion lateral diffusion affects channel length and parasitics. Capacitor affects the working efficiency of the transistor.
By providing a first contact diffusion region on the semiconductor substrate, it is located on the side of the active region facing away from the gate, only partially overlap, and through holes are formed in the dielectric layer for ion implantation, a metal plug layer is generated, and a metal plug layer is reduced The contact resistance between the active region and the metal plug is reduced by a pixel isolation structure.
In the pixel size miniaturization process, the channel is reduced by ion diffusion, the working efficiency of the transistor is improved, and sufficient connection is made through lateral diffusion of the contact diffusion region, reducing the between the active region and the metal plug. contact resistance.
Smart Images
Figure CN119300492A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of image sensors, and in particular to a semiconductor structure of an image sensor and a method for manufacturing the semiconductor structure of the image sensor. Background Art
[0002] The current CMOS sensor process has evolved from the traditional logic circuit process, in which many process steps restrict each other between the performance of the sensor photosensitive device and the performance of the peripheral logic circuit. Therefore, it is impossible to achieve the best image sensor performance in actual production design. With the continuous optimization of special pixel processes and the emergence of stacking methods, it is possible to further optimize the performance of photosensitive devices. This patent proposes a process step for optimizing the access hole of the photosensitive device to achieve better pixel performance optimization. Summary of the invention
[0003] In view of this, the present invention provides a semiconductor structure of an image sensor, comprising: a semiconductor substrate, wherein the semiconductor substrate has a photoelectric conversion region and a gate located on the photoelectric conversion region; an active region, located in the semiconductor substrate and distributed on both sides of the gate; a contact diffusion region, located in the semiconductor substrate, the contact diffusion region at least including a first contact diffusion region, and the first contact diffusion region is located on a side of the active region away from the gate and only partially overlaps with the active region; a dielectric layer, located above the semiconductor substrate and the gate, a through hole is opened in the dielectric layer to at least partially expose the contact diffusion region; and a metal plug layer, located in the through hole.
[0004] Optionally, the area of the overlapping region between the first contact diffusion region and the active region is a, and the area of the non-overlapping region between the first contact diffusion region and the active region is b; wherein a>b.
[0005] Optionally, the ion doping concentration in the overlapping region of the first contact diffusion region and the active region is greater than the ion doping concentration in the non-overlapping region of the first contact diffusion region and the active region.
[0006] Optionally, the lateral width of the overlapping region between the first contact diffusion region and the active region is n, the lateral width of the active region is m, and the lateral width of the gate spacer is s, wherein mn≥s.
[0007] Optionally, the contact diffusion region further includes a second contact diffusion region, and a vertical projection of the second contact diffusion region is located within the active region.
[0008] Optionally, the gate includes one or more of a transfer gate, a reset gate, a source follower gate and a row select gate.
[0009] Optionally, the semiconductor structure further includes: a pixel isolation structure located between adjacent photoelectric conversion regions; and a vertical projection of the first contact diffusion region partially overlaps with the pixel isolation structure.
[0010] Optionally, the lateral width of the first contact diffusion region is always greater than the lateral width of the metal plug located on the same horizontal plane.
[0011] The present invention also includes a method for manufacturing the semiconductor structure of the above-mentioned image sensor, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has a photoelectric conversion region, a gate located on the photoelectric conversion region, and active regions distributed on both sides of the gate; forming a dielectric layer above the semiconductor substrate; patterning the dielectric layer to generate a through hole that partially exposes the active region; performing ion implantation on the portion of the active region exposed by the through hole to generate a contact diffusion region; depositing metal in the through hole, wherein the metal reacts with the contact diffusion region to form a metallization, thereby finally generating a metal plug layer.
[0012] The present invention also includes a method for manufacturing the semiconductor structure of the above-mentioned another image sensor, comprising:
[0013] A semiconductor substrate is provided, wherein the semiconductor substrate has a photoelectric conversion region, a gate located on the photoelectric conversion region, active regions distributed on both sides of the gate, and a pixel isolation structure distributed between adjacent photoelectric conversion regions; a dielectric layer is formed above the semiconductor substrate; the dielectric layer and the pixel isolation structure are patterned to generate a through hole partially exposing the active region; ion implantation is performed on the part of the active region exposed by the through hole to generate a contact diffusion region; metal is deposited in the through hole, and the metal reacts with the contact diffusion region to form a metallization to finally generate a metal plug layer.
[0014] Compared with the prior art, the present invention has at least one of the following outstanding advantages:
[0015] The present invention arranges the first contact diffusion region on the side of the active region away from the gate, so that the first contact diffusion region and the active region only partially overlap, so that in the pixel size miniaturization process, even if ions diffuse laterally, the channel is still less affected, and the ion diffusion does not affect the parasitic capacitance of the source and drain, so that the working efficiency of the transistor is improved, and sufficient connection can be made through the lateral diffusion of ions in the contact diffusion region, thereby reducing the contact resistance between the active region and the metal plug. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a diagram of the process steps for forming a conventional image sensor semiconductor structure;
[0017] Figure 2 is a partial cross-sectional schematic diagram of a semiconductor structure provided by an embodiment of the present invention;
[0018] Figure 3 is a schematic structural diagram of a first contact diffusion region provided by an embodiment of the present invention;
[0019] Figure 4is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;
[0020] Figure 5 is a partial cross-sectional schematic diagram of another semiconductor structure provided by an embodiment of the present invention;
[0021] Figure 6 This is a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;
[0022] Figure 7 yes Figure 2 A diagram showing steps of a method for manufacturing the semiconductor structure shown;
[0023] Figure 8 This is another method for manufacturing a semiconductor structure provided by an embodiment of the present invention;
[0024] Fig. 9 yes Figure 5 A diagram showing the steps of a method for manufacturing a semiconductor structure. DETAILED DESCRIPTION
[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0026] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0027] Please refer to Figure 2 , Figure 2 A semiconductor structure provided by an embodiment of the present invention includes:
[0028] The semiconductor substrate 10 has a photoelectric conversion region (not shown in the figure) and a gate 20 located on the photoelectric conversion region; wherein the gate 20 also includes a side wall 201 located on its side to increase the width of the gate 20 and the drain LDD region, thereby effectively controlling the influence of parasitic capacitance.
[0029] The active region 12 is located in the semiconductor substrate 10 and distributed on both sides of the gate 20 . Active regions of different doping types can form n-type active regions or p-type active regions. The active region can be divided into a source region and a drain region.
[0030] The contact diffusion region 14 is located in the semiconductor substrate 10. The contact diffusion region 14 includes at least a first contact diffusion region 140. The first contact diffusion region 140 is located on the side of the active region 12 away from the gate and only partially overlaps with the active region. Forming a contact diffusion region in the active region is a preliminary step for forming a metal plug. The ion doping concentration of the active region has a great influence on the contact resistance between the metal plug and the active region. Therefore, by further ion doping on the active region to form a contact diffusion region with a higher ion concentration, the contact resistance between the active region and the metal plug can be reduced. The ion doping type of the contact diffusion region is consistent with the ion doping type of its corresponding active region.
[0031] The dielectric layer 30 is located above the semiconductor substrate 10 and the gate 20. A through hole 32 is opened in the dielectric layer 30 to at least partially expose the contact diffusion region 14. It can be understood that the dielectric layer 30 here may include more than one dielectric layer, for example, it may include a combination of one or more of oxide, silicon oxide, nitride, silicon nitride or oxynitride, which is not limited here.
[0032] The metal plug layer 40 is located in the through hole 32. The process of depositing metal or metallization in the through hole 32 to form a metal connection layer is called a local interconnection process. In some embodiments, at least one of nickel, cobalt, aluminum, copper, titanium or tungsten can be used.
[0033] In the prior art, Figure 1 As shown in the process steps of forming the semiconductor structure of the conventional image sensor, after forming the active region 112 in the semiconductor substrate 110, further ion doping is performed in the active region 112 to form the contact diffusion region 114, and then the dielectric layer 130 is provided, and the contact hole pattern is defined in the dielectric layer 130 by the photolithography process, and the contact hole is self-aligned and etched according to the contact hole pattern to form the contact hole to expose the contact diffusion region 114, and finally metal or metallization is deposited in the contact hole to form the metal plug layer 140. However, as the size of the pixel unit decreases, the spacing between the gates decreases, and in the process of directly ion doping in the active region to form the contact diffusion region, the lateral diffusion of ions will affect the length of the channel, the integration and performance of the device, and secondly, the diffusion of ions will affect the parasitic capacitance of the source and drain, and thus affect the working efficiency of the transistor.
[0034] Therefore, in the present invention, the first contact diffusion region 140 is arranged on the side of the active region 12 away from the gate 20, so that the first contact diffusion region 140 and the active region 12 only partially overlap, so that in the pixel size miniaturization process, even if the ions diffuse laterally, the channel is still less affected, and the ion diffusion does not affect the parasitic capacitance of the source and drain, so that the working efficiency of the transistor is improved. In addition, the lateral diffusion of ions in the contact diffusion region can also make the metal plug and the active region sufficiently connected, thereby reducing the contact resistance between the active region and the metal plug.
[0035] In some embodiments, Figure 3 As shown, the overlapping area of the first contact diffusion region 140 and the active region 12 is a, and the non-overlapping area of the first contact diffusion region 140 and the active region 12 is b; wherein a>b. Increasing the overlapping area of the first contact diffusion region and the active region can improve its conductivity, so that the contact resistance between the metal plug and the active region is further reduced.
[0036] Furthermore, the ion doping concentration of the overlapping region of the first contact diffusion region 140 and the active region 12 is greater than the ion doping concentration of the non-overlapping region of the first contact diffusion region 140 and the active region 12. Since the first contact diffusion region 140 is based on the ion doping concentration of the active region 12 itself, the subsequent ion doping concentration is superimposed, so the ion doping concentration of the overlapping region of the first contact diffusion region 140 and the active region 12 is greater than the ion doping concentration of the non-overlapping region of the first contact diffusion region 140 and the active region 12.
[0037] In some embodiments, in conjunction with reference Figure 2 and Figure 3 , the lateral width of the overlapping area of the first contact diffusion region 140 and the active region 12 is n, the lateral width of the active region 12 is m, and the lateral width of the gate sidewall 201 is s, wherein mn≥s. It can be understood that the lateral width here refers to the direction from the source corresponding to the gate to the drain corresponding to the gate. In the embodiment of the present invention, by limiting the size of the active region and the first contact diffusion region, the length of the channel is retained as much as possible so that it is not affected by the lateral diffusion of ions in the first contact diffusion region.
[0038] In some embodiments, Figure 4As shown, the pixel unit of the CMOS image sensor generally includes a photoelectric conversion element, a transmission transistor TX, a reset transistor RST, a source follower transistor SF and a row selection transistor RS, wherein the photoelectric conversion element includes but is not limited to a photodiode PD, such as a Pin-type photodiode PD, and the number of the photoelectric conversion element, the transmission transistor TX, the reset transistor RST, the source follower transistor SF and the row selection transistor RS can be one or more, that is, the structure of the pixel unit can be selected accordingly, and the specific structure is not limited. Correspondingly, in the semiconductor structure of the CMOS image sensor, a transmission gate, a reset gate, a source follower gate and a row selection gate can be arranged on the semiconductor substrate, and corresponding active areas are arranged on both sides of each of the above gates to form a source and a drain.
[0039] In the present invention application, the first contact diffusion regions corresponding to the transmission gate, reset gate, source follower gate and row selection gate on the semiconductor substrate can be designed to overlap only partially with the active region, thereby reducing the influence of the lateral diffusion of ion doping on the channel, reducing the parasitic capacitance of the source and drain regions, and making sufficient connection between the metal plug and the active region through the lateral diffusion of ions in the contact diffusion region.
[0040] In some embodiments, reference Figure 2 , the contact diffusion region also includes a second contact diffusion region 142, and the second contact diffusion region 142 is vertically projected in the active region 12; it can be understood that the vertical projection refers to the projection of the dielectric layer 30 in the direction of the semiconductor substrate 10. That is, the active regions on both sides of the gate are doped with the first contact diffusion region 140 on one side and the second contact diffusion region 142 on the other side. Based on the semiconductor structure design of the CMOS image sensor, the active regions corresponding to the transmission gate, reset gate, source follower gate and row selection gate on the semiconductor substrate are usually set as N-type ion doped regions, that is, the contact diffusion regions corresponding to the transmission gate, reset gate, source follower gate and row selection gate can be set as the first contact diffusion region doped with N-type ions, so that they only partially overlap with the active region. The semiconductor substrate itself is a P-type semiconductor substrate, and its corresponding contact diffusion region can be set as the second contact diffusion region 142 located in the active region, and voltage is applied through external wiring.
[0041] In some embodiments, Figure 5 As shown, the semiconductor structure further includes: a pixel isolation structure 50, located between adjacent photoelectric conversion regions (not shown in the figure); the vertical projection of the first contact diffusion region 140 partially overlaps with the pixel isolation structure 50. It can be understood that the vertical projection refers to the projection of the dielectric layer 30 in the direction pointing to the semiconductor substrate 10.
[0042] Optionally, the lateral width of the first contact diffusion region 140 is always greater than the lateral width of the metal plug 40 located on the same horizontal plane. It can be understood that the lateral width here refers to the direction from the source corresponding to the gate to the drain corresponding to the gate. Further, since the first contact diffusion region is not provided on the same horizontal plane as the metal plug located above the pixel isolation structure 50, that is, the metal plug located on the same horizontal plane does not include the metal plug located in the dielectric layer, by increasing the lateral width of the first contact diffusion region 14 in the through hole 32, the contact area between the metal plug and the active area can be increased, thereby reducing the contact resistance.
[0043] In the process of the image sensor, part of the pixel isolation structure 50 can be etched to allow the contact diffusion area to diffuse laterally into the etched area of the pixel isolation structure 50, so as to further reduce the pixel unit area by fully utilizing the space of the pixel isolation structure, thereby achieving miniaturization of the pixel size.
[0044] The present invention also includes a method for manufacturing the semiconductor structure, comprising:
[0045] S11: providing a semiconductor substrate, wherein the semiconductor substrate has a photoelectric conversion region, a gate located on the photoelectric conversion region, and active regions distributed on both sides of the gate;
[0046] In some embodiments, the semiconductor substrate may be a single crystal silicon, single crystal germanium or single crystal germanium silicon substrate. In other embodiments, the substrate 10 may also be a substrate formed by doping the above single crystal silicon, single crystal germanium or single crystal germanium silicon substrate with p-type ions or n-type ions.
[0047] S12: forming a dielectric layer above the semiconductor substrate;
[0048] The dielectric layer herein may include more than one dielectric layer, for example, may include one or more combinations of oxide, silicon oxide, nitride, silicon nitride or oxynitride.
[0049] S13: patterning the dielectric layer to generate a through hole partially exposing the active area;
[0050] S14: performing ion implantation on a portion of the active area exposed by the through hole to generate a contact diffusion area;
[0051] The ion type selected for ion implantation here is consistent with the ion type of the active area exposed by the through hole. For example, if the active area is an N-type ion doped area, N-type ions are selected to further implant the active area to form a contact diffusion area.
[0052] S15: depositing metal in the through hole, and the metal reacts with the contact diffusion region to form a metallization, so as to finally generate a metal plug layer.
[0053] The metal may be at least one of nickel, cobalt, aluminum, copper, titanium or tungsten.
[0054] In the embodiment of the present invention, by first covering the dielectric layer and opening a through hole in the dielectric layer to expose the active area, and then performing ion implantation through the through hole, the lateral diffusion range of the contact diffusion area is reduced, thereby further miniaturizing the pixel size.
[0055] The present invention also includes a method for manufacturing the above-mentioned another semiconductor structure, comprising:
[0056] S21: providing a semiconductor substrate, wherein the semiconductor substrate has a photoelectric conversion region, a gate located on the photoelectric conversion region, active regions distributed on both sides of the gate, and a pixel isolation structure distributed between adjacent photoelectric conversion regions;
[0057] In some embodiments, the semiconductor substrate may be a single crystal silicon, single crystal germanium or single crystal germanium silicon substrate. In other embodiments, the substrate 10 may also be a substrate formed by doping the above single crystal silicon, single crystal germanium or single crystal germanium silicon substrate with p-type ions or n-type ions.
[0058] S22: forming a dielectric layer above the semiconductor substrate;
[0059] The dielectric layer herein may include more than one dielectric layer, for example, may include one or more combinations of oxide, silicon oxide, nitride, silicon nitride or oxynitride.
[0060] S23: patterning the dielectric layer and the pixel isolation structure to generate a through hole that partially exposes the active area;
[0061] S24: performing ion implantation on a portion of the active area exposed by the through hole to generate a contact diffusion area;
[0062] The ion type selected for ion implantation here is consistent with the ion type of the active area exposed by the through hole. For example, if the active area is an N-type ion doped area, N-type ions are selected to further implant the active area to form a contact diffusion area.
[0063] What is different from the manufacturing method of the above-mentioned semiconductor structure is that, in this embodiment, while patterning the dielectric layer, part of the pixel isolation structure is etched, and ion implantation is performed on the side of the active area away from the gate, so that the ions diffuse laterally to the etched pixel isolation structure, thereby utilizing part of the area of the pixel isolation structure to further achieve miniaturization of the pixel size.
[0064] S25: depositing metal in the through hole, and the metal reacts with the contact diffusion region to form a metallization, so as to finally generate a metal plug layer.
[0065] The metal may be at least one of nickel, cobalt, aluminum, copper, titanium or tungsten.
[0066] In the present invention, by first covering the dielectric layer and opening a through hole in the dielectric layer to expose the active area, etching part of the pixel isolation structure, and then performing ion implantation through the through hole, the lateral diffusion range of the contact diffusion area is reduced, and the contact diffusion area and the pixel isolation structure are partially overlapped, thereby fully utilizing the area of the pixel unit, thereby further realizing the miniaturization of the pixel size.
[0067] The present application also provides an image sensor, whose semiconductor structure is as described in the above embodiment, by arranging the first contact diffusion region on the side of the active region away from the gate, so that the first contact diffusion region and the active region only partially overlap, so that in the pixel size miniaturization process, even if the ions diffuse laterally, the channel is still less affected, and the ion diffusion does not affect the parasitic capacitance of the source and drain, so that the working efficiency of the transistor is improved, and sufficient connection can be made through the lateral diffusion of ions in the contact diffusion region, thereby reducing the contact resistance between the active region and the metal plug.
[0068] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.
Claims
1. A semiconductor structure of an image sensor, characterized in that: include: A semiconductor substrate having a photoelectric conversion region and a gate located above the photoelectric conversion region; An active region, located in the semiconductor substrate and distributed on both sides of the gate; A contact diffusion region, located in the semiconductor substrate, the contact diffusion region at least comprising a first contact diffusion region, and the first contact diffusion region is located on a side of the active region away from the gate and only partially overlaps with the active region; A dielectric layer, located above the semiconductor substrate and the gate, wherein a through hole is provided in the dielectric layer to at least partially expose the contact diffusion region; The metal plug layer is located in the through hole.
2. The semiconductor structure of the image sensor according to claim 1, wherein: The area of the overlapped region between the first contact diffusion region and the active region is a, and the area of the non-overlapped region between the first contact diffusion region and the active region is b; Among them, a>b.
3. The semiconductor structure of the image sensor according to claim 2, wherein: An ion doping concentration in an overlapping region between the first contact diffusion region and the active region is greater than an ion doping concentration in an overlapping region between the first contact diffusion region and the active region.
4. The semiconductor structure of the image sensor according to claim 1, wherein: The lateral width of the overlapping region between the first contact diffusion region and the active region is n, the lateral width of the active region is m, and the lateral width of the sidewall of the gate is s, wherein mn≥s.
5. The semiconductor structure of the image sensor according to claim 1, wherein: The contact diffusion region further includes a second contact diffusion region, and a vertical projection of the second contact diffusion region is located in the active region.
6. The semiconductor structure of the image sensor according to claim 1, wherein: The gate includes one or more of a transfer gate, a reset gate, a source follower gate, and a row select gate.
7. The semiconductor structure of the image sensor according to claim 1, wherein: The semiconductor structure further includes: a pixel isolation structure located between adjacent photoelectric conversion regions; A vertical projection of the first contact diffusion region partially overlaps with the pixel isolation structure.
8. The semiconductor structure of the image sensor according to claim 7, characterized in that: The lateral width of the first contact diffusion region is always greater than the lateral width of the metal plug located on the same horizontal plane.
9. A method for manufacturing a semiconductor structure of an image sensor according to any one of claims 1 to 6, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has a photoelectric conversion region, a gate located on the photoelectric conversion region, and active regions distributed on both sides of the gate; forming a dielectric layer above the semiconductor substrate; Patterning the dielectric layer to generate a through hole partially exposing the active area; Performing ion implantation on the portion of the active area exposed by the through hole to generate a contact diffusion area; A metal is deposited in the through hole, and the metal reacts with the contact diffusion region to form a metallization, so as to finally generate a metal plug layer.
10. A method for manufacturing a semiconductor structure of an image sensor according to any one of claims 7 or 8, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has a photoelectric conversion region, a gate located on the photoelectric conversion region, an active region distributed on both sides of the gate, and a pixel isolation structure distributed between adjacent photoelectric conversion regions; forming a dielectric layer above the semiconductor substrate; Patterning the dielectric layer and the pixel isolation structure to generate a through hole partially exposing the active area; Performing ion implantation on the portion of the active area exposed by the through hole to generate a contact diffusion area; A metal is deposited in the through hole, and the metal reacts with the contact diffusion region to form a metallization, so as to finally generate a metal plug layer.