Back contact solar cell and preparation method thereof

Abstract

The invention belongs to the technical field of solar photovoltaics, and particularly relates to a back contact solar cell and a preparation method thereof. According to the method, the doped silicon oxide layer in the area needing to be removed is effectively removed by utilizing the strong directionality of dry fluorine etching and the difference of selective etching of the organic polymer and the silicon oxide, so that the doped silicon oxide layer and the doped polycrystalline silicon layer which are arranged below the organic polymer mask area are well protected. According to the invention, the doped silicon oxide layer is removed by adopting the dry fluorine etching, and the dry fluorine etching has good selectivity on the organic polymer mask and the doped silicon oxide layer, so that the loss of wet etching in the transverse direction can be effectively avoided. And the dry fluorine etching is strong in directivity and higher in etching precision. The doped silicon oxide layer in the non-printing area is removed through dry fluorine etching, and meanwhile, a part of the doped polycrystalline silicon layer located below the doped silicon oxide layer is correspondingly etched, so that the etching pressure of the subsequent doped polycrystalline silicon layer is reduced, and the production efficiency is further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar photovoltaics, and in particular relates to a back-contact solar cell and a preparation method thereof. Background Art

[0002] The biggest feature of the back-contact battery is that the emitter and the metal contact are both on the back of the battery. The front of the battery is not affected by the metal electrode, so it has a higher short-circuit current Isc. At the same time, the back of the battery can allow wider metal grid lines to reduce the series resistance Rs, thereby increasing the fill factor FF. And this kind of battery with no obstruction on the front not only has high conversion efficiency, but also looks more beautiful. At the same time, the components of the full back electrode are easier to assemble. However, the preparation method of IBC batteries is relatively complicated and the process steps are cumbersome, requiring multiple steps of graphic and wet cleaning processes.

[0003] In order to simplify the preparation of back-contact cells, it is preferred to use a naturally formed film layer in the process engineering as a patterned mask, such as a borosilicate glass layer (BSG) or a phosphorus silicon glass layer (PSG). This does not require additional mask deposition and removal processes, which helps to simplify the process flow and reduce production costs. During the patterning process, the BSG / PSG film layer needs to be partially removed to form the desired pattern, usually by laser ablation. However, for small-area patterns that need to be retained, since the laser removes a large area of ​​the BSG / PSG film layer, a high-power laser is required, the equipment investment cost is high and the removal efficiency is low.

[0004] The printing mask method is to print an organic polymer mask on the entire BSG / PSG film layer, and remove the remaining BSG / PSG film layer by etching. Since it is only printed on a small target area, and the printing equipment and process are relatively mature, the production efficiency is high, the equipment investment cost is low, and it has an excellent cost-effectiveness.

[0005] At present, the printing mask method usually uses wet etching to remove the remaining BSG / PSG film layer. The height of the printed organic polymer mask is high in the middle and low on both sides. When wet cleaning is used, it will be etched evenly in all directions. The low-height areas on both sides are very easy to be partially corroded due to insufficient etching resistance, resulting in unnecessary pattern loss, further reducing the performance of the battery. Summary of the invention

[0006] The present invention aims to overcome the defects of low efficiency and high manufacturing cost of solar cells in the prior art, and provides a back contact solar cell and a preparation method thereof.

[0007] To achieve the above-mentioned purpose, the present invention is implemented by the following technical solutions: A method for preparing a back contact solar cell comprises the following steps: forming a tunneling layer on the back side of the silicon substrate; forming an amorphous silicon layer on the tunneling layer; converting the amorphous silicon layer into a doped polysilicon layer and forming a doped silicon oxide layer on the surface of the doped polysilicon layer; printing an organic polymer mask on a target area of ​​the doped silicon oxide layer and drying it; Dry fluorine etching removes the doped silicon oxide layer in the non-printed area; removing the organic polymer mask and cleaning; The doped polysilicon layer in the non-printed area is removed.

[0008] The present invention screen prints an organic polymer mask in the target area of ​​the doped silicon oxide layer, and then uses a dry fluorine etching process to remove the doped silicon oxide layer in the non-printed area. By utilizing the strong directionality of dry fluorine etching and the difference in selective etching of organic polymer and silicon oxide, the doped silicon oxide layer in the area to be removed can be conveniently removed, so that the doped silicon oxide layer and the doped polysilicon layer arranged below the organic polymer mask area are well protected. The present invention uses dry fluorine etching to remove the doped silicon oxide layer. Since dry fluorine etching has good selectivity (1~5) for the organic polymer mask and the doped silicon oxide layer, it can effectively avoid the loss of wet etching in the lateral direction. In addition, the dry fluorine etching has strong directionality and higher etching accuracy. On the other hand, the present invention removes the doped silicon oxide layer in the non-printed area by dry fluorine etching, and also correspondingly etches a portion of the doped polysilicon layer located below it, which helps to reduce the etching pressure of the subsequent doped polysilicon layer and further improve production efficiency.

[0009] Preferably, the amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer; the thickness of the amorphous silicon layer is 100-500 nm.

[0010] As a further preference, when the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is of the first conductivity type.

[0011] More preferably, the doped amorphous silicon layer is any one of n-type doping and p-type doping.

[0012] As a further preference, the process for forming the amorphous silicon layer is any one of a physical vapor deposition process (PVD), a low pressure chemical vapor deposition process (LPCVD), and a plasma chemical vapor deposition process (PECVD).

[0013] More preferably, when the amorphous silicon layer is a doped amorphous silicon layer, the process of forming the amorphous silicon layer is an in-situ doping method.

[0014] As a further preference, the equipment for forming the amorphous silicon layer is a LPCVD device.

[0015] More preferably, the tunneling layer and the amorphous silicon layer can be continuously formed on the back side of the silicon substrate using the same LPCVD device.

[0016] By using the same LPCVD device to complete the two processes, the process flow can be simplified, which helps to reduce manufacturing time and thus reduce manufacturing costs. In addition, when the tunneling layer and the amorphous silicon layer are formed using the LPCVD device, the temperature difference between the operating temperature for forming the tunneling layer and the operating temperature for forming the amorphous silicon layer can be set in the range of 0 to 200°C. Preferably, the temperature difference can be in the range of 0 to 100°C. At this time, the operating temperature difference between the two processes is small, which is conducive to reducing the time required to change the operating temperature, thereby further improving the efficiency of continuously forming the tunneling layer and the amorphous silicon layer. At the same time, when the temperature difference is small, the parameter changes of the two process flows are small, which helps to control the temperature to be constant.

[0017] Preferably, the method for converting an amorphous silicon layer into a doped polycrystalline silicon layer comprises the following steps: When the amorphous silicon layer is an intrinsic amorphous silicon layer, high-temperature diffusion and annealing are performed on the intrinsic amorphous silicon layer to form a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer; When the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is annealed to form a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer.

[0018] Preferably, the thickness of the doped silicon oxide layer removed from the non-printing area by dry fluorine etching is 30-60 nm.

[0019] As a further preference, the doped silicon oxide layer contains a dopant, and the dopant is boron or phosphorus.

[0020] Preferably, the doped silicon oxide layer is any one of a boron-doped silicon oxide layer and a phosphorus-doped silicon oxide layer.

[0021] As a further preference, the doped silicon oxide layer is any one of a borosilicate glass layer (BSG) and a phosphosilicate glass layer (PSG).

[0022] Preferably, the printing height of the organic polymer mask is 1-10 μm, and the ratio of the printing width of the organic polymer mask to the designed width of the electrode is 1:1-5.

[0023] The printed pattern of the organic polymer mask corresponds to the electrode design pattern, and the ratio of the printed width of the organic polymer mask to the electrode design width is 1:1~5, which is helpful for the alignment and positioning during the subsequent click printing. The printed height of the organic polymer mask is 1~10μm, because the dry fluorine etching has a selectivity of more than 100 for the organic polymer mask and the doped silicon oxide layer. Therefore, a very thick organic polymer mask is not required to achieve a good protection effect, which helps to save the material cost of the organic polymer mask and reduce the subsequent cleaning pressure.

[0024] Preferably, the method for removing the organic polymer mask comprises the following steps: The organic polymer mask is fully or partially dissolved in the alkaline etchant, and the non-dissolved portion is collected by the filter through overflow cleaning.

[0025] As further preferred, the alkaline etchant is any one or more combinations of NaOH, KOH, and organic alkaline reagents.

[0026] As a further preference, when the organic polymer mask is completely or partially dissolved in the alkaline etchant, the etching temperature is 25-80° C. and the etching time is 1-10 min.

[0027] More preferably, the method for removing the organic polymer mask comprises the following steps: Soak in 1.5%~5% NaOH or KOH solution for 2~5 minutes to completely remove the organic polymer mask.

[0028] As further preferred, the cleaning method after removing the organic polymer mask comprises the following steps: Rinse with deionized water, followed by a mixture of alkaline and hydrogen peroxide or ozone.

[0029] More preferably, the cleaning temperature for the mixed cleaning of alkali and hydrogen peroxide or ozone is 25-80° C. and the cleaning time is 1-5 min.

[0030] More preferably, the alkali in the mixed cleaning process of alkali and hydrogen peroxide or ozone is any one or more combinations of NaOH, KOH, and organic alkali reagents; and the concentration of the alkali is 1-3%.

[0031] Through the above arrangement, deionized water cleaning is used to rinse the residual alkali solution on the surface of the silicon wafer. Then, a mixed cleaning of alkali and hydrogen peroxide or ozone is performed to help remove the residual organic matter or organic groups on the surface of the silicon wafer, and the organic matter is decomposed by the oxidation effect of hydrogen peroxide or ozone.

[0032] Preferably, the process of removing the doped silicon oxide layer in the non-printing area by dry fluorine etching is any one of non-plasma dry fluorine etching and plasma dry fluorine etching.

[0033] Preferably, the reaction gas in the non-plasma dry fluorine etching process is any one of anhydrous ethanol, anhydrous hydrogen fluoride vapor (VHF) containing nitrogen, and XeF2 gas containing water vapor.

[0034] As a further preference, when the reaction gas in the non-plasma dry fluorine etching process is anhydrous hydrogen fluoride vapor (VHF) containing anhydrous ethanol and nitrogen, the method for removing the doped silicon oxide layer in the non-printing area by dry fluorine etching comprises the following steps: Anhydrous hydrogen fluoride vapor (VHF) is introduced and combined with anhydrous ethanol vapor for etching. The reaction gas system is composed of HF, anhydrous ethanol vapor, and N2; among them, HF accounts for 5%~30% of the total volume of the reaction gas system, the reaction temperature is 25℃~60℃, the N2 flow rate is 5~50sccm, and the reaction time is 5s~10min.

[0035] As a further preference, when the reaction gas in the non-plasma dry fluorine etching process is XeF2 gas containing water vapor, the reaction equation for removing the doped silicon oxide layer in the non-printing area by the dry fluorine etching is as follows: 2XeF2+ 2H2O = 2Xe↑+ O2↑+ 4HF.

[0036] Water vapor reacts with XeF2 to generate HF to corrode the doped silicon oxide layer in the non-printing area, and the generated HF will not react with the doped polysilicon layer. The XeF2 etching selectivity ratio for SiO2 / Si is greater than 1000.

[0037] Preferably, the reaction gas in the plasma dry fluorine etching process is any one of CHF3, CF4, a mixed gas of CHF3 and CF4, a mixed gas of CHF3 and O2, a mixed gas of CF4 and O2, and a mixed gas of CHF3, SF6 and He.

[0038] As a further preference, the fluorine-carbon molar ratio (F:C) of the reaction gas in the plasma dry fluorine etching process is ≥4.

[0039] By controlling the fluorine-carbon molar ratio (F:C) in the reaction gas in the plasma dry fluorine etching process to be ≥4, it is helpful to provide a higher fluorine plasma concentration, which significantly improves the etching rate of the doped silicon oxide layer in the non-printed area, and further improves production efficiency. In addition, when the reaction gas in the plasma dry fluorine etching process is CHF3 or CF4, the addition of O2 can consume some carbon atoms, increase the proportion of fluorine active atoms, and promote the etching of SiO2. The addition of He helps to make the doped silicon oxide layer in the non-printed area be corroded more uniformly and consistently. In addition, fluorine plasma not only etches SiO2, but also reacts with silicon to generate SiF4. Therefore, after etching the doped silicon oxide layer in the non-printed area, the fluorine-containing plasma will continue to react with the doped polysilicon layer underneath it, resulting in the removal of part of the doped polysilicon, effectively reducing the pressure of subsequent removal of the doped polysilicon layer.

[0040] Preferably, the method for removing the doped polysilicon layer in the non-printing area comprises the following steps: The doped polysilicon layer in the non-printed area is dissolved in an alkaline etchant containing an additive.

[0041] As further preferred, the alkaline etchant is any one or more combinations of NaOH, KOH, and organic alkaline reagents.

[0042] As a further preference, when the doped polysilicon layer in the non-printing area is dissolved in an alkaline etchant containing an additive, the etching temperature is 50-85° C. and the etching time is 2-6 min.

[0043] Preferably, the silicon substrate is any one of an n-type semiconductor substrate and a p-type semiconductor substrate.

[0044] As a further preference, the material of the silicon substrate is any one of single crystal silicon and polycrystalline silicon.

[0045] Preferably, the thickness of the tunneling layer is 0.5-5 nm.

[0046] Preferably, the material of the tunneling layer is any one or more combinations of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide and silicon oxide.

[0047] Preferably, the process for forming the tunneling layer is any one of a physical vapor deposition process, an atmospheric pressure chemical vapor deposition process (APCVD), a low pressure chemical vapor deposition process (LPCVD), a plasma chemical vapor deposition process (PECVD), a thermal oxidation process, and a chemical oxidation process.

[0048] A back-contact solar cell is prepared using the method for preparing a back-contact solar cell as described above.

[0049] Therefore, the present invention has the following beneficial effects: (1) The present invention screen-prints an organic polymer mask in the target area of ​​the doped silicon oxide layer, and then uses a dry fluorine etching process to remove the doped silicon oxide layer in the non-printed area. By utilizing the strong directionality of dry fluorine etching and the difference in selective etching of organic polymer and silicon oxide, the doped silicon oxide layer in the area to be removed can be easily removed, thereby allowing the doped silicon oxide layer and the doped polysilicon layer disposed under the organic polymer mask area to be well protected; (2) The present invention uses dry fluorine etching to remove the doped silicon oxide layer. Since dry fluorine etching has good selectivity for the organic polymer mask and the doped silicon oxide layer, it can effectively avoid the loss of wet etching in the lateral direction. In addition, dry fluorine etching has strong directionality and higher etching accuracy; (3) The present invention removes the doped silicon oxide layer in the non-printed area by dry fluorine etching, and at the same time, a portion of the doped polysilicon layer located thereunder is correspondingly etched away, which helps to reduce the etching pressure of the subsequent doped polysilicon layer and further improves production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 Schematic diagram of the structure of a back-contact solar cell.

[0051] Figure 2 Schematic diagram of the silicon substrate structure.

[0052] Figure 3 Schematic diagram of the structure for depositing a tunneling layer and an amorphous silicon layer on the back of the battery.

[0053] Figure 4 A schematic diagram of the structure for forming a boron-doped polysilicon layer by diffusion and forming a BSG layer on the surface of the boron-doped polysilicon layer.

[0054] Figure 5 Schematic diagram of the structure of printing an organic polymer mask in the target area of ​​the doped silicon oxide layer.

[0055] Figure 6 Schematic diagram of the structure of removing the BSG layer in the non-printing area by dry fluorine etching.

[0056] Figure 7 Schematic diagram of the structure for removing the organic polymer mask layer.

[0057] Figure 8 Schematic diagram of the structure for wet removal of the doped polysilicon layer in the non-printing area. DETAILED DESCRIPTION

[0058] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments of the specification. Those of ordinary skill in the art will be able to implement the present invention based on these descriptions. In addition, the embodiments of the present invention involved in the following description are generally only embodiments of a part of the present invention, rather than all embodiments. Therefore, based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work should fall within the scope of protection of the present invention.

[0059] Example 1 This embodiment provides a method for preparing a back-contact solar cell.

[0060] A method for preparing a back contact solar cell comprises the following steps: (S.1) Provide a silicon substrate. The structure of the silicon substrate is as follows Figure 2 As shown. The silicon substrate can be an n-type semiconductor substrate or a p-type semiconductor substrate. The material of the silicon substrate is silicon, which can be single crystal silicon or polycrystalline silicon. The front and back of the silicon substrate are consistent with the front and back of the solar cell, the front side is the side facing the sunlight, and the back side is the backlight side. As an implementation method, the silicon substrate needs to be dedamaged and polished first, Figure 2 The silicon substrate shown in FIG. 1 is subjected to double-sided polishing. The polishing is performed using an alkaline solution with an additive. The most preferred silicon substrate in this embodiment is an n-type semiconductor substrate.

[0061] A tunneling layer is formed on the back side of the silicon substrate. The tunneling layer is formed on the back side of the silicon substrate in its entirety. The tunneling layer can produce a tunneling effect, allowing majority carriers to pass through while hindering minority carriers from passing through. As an embodiment, the material of the tunneling layer can be various materials through which majority carriers can tunnel. For example, oxides, nitrides, semiconductors, and conductive polymers. As an embodiment, the material of the tunneling layer can be any one or more combinations of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide. The most preferred material for the tunneling layer in this embodiment is silicon oxide, which has good passivation properties, and carriers can easily tunnel through the silicon oxide layer. As an embodiment, the thickness of the tunneling layer is 0.5 nm to 5 nm.

[0062] As an implementation method, the process for forming the tunnel layer may be a physical vapor deposition process, or a chemical vapor deposition process such as an atmospheric pressure chemical vapor deposition process (APCVD), a low pressure chemical vapor deposition process (LPCVD), or a plasma chemical vapor deposition process (PECVD). As another implementation method, when the tunnel layer is a silicon oxide layer, the process for forming the tunnel layer may also be any one of a thermal oxidation process and a chemical oxidation process.

[0063] As another embodiment, the pressure when forming the tunneling layer can be set lower than the atmospheric pressure to reduce the growth rate of the tunneling layer. For example, when forming the tunneling layer on the back side of the silicon substrate using a thermal oxidation process, the working pressure of the thermal oxidation process can be set lower than the atmospheric pressure. At this time, although the working temperature of the thermal oxidation process is relatively high (600°C or higher), due to the low working pressure, the tunneling layer can maintain a low growth rate, which can significantly reduce the thickness of the tunneling layer. Specifically, the working temperature of the thermal oxidation process can be set to 600-800°C, and the working pressure can be set to 600 Torr or lower, thereby effectively controlling the thickness of the tunneling layer.

[0064] The above-mentioned deposition process or thermal oxidation process for forming the tunnel layer can be performed in a deposition device. In view of the requirement of the process of forming the tunnel layer for a low-pressure environment, the tunnel layer can be manufactured in a low-pressure chemical vapor deposition device.

[0065] (S.2) An amorphous silicon layer is formed on the tunneling layer. The amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer. The thickness of the amorphous silicon layer is 100-500 nm.

[0066] When the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is of the first conductivity type. As another embodiment, the doped amorphous silicon layer is any one of n-type doping and p-type doping.

[0067] As an implementation manner, the process of forming the amorphous silicon layer is any one of a physical vapor deposition process (PVD), a low pressure chemical vapor deposition process (LPCVD), and a plasma chemical vapor deposition process (PECVD).

[0068] As another implementation manner, when the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer may be manufactured by in-situ doping.

[0069] As an implementation method, the device for forming the amorphous silicon layer is a LPCVD device. More preferably, in this embodiment, the same LPCVD device can be used to continuously form the tunneling layer and the amorphous silicon layer on the back side of the silicon substrate. The structure of depositing the tunneling layer and the amorphous silicon layer on the back side of the battery is as follows: Figure 3 shown.

[0070] By using the same LPCVD device to complete the two processes, the process flow can be simplified, which helps to reduce manufacturing time and thus reduce manufacturing costs. In addition, when the tunneling layer and the amorphous silicon layer are formed using the LPCVD device, the temperature difference between the operating temperature for forming the tunneling layer and the operating temperature for forming the amorphous silicon layer can be set in the range of 0 to 200°C. Further preferably, the temperature difference can be in the range of 0 to 100°C. At this time, the operating temperature difference between the two processes is small, which is conducive to reducing the time required to change the operating temperature, thereby further improving the efficiency of continuously forming the tunneling layer and the amorphous silicon layer. At the same time, when the temperature difference is small, the parameter changes of the two process flows are small, which helps to control the temperature to be constant.

[0071] (S.3) Converting the amorphous silicon layer into a doped polysilicon layer and forming a doped silicon oxide layer on the surface of the doped polysilicon layer. As an embodiment, the doped silicon oxide layer is any one of a boron-doped silicon oxide layer and a phosphorus-doped silicon oxide layer.

[0072] As another implementation manner, the doped silicon oxide layer is any one of a borosilicate glass layer (BSG) and a phosphosilicate glass layer (PSG).

[0073] As an implementation method, when the amorphous silicon layer is an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer is subjected to high-temperature boron diffusion and annealing treatment, so that the intrinsic amorphous silicon layer is converted into a boron-doped polysilicon layer, and the outer layer of the boron-doped polysilicon layer is diffused to form a borosilicate glass layer (BSG). The thickness of the diffused borosilicate glass layer (BSG) is 30-60nm. The structure of diffusing to form a boron-doped polysilicon layer and forming a BSG layer on the surface of the boron-doped polysilicon layer is as follows: Figure 4 shown.

[0074] As another embodiment, a silicon substrate is placed in a boron diffusion furnace, and a boron source is used to perform boron diffusion treatment on the back side of the n-type silicon substrate at a temperature of 900 to 1050°C for 1 to 3 hours to form a p-type B-doped polysilicon (i.e., a boron-doped polysilicon layer). The volume proportion of the boron source in the boron diffusion atmosphere in the boron diffusion furnace is 5 to 30%. The boron source can be selected from boron trichloride (BCl3) and / or boron tribromide (BBr3).

[0075] As an implementation method, when the amorphous silicon layer is an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer is subjected to high-temperature phosphorus diffusion and annealing treatment, so that the intrinsic amorphous silicon layer is converted into a phosphorus-doped polysilicon layer, and the outer layer of the phosphorus-doped polysilicon layer is diffused to form a phosphorus-silicate glass layer (PSG). The thickness of the diffused phosphorus-silicate glass layer (PSG) is 20 to 80 nm.

[0076] As another implementation, a silicon substrate is placed in a phosphorus diffusion furnace, and a phosphorus source is used to perform phosphorus diffusion treatment on the back of the n-type silicon substrate at a temperature of 700 to 850°C for 1 to 3 hours to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer). The volume proportion of the phosphorus source in the phosphorus diffusion atmosphere in the phosphorus diffusion furnace is 20%. The phosphorus source can be phosphorus oxychloride (POCl3).

[0077] As an implementation method, when the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer only needs to be annealed to convert the doped amorphous silicon layer into a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer. The doped silicon oxide layer may contain a small amount of dopant, and the type of dopant is boron or phosphorus, depending on the doping type of the doped amorphous silicon layer.

[0078] (S.4) Printing an organic polymer mask in the target area of ​​the doped silicon oxide layer and drying it to form a patterned blocking organic polymer mask layer. The structure of printing an organic polymer mask in the target area of ​​the doped silicon oxide layer is as follows: Figure 5 As shown. The organic polymer mask slurry is a waxy resin material that is resistant to acid corrosion but not resistant to alkali corrosion, such as 0915A from SunChemical Company in the United States. The grid line printing width of the patterned blocking organic polymer mask layer is 100~300μm, and the height after drying is 3~20μm.

[0079] As an implementation method, the printed pattern of the organic polymer mask corresponds to the electrode design pattern, and the ratio of the printed width of the organic polymer mask to the electrode design width is 1:1~5, which is helpful for alignment and positioning during subsequent click printing. The printed height of the organic polymer mask is 1~10μm, because the dry fluorine etching has a selectivity of more than 100 for the organic polymer mask and the doped silicon oxide layer. Therefore, a thick organic polymer mask is not required to achieve a good protection effect, which helps to save the material cost of the organic polymer mask and reduce the subsequent cleaning pressure.

[0080] (S.5) Dry fluorine etching removes the doped silicon oxide layer in the non-printed area.

[0081] As an implementation method, dry fluorine etching is used to remove the borosilicate glass layer (BSG) in the non-printed area. The printed organic polymer mask grid line morphology is high in the middle and low on both sides. The height in the middle is generally above 3μm, and the height at the low sides is only below 1μm.

[0082] During the traditional trench wet etching process, the HF solution will penetrate the lower organic polymer mask and react with the BSG layer. Due to its low surface tension, the HF solution is also prone to erode inward from the interface between the organic polymer mask and the silicon wafer, causing local damage to the edge of the BSG layer. In the subsequent thermal diffusion process, it may not be able to completely block the entry of heterogeneous dopants, causing local leakage of the battery, further affecting the reliability of the battery and components.

[0083] The etching mechanism of the organic polymer mask under dry conditions is mainly bombardment by oxygen atoms and ions. Although the organic polymer mask will also be partially reacted, compared with the thicker BSG layer, the lower parts on both sides of the organic polymer mask can still be effectively protected. The thickness of the BSG layer removed by dry fluorine etching in the non-printing area is 30~60nm.

[0084] As an implementation manner, the process of removing the BSG layer in the non-printing area by dry fluorine etching is any one of non-plasma dry fluorine etching and plasma dry fluorine etching.

[0085] As an implementation manner, the reaction gas in the non-plasma dry fluorine etching process is any one of anhydrous ethanol, anhydrous hydrogen fluoride vapor (VHF) containing nitrogen, and XeF2 gas containing water vapor.

[0086] As another embodiment, when the reaction gas in the non-plasma dry fluorine etching process is anhydrous hydrogen fluoride vapor (VHF) containing anhydrous ethanol and nitrogen, the method for removing the BSG layer in the non-printing area by dry fluorine etching includes the following steps: Anhydrous hydrogen fluoride vapor (VHF) is introduced and combined with anhydrous ethanol vapor for etching. The reaction gas system is composed of HF, anhydrous ethanol vapor, and N2; among them, HF accounts for 5%~30% of the total volume of the reaction gas system, the reaction temperature is 25℃~60℃, the N2 flow rate is 5~50sccm, and the reaction time is 5s~10min.

[0087] As another embodiment, when the reaction gas in the non-plasma dry fluorine etching process is XeF2 gas containing water vapor, the reaction equation for removing the BSG layer in the non-printing area by dry fluorine etching is as follows: 2XeF2+ 2H2O = 2Xe↑+ O2↑+ 4HF.

[0088] Water vapor reacts with XeF2 to generate HF to corrode the BSG layer in the non-printing area, and the generated HF will not react with the doped polysilicon layer. The XeF2 etching selectivity ratio for SiO2 / Si is greater than 1000.

[0089] As an embodiment, the reaction gas in the plasma dry fluorine etching process is any one of CHF3, CF4, a mixed gas of CHF3 and CF4, a mixed gas of CHF3 and O2, a mixed gas of CF4 and O2, and a mixed gas of CHF3, SF6 and He.

[0090] As another embodiment, the fluorine-carbon molar ratio (F:C) in the reaction gas in the plasma dry fluorine etching process is ≥4.

[0091] By controlling the fluorine-carbon molar ratio (F:C) in the reaction gas in the plasma dry fluorine etching process to ≥4, it is helpful to provide a higher fluorine plasma concentration, which significantly increases the etching rate of the doped silicon oxide layer in the non-printed area, further improving production efficiency. In addition, when the reaction gas in the plasma dry fluorine etching process is CHF3 or CF4, the addition of O2 can consume some carbon atoms, increase the proportion of fluorine active atoms, and promote SiO2 etching. The addition of He helps to make the doped silicon oxide layer in the non-printed area be etched more uniformly and consistently.

[0092] In addition, fluorine plasma not only etches SiO2, but also reacts with silicon to generate SiF4. Therefore, after etching away the doped silicon oxide layer in the non-printing area, the fluorine-containing plasma will continue to react with the doped polysilicon layer underneath, resulting in the removal of part of the doped polysilicon. The structure of the BSG layer removed by dry fluorine etching in the non-printing area is shown in the figure. Figure 6 This effectively reduces the pressure of subsequent removal of the doped polysilicon layer.

[0093] As another embodiment, a laser is used to laser ablate the phosphosilicate glass layer (PSG) in the non-printing area above the phosphorus-doped polysilicon layer on the back side of the silicon substrate, and the area of ​​the laser ablation area is 30% to 100% larger than the area of ​​the boron-doped polysilicon area.

[0094] (S.6) Removing the organic polymer mask and cleaning. The structure of removing the organic polymer mask layer is as follows: Figure 7 shown.

[0095] As an embodiment, the organic polymer mask is removed by using an alkaline etchant, the etching temperature is 25-80°C, preferably 45-65°C, and the etching time is 1-10 minutes. The alkaline etchant is any one or more combinations of NaOH, KOH, and organic alkaline reagents. Under this etching parameter, the organic polymer mask can be removed quickly and efficiently.

[0096] As another embodiment, the method for removing the organic polymer mask comprises the following steps: The organic polymer mask is completely or partially dissolved in the alkaline solution, and the insoluble part floats in the solution in the form of strips or flocs and is collected by the filter through overflow cleaning.

[0097] As another embodiment, the method for removing the organic polymer mask comprises the following steps: Soak in 1.5%~5% NaOH or KOH solution for 2~5 minutes to completely remove the organic polymer mask.

[0098] As an embodiment, the cleaning method after removing the organic polymer mask comprises the following steps: Rinse with deionized water, followed by a mixture of alkaline and hydrogen peroxide or ozone.

[0099] As another embodiment, the cleaning temperature of the mixed cleaning of alkali and hydrogen peroxide or ozone is 25-80°C, and the cleaning time is 1-5 minutes. The alkali in the mixed cleaning process of alkali and hydrogen peroxide or ozone is any one or more combinations of NaOH, KOH, and organic alkali reagents. The concentration of the alkali is 1-3%.

[0100] Through the above arrangement, deionized water cleaning is used to rinse the residual alkali solution on the surface of the silicon wafer. Then, a mixed cleaning of alkali and hydrogen peroxide or ozone is performed to help remove the residual organic matter or organic groups on the surface of the silicon wafer, and the organic matter is decomposed by the oxidation effect of hydrogen peroxide or ozone.

[0101] (S.7) Remove the doped polysilicon layer in the non-printing area. The structure of wet removal of the doped polysilicon layer in the non-printing area is as follows: Figure 8 shown.

[0102] As an implementation method, the removal of the doped polysilicon layer in the non-printing area is performed using an alkaline etchant containing an additive, the etching temperature is 50-85°C, and the etching time is 2-6 minutes. The alkaline etchant is any one or more combinations of NaOH, KOH, and organic alkali reagents. Under this etching parameter, the doped polysilicon layer in the non-printing area can be removed quickly and efficiently.

[0103] It should be noted that when a non-plasma dry fluorine etching process is used to remove the BSG layer in the non-printing area, the above-mentioned step of wet removal of the doped polysilicon layer in the non-printing area is required. When a plasma dry fluorine etching process is used to remove the BSG layer in the non-printing area, the BSG layer and the doped polysilicon layer in the non-printing area can be removed in one step (i.e., removed simultaneously), and in this case, the above-mentioned step of wet removal of the doped polysilicon layer in the non-printing area is no longer required.

[0104] In addition, since both the removal of the organic polymer mask and the removal of the doped polysilicon layer in the non-printing area are wet processes, they can be integrated in different slots of the same slot equipment.

[0105] As an implementation method, the doped polysilicon layer in the non-printing area below can be completely removed by selecting appropriate reaction process parameters. Furthermore, the tunneling layer and part of the silicon substrate below the doped polysilicon layer can be removed, for example, the silicon substrate is etched inward by 0.1 to 5 μm. It should be noted that the organic polymer mask is etched due to the bombardment of fluorine-containing plasma. The fluorine-containing plasma has an etching selectivity of 1 to 5 for silicon and the organic polymer mask. The thickness of the organic polymer mask is usually 5 to 30 times that of the doped polysilicon layer, so it does not affect the protective effect of the organic polymer mask. In addition, there is a BSG layer of a certain thickness below the coverage area of ​​the organic polymer mask. The etching selectivity of the BSG layer to silicon is usually >20, so it can also play a good etching protection role.

[0106] As an implementation method, a chain acid polishing (HF+HNO3) device is used to remove silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass on the front side of the silicon substrate, and then the silicon substrate is textured on the front side using NaOH or KOH solution in a tank cleaning machine. The back side will not be etched by alkali due to the protective effect of the phosphosilicate glass layer (PSG) and the borosilicate glass layer (BSG), and finally cleaned with a mixed solution of HF and HCl.

[0107] As an implementation method, an aluminum oxide layer (AlOx) is prepared on the front and back sides of a silicon substrate respectively by ALD, and the thickness of the aluminum oxide layer is 2-10 nm.

[0108] As an embodiment, a silicon nitride (SiNx) passivation anti-reflection layer is prepared on the front and back sides of a silicon substrate by using a tubular PECVD method, wherein the thickness of the passivation anti-reflection layer on the front side of the silicon substrate is 50-100 nm, and the thickness of the passivation anti-reflection layer on the back side of the silicon substrate is 50-100 nm.

[0109] As an implementation mode, a laser is used to open a hole in the passivation anti-reflection layer on the back of the silicon substrate to form a first electrode contact hole connected to the boron-doped polysilicon layer and a second electrode contact hole connected to the phosphorus-doped polysilicon layer.

[0110] As an implementation mode, a first electrode is formed at the first electrode contact hole by screen printing, and a second electrode is formed at the second electrode contact hole. The first electrode is connected to the boron-doped polysilicon layer, and the second electrode is connected to the phosphorus-doped polysilicon layer.

[0111] This embodiment also provides a back-contact solar cell.

[0112] The structure of a back contact solar cell is as follows Figure 1 As shown. The back contact solar cell is prepared by the method for preparing the back contact solar cell as described above. The positive electrode and the negative electrode of the back contact solar cell are both arranged on the back side, and the positive electrode and the negative electrode are respectively in contact with the doped polysilicon layer below through the opening of the back passivation layer, and the doped polysilicon layer is arranged on the tunneling layer on the back side.

[0113] The above description is only a detailed description of the preferred embodiments and principles of the present invention. For ordinary technicians in this field, according to the ideas provided by the present invention, there will be changes in the specific implementation methods, and these changes should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a back contact solar cell, characterized in that: The following steps are involved: forming a tunneling layer on the back side of the silicon substrate; forming an amorphous silicon layer on the tunneling layer; converting the amorphous silicon layer into a doped polysilicon layer and forming a doped silicon oxide layer on the surface of the doped polysilicon layer; printing an organic polymer mask on a target area of ​​the doped silicon oxide layer and drying it; Dry fluorine etching removes the doped silicon oxide layer in the non-printed area; removing the organic polymer mask and cleaning; The doped polysilicon layer in the non-printed area is removed.

2. The method for preparing a back contact solar cell according to claim 1, characterized in that: The amorphous silicon layer is any one of an intrinsic amorphous silicon layer and a doped amorphous silicon layer; the thickness of the amorphous silicon layer is 100-500 nm.

3. The method for preparing a back contact solar cell according to claim 1, characterized in that: The method for converting an amorphous silicon layer into a doped polysilicon layer comprises the following steps: When the amorphous silicon layer is an intrinsic amorphous silicon layer, high-temperature diffusion and annealing are performed on the intrinsic amorphous silicon layer to form a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer; When the amorphous silicon layer is a doped amorphous silicon layer, the doped amorphous silicon layer is annealed to form a doped polysilicon layer, and the surface of the doped polysilicon layer is oxidized to form a doped silicon oxide layer.

4. The method for preparing a back contact solar cell according to claim 1 or 3, characterized in that: The doped silicon oxide layer is any one of a boron-doped silicon oxide layer and a phosphorus-doped silicon oxide layer.

5. The method for preparing a back contact solar cell according to claim 1, characterized in that: The printing height of the organic polymer mask is 1-10 μm, and the ratio of the printing width of the organic polymer mask to the designed width of the electrode is 1:1-5.

6. The method for preparing a back contact solar cell according to claim 1, characterized in that: The process of removing the doped silicon oxide layer in the non-printing area by dry fluorine etching is any one of non-plasma dry fluorine etching and plasma dry fluorine etching.

7. The method for preparing a back contact solar cell according to claim 6, characterized in that: The reaction gas in the non-plasma dry fluorine etching process is any one of anhydrous hydrogen fluoride vapor and XeF2 gas containing water vapor.

8. The method for preparing a back contact solar cell according to claim 6, characterized in that: The reaction gas in the plasma dry fluorine etching process is any one of CHF3, CF4, a mixed gas of CHF3 and CF4, a mixed gas of CHF3 and O2, a mixed gas of CF4 and O2, and a mixed gas of CHF3, SF6 and He.

9. The method for preparing a back contact solar cell according to claim 1, characterized in that: The material of the tunneling layer is any one or more combinations of silicon oxynitride, silicon carbide, silicon nitride, aluminum oxide, and silicon oxide.

10. A back-contact solar cell prepared by the method for preparing a back-contact solar cell according to any one of claims 1 to 9.

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