Fuse unit, memory, working method of memory and working method of monitoring circuit

Abstract

The invention discloses a fuse unit, a memory, a working method of the memory and a working method of a monitoring circuit, and the fuse unit comprises a first fuse which is provided with a first end and a second end, and the second end is grounded; the first amplification unit comprises a first PNP triode and a first NPN triode, the first PNP triode is provided with a first emitting electrode, a first collecting electrode and a first base electrode, the first emitting electrode is connected with the first power supply end, and the first collecting electrode is used for outputting a current signal to the first end; the first NPN triode is provided with a second emitter, a second collector and a second base, the second collector is connected with the first base, the second emitter is connected with the first end, and the second base is used for inputting a first trigger signal. According to the fuse unit, input current is amplified by multiple times, and high fusing current is obtained while the area of the fuse unit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a fuse unit, a memory, a working method of the memory, and a working method of a monitoring circuit. Background Art

[0002] In memory systems, fuse units play a very important role. In traditional fuse units, hundreds of N-type metal oxide semiconductors (NMOS) are connected in parallel to obtain a larger fuse current. In addition, with the development of science and technology, the monitoring of weak current in precision systems is becoming more and more indispensable.

[0003] However, in the prior art, the area of ​​a fuse unit in which multiple metal oxide semiconductors are connected in parallel is too large, and it cannot be applied to weak current monitoring, which has great limitations in application. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a fuse unit, a memory, a working method of the memory and a working method of a monitoring circuit, which reduce the area of ​​the fuse unit and play a role in monitoring weak current.

[0005] To solve the above technical problems, the technical solution of the present invention proposes a fuse unit, including: a first fuse, having a first end and a second end, the second end being grounded; a first amplifying unit, the first amplifying unit including: a first PNP transistor and a first NPN transistor, the first PNP transistor having a first emitter, a first collector and a first base, the first emitter being connected to the first power supply end, and the first collector being used to output a current signal to the first end; the first NPN transistor having a second emitter, a second collector and a second base, the second collector being connected to the first base, the second emitter being connected to the first end, and the second base being used to input a first trigger signal.

[0006] Optionally, it also includes: a second resistor, the second resistor is connected between the first collector and the first end; and a first resistor, the two ends of the first resistor are respectively connected to the first emitter and the first base.

[0007] Optionally, it also includes: a first MOS tube, the third end of the first MOS tube is connected to the second base, the fourth end of the first MOS tube is used to input a first trigger signal, the third end is one of the source and the drain of the first MOS tube, the fourth end is the other of the source and the drain of the first MOS tube, and the first gate of the first MOS tube is used to input a first switching signal; when the first MOS tube is a PMOS, the third end is the drain of the PMOS tube, and the fourth end is the source of the PMOS tube; when the first MOS tube is an NMOS, the third end is the source of the NMOS tube, and the fourth end is the drain of the NMOS tube.

[0008] Optionally, the method further includes: the second base is connected to the first device to be monitored.

[0009] Optionally, the method further includes: the first base is connected to a second device to be monitored.

[0010] The technical solution of the present invention also provides another fuse unit, including: a second fuse having a fifth end and a sixth end, the sixth end being grounded; a second amplifying unit, the second amplifying unit including: a second PNP transistor and a second NPN transistor, the second PNP transistor having a third emitter, a third collector and a third base, the third emitter being connected to the second power supply end, and the third base being used to input a second trigger signal; the second NPN transistor having a fourth emitter, a fourth collector and a fourth base, the fourth base being connected to the third collector, the fourth emitter being connected to the fifth end, and the fourth collector being used to input a current signal from the second power supply end.

[0011] Optionally, it also includes: a third resistor, which is connected between the third collector and the fifth terminal; and a fourth resistor, which is connected between the third emitter and the fourth collector.

[0012] Optionally, it also includes: a second MOS tube, the seventh end of the second MOS tube is connected to the third base, the eighth end of the second MOS tube is used to input a second trigger signal, the seventh end is one of the source and the drain of the second MOS tube, the eighth end is the other of the source and the drain of the second MOS tube, and the second gate of the second MOS tube is used to input a second switching signal; when the second MOS tube is a PMOS, the seventh end is the drain of the PMOS tube, and the eighth end is the source of the PMOS tube; when the second MOS tube is an NMOS, the seventh end is the source of the NMOS tube, and the eighth end is the drain of the NMOS tube.

[0013] Correspondingly, the technical solution of the present invention further provides a memory, comprising: a plurality of fuse units.

[0014] Correspondingly, the technical solution of the present invention also provides a working method of a memory, including: inputting a first switching signal at a first gate of a first MOS tube, and when the voltage value of the first switching signal is greater than a threshold voltage value of the first MOS tube, the first MOS tube is turned on; inputting a first trigger signal at a fourth end of the first MOS tube, and when the current value of the first trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the blowing current, the first fuse is blown and logic 1 is written; when the current value of the first trigger signal is less than the threshold current, the current flowing through the first fuse is less than the blowing current, the first fuse is not blown and logic 0 is written.

[0015] Optionally, the threshold current is the threshold current of the first NPN transistor; the threshold current of the first NPN transistor is 10 μA; and the magnitude of the fuse current is 50 mA.

[0016] Optionally, the voltage range of the first power supply terminal is 1.0V to 1.8V; the threshold voltage of the first MOS tube is 0.75V; and the voltage value of the first trigger signal is greater than 0.1V.

[0017] The technical solution of the present invention also provides another memory, including: a plurality of fuse units.

[0018] The technical solution of the present invention also provides another working method of a memory, comprising: inputting a second switching signal to a second gate of a second MOS tube, and when the voltage value of the second switching signal is greater than the threshold voltage value of the second MOS tube, the second MOS tube is turned on; inputting a second trigger signal to an eighth end of the second MOS tube, and when the current value of the second trigger signal is greater than the threshold current, the current flowing through the second fuse is greater than the fusing current, the second fuse is blown and logic 1 is written; when the current value of the second trigger signal is less than the threshold current, the current flowing through the second fuse is less than the fusing current, the second fuse is not blown and logic 0 is written.

[0019] Optionally, the threshold current is the threshold current of the second PNP transistor; the threshold current of the second PNP transistor is 10 μA; and the magnitude of the fuse current is 50 mA.

[0020] Optionally, the voltage range of the second power supply terminal is 1.0V to 1.8V; the threshold voltage of the second MOS tube is 0.75V; and the voltage value of the second trigger signal is greater than 0.1V.

[0021] Correspondingly, the technical solution of the present invention also provides a working method of a monitoring circuit, wherein the monitoring circuit includes the fuse unit and a first device to be monitored, and the first device to be monitored is connected to the second base, and is characterized in that it includes: the first device to be monitored inputs a third trigger signal to the second base, and when the current value of the third trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the blowing current, and the first fuse blows.

[0022] Optionally, the threshold current is the threshold current of the first NPN transistor; the threshold current of the first NPN transistor is 10 μA; and the magnitude of the fuse current is 50 mA.

[0023] The technical solution of the present invention also provides another working method of a monitoring circuit, wherein the monitoring circuit includes the fuse unit and a second monitored device, wherein the second monitored device is connected to the first base, and is characterized in that it includes: the second monitored device inputs a fourth trigger signal to the first base, and when the current value of the fourth trigger signal is greater than a threshold current, the current flowing through the first fuse is greater than the blowing current, and the first fuse blows.

[0024] Optionally, the threshold current is the threshold current of the first PNP transistor; the threshold current of the first PNP transistor is 10 μA; and the magnitude of the fuse current is 50 mA.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the fuse unit provided by the technical solution of the present invention, the second base is connected to the first collector, and the second collector is connected to the first base, so the first PNP transistor and the first NPN transistor are connected in series to form a common emitter amplifier circuit, so that the input current is amplified several times, thereby reducing the area of ​​the fuse unit and obtaining a high fuse current.

[0027] Furthermore, when the second base is connected to the first monitored device and a weak current is input at the second base terminal, the first PNP transistor and the first NPN transistor greatly amplify the weak current, and the presence of the weak current is monitored by determining whether the greatly amplified weak current blows the first fuse, thereby protecting important devices in the circuit.

[0028] The memory provided by the technical solution of the present invention includes a plurality of fuse units. Since the area of ​​a single fuse unit is small, the area of ​​the memory is small, which reduces the process cost and improves the integration of the device.

[0029] In the working method of the monitoring circuit provided by the technical solution of the present invention, the first PNP transistor and the first NPN transistor greatly amplify the weak current, and monitor the existence of the weak current by judging whether the current amplified by the transistor blows the first fuse to protect important components in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a structural schematic diagram of an embodiment of a fuse unit;

[0031] Figure 2 is a structural schematic diagram of a fuse unit according to an embodiment of the present invention;

[0032] Figure 3 is a structural schematic diagram of another fuse unit according to an embodiment of the present invention;

[0033] Figure 4 is a structural schematic diagram of another fuse unit according to an embodiment of the present invention;

[0034] Figure 5 is a structural schematic diagram of another fuse unit according to an embodiment of the present invention;

[0035] Figure 6 is a schematic flow chart of a working method of a memory according to an embodiment of the present invention;

[0036] Figure 7 is a flowchart of another memory operation method according to an embodiment of the present invention;

[0037] Figure 8 is a flow chart of a working method of a monitoring circuit according to an embodiment of the present invention;

[0038] Fig. 9 It is a flowchart of another working method of a monitoring circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] As described in the background art, in the prior art, the area of ​​the fuse unit is too large and cannot be applied to weak current monitoring, which has great limitations in application.

[0040] Figure 1 The present invention is a structural schematic diagram of an embodiment of a fuse unit.

[0041] Please refer to Figure 1The fuse unit includes: a fuse 100, the fuse 100 has a first end a and a second end b, the second end b is connected to the power supply end Vpp; a plurality of MOS tubes 101, the MOS tube 101 has a drain end, a source end and a control end, the drain end is connected to the first end a, the source end is connected to the ground end Vss, the control end Vg is connected to the gate end, and the MOS tubes 101 are connected in parallel.

[0042] When multiple MOS tubes 101 are connected in parallel to obtain a sufficiently large fusing current, the area of ​​the fuse unit is too large due to the excessive number of parallel MOS tubes 101, which will increase the area of ​​the memory; and the fuse unit is a plurality of MOS tubes 101 connected in parallel to obtain a large fusing current, which cannot monitor weak currents and cannot be used in precision systems.

[0043] In order to solve the above problems, the present invention provides a fuse unit, a memory, a working method of the memory, and a working method of a monitoring circuit, which reduces the area of ​​the fuse unit and can monitor weak current.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figure 2 It is a structural schematic diagram of a fuse unit according to an embodiment of the present invention.

[0046] Please refer to Figure 2 The fuse unit includes: a first fuse F1 having a first end a and a second end b, and the second end b is grounded.

[0047] The first fuse F1 is a programmable fuse, and the programmable fuse stores information according to whether the electric fuse is blown by current.

[0048] The resistance range of the first fuse F1 is 70Ω to 120Ω.

[0049] The fuse unit includes: a first amplifying unit, the first amplifying unit includes: a first PNP transistor PNP1 and a first NPN transistor NPN1, the first PNP transistor PNP1 has a first emitter e11, a first collector c11 and a first base b11, the first emitter e11 is connected to the first power supply terminal Vpp1, and the first collector c11 is used to output a current signal to the first terminal a; the first NPN transistor NPN1 has a second emitter e21, a second collector c21 and a second base b21, the second collector c21 is connected to the first base b11, the second emitter e21 is connected to the first terminal a, and the second base b21 is used to input a first trigger signal.

[0050] The on-state voltage of the first PNP transistor PNP1 is in the range of 0.3V to 0.6V.

[0051] The on-state voltage of the first NPN transistor NPN1 is in the range of 0.3V to 0.6V.

[0052] The current I1 of the first power supply terminal Vpp1 is divided into two branch currents I2 and I3. The current I2 flows through the first resistor R1, and the current I3 flows into the first PNP transistor PNP1 through the first emitter e11. The current I1=I2+I3. The current I3 is divided into the current I flowing through the first base b11 through the first PNP transistor PNP1. 3-1 and the current I flowing through the first collector c11 3-2 , said I3=I 3-1 +I 3-2 Current I 3-1 The current I2 flowing through the first resistor is combined into a current I4, where I4 = I 3-1 +I2, current I4 flows into the first NPN transistor NPN1 through the second collector c21. Current I 3-2 The current I flows through the second base b21. 3-2-2 The current I flowing through the second resistor R2 3-2-1 , the I 3-2 =I 3-2-2 +I 3-2-1 .

[0053] The first NPN transistor NPN1 and the first PNP transistor PNP1 both have the function of amplifying current, and the first NPN transistor NPN1 and the first PNP transistor PNP1 are connected in series, so as to amplify the input current twice. Specifically, in this embodiment, the I 3-2 =βI 3-1 , said I4=β(I 3-2-2 +I 5-1 ), where 60<β<80.

[0054] In this embodiment, on the one hand, the secondary amplification of the two transistors in series can obtain a larger fuse current, which overcomes the problem of too many parallel MOS tubes resulting in an excessively large fuse unit area in the method of connecting multiple MOS tubes in parallel to obtain a larger fuse current; on the other hand, the cost of the transistor is relatively low, which saves manufacturing costs while reducing the fuse unit area.

[0055] Specifically, in this embodiment, when the parasitic resistances of the first NPN transistor NPN1 and the first PNP transistor PNP1 are both 0, the maximum current in the circuit is: the ratio of the voltage value of the first power supply terminal Vpp1 to the resistance value of the first fuse F1.

[0056] Specifically, in this embodiment, the voltage range of the first power supply terminal Vpp1 is 1.0V to 1.8V.

[0057] The fuse unit includes: a second resistor R2, which is connected between the first collector c11 and the first end a; and a first resistor R1, whose two ends are respectively connected to the first emitter e11 and the first base b11.

[0058] The second resistor R2 is a bias resistor, and the function of the second resistor R2 is to share the voltage in the circuit and protect the first PNP transistor PNP1.

[0059] The resistance range of the second resistor R2 is 80 kΩ to 120 kΩ.

[0060] The first resistor R1 is a bias resistor, and the function of the first resistor R1 is to share the voltage in the circuit and protect the first NPN transistor NPN1.

[0061] The resistance range of the first resistor R1 is 100Ω to 500Ω.

[0062] In this embodiment, the fuse unit includes: a first MOS tube, a third end x of the first MOS tube is connected to the second base b21, a fourth end y of the first MOS tube is used to input a first trigger signal, the third end x is one of the source and the drain of the first MOS tube, the fourth end y is the other of the source and the drain of the first MOS tube, and the first gate of the first MOS tube is used to input a first switching signal; when the first MOS tube is a PMOS, the third end x is the drain of the PMOS tube, and the fourth end y is the source of the PMOS tube; when the first MOS tube is an NMOS, the third end x is the source of the NMOS tube, and the fourth end y is the drain of the NMOS tube.

[0063] When the voltage value Vg1 of the first switch signal is greater than the threshold voltage value of the first MOS transistor, the first MOS transistor is turned on. The first gate of the first MOS transistor plays the role of controlling the switch.

[0064] Specifically, in this embodiment, the threshold voltage of the first MOS tube is 0.75V.

[0065] When the product of the current value I5 of the first trigger signal and the second resistor R2 is greater than the conduction voltage of the first PNP transistor PNP1 and the first NPN transistor NPN1, the first PNP transistor PNP1 and the first NPN transistor NPN1 are turned on. The current I1 of the first power supply terminal Vpp1 is divided into two branch currents I2 and I3. The current I2 flows through the first resistor R1, and the current I3 flows into the first PNP transistor PNP1 through the first emitter e11, and the current I1=I2+I3. The current I3 is divided into the current I flowing through the first base b11 through the first PNP transistor PNP1. 3-1 and the current I flowing through the first collector c11 3-2 , said I3=I 3-1 +I 3-2 And the I 3-2 =βI 3-1 , where 60<β<80. Current I 3-1 The current I4 is combined with the current I2 flowing through the first resistor R1 to form a current I4, and the current I4 flows into the first NPN transistor NPN1 through the second collector c21. 3-1 +I2. Current I 3-2 The current I flows through the second base b21. 3-2-2 The current I flowing through the second resistor R2 3-2-1 , the I 3-2 =I 3-2-1 +I 3-2-2 The current I5 of the first trigger signal is input, and the current I5 is divided into the current I flowing through the first NPN transistor NPN1. 5-1 and the current I flowing through the second resistor 5-2 , said I5=I 5-1 +I 5-2 , said I4=β(I 3-2-2 +I 5-1 ), where 60<β<80. Current I4, current I 3-2-2 And the current I 5-1 The current I6 is collected into I4+I 3-2-2 +I 5-1 , current I 3-2-1 、Current I 5-2 And the current I6 is integrated into the current I7, where I7=I 3-2-1 +I 5-2 +I6, current I7 flows through the first fuse F1 and then goes to ground.

[0066] The I7=I1+I5, where I5 ​​is the current of the first trigger signal. The magnitude of I5 is very small, generally in microamperes (μA). The current I1 is very large, which can reach several hundred milliamperes (mA). Therefore, the current I7 flowing through the first fuse F1 is much larger than the current I5 of the first trigger signal.

[0067] The current I5 of the first trigger signal may be a transient current. When the product of I5 and R2 is greater than the threshold voltage of the first NPN transistor NPN1, the first fuse F1 is blown.

[0068] When the first MOS tube is a PMOS, the drain of the PMOS tube is connected to the second base b21; the source of the PMOS tube is used to input the first trigger signal.

[0069] When the first MOS tube is an NMOS, the source of the NMOS tube is connected to the second base b21; the drain of the NMOS tube is used to input the first trigger signal.

[0070] In the fuse unit described in this embodiment, the second base b21 is connected to the first collector c11 and the second collector c21 is connected to the first base b11, so the first PNP transistor PNP1 and the first NPN transistor NPN1 are connected in series to form a common emitter amplifier circuit, so that the input current is amplified several times, thereby reducing the area of ​​the fuse unit and obtaining a high fuse current.

[0071] Figure 3 It is a schematic structural diagram of another fuse unit according to an embodiment of the present invention.

[0072] Please refer to Figure 3 , the fuse unit includes: the second base b22 is connected to the first monitored device D1.

[0073] When the second base b22 is connected to the first device to be monitored D1, the weak current flowing through the first device to be monitored D1 can be monitored, thereby protecting precision instruments.

[0074] When the weak current I flowing through the first monitored device D1 12 When the current is small, it is difficult to detect the existence of the current, which is not conducive to the protection of precision instruments. In this embodiment, the third trigger signal is input to the second base b22. When the weak current I 12 After two amplifications by the first NPN transistor NPN1 and the first PNP transistor PNP1, a larger current can be obtained. By judging whether the amplified current blows the first fuse F1 and monitoring whether a weak current flows through the first monitored device D1, it is beneficial to protect precision devices.

[0075] In this embodiment, the fusing current of the first fuse F1 is 50 mA.

[0076] The on-state voltage of the first PNP transistor PNP1 is in the range of 0.3V to 0.6V.

[0077] The on-state voltage of the first NPN transistor NPN1 is in the range of 0.3V to 0.6V.

[0078] When the current value of the third trigger signal I 12 When the product of the current I8 and the second resistor R2 is greater than the on-state voltage of the first PNP transistor PNP1 and the first NPN transistor NPN1, the first PNP transistor PNP1 and the first NPN transistor NPN1 are turned on. The current I8 at the first power supply terminal Vpp1 is divided into I9 and I 10 There are two branch currents, current I9 flows through the first resistor R1, and current I 10 Flows into the first PNP transistor PNP1 through the first emitter e12, and I8=I9+I 10 Current I 10 The current I is divided into the current I flowing through the first base b12 by the first PNP transistor PNP1. 10-1 and the current I flowing through the first collector c12 10-2 , the I 10 =I 10-1 +I 10-2 And the I 10-2 =βI 10-1 , where 60<β<80. Current I 10-1 The current I9 flowing through the first resistor is combined into a current I 11 , current I 11 The current flows into the first NPN transistor NPN1 through the second collector c22. 11 =I9+I 10-1 Current I 10-2 The current I flows through the second base b22. 10-2-2 The current I flowing through the second resistor R2 10-2-1 , the I 10-2 =I 10-2-2 +I 10-2-1 The weak current I of the third trigger signal 12 Input, current I 12 The current I flows through the first NPN transistor NPN1. 12-1 and the current I flowing through the second resistor R2 12-2 , the I 12 =I 12-1 +I 12-2 , the I 11 =β(I 10-2-2 +I 12-1 ), where 60<β<80. Current I 11 、Current I 10-2-2 And the current I 12-1 The current I 13 , the I 13 =I11 +I 10-2-2 +I 12-1 , current I 10-2-1 、Current I 12-2 And the current I 13 The current I 14 , the I 14 =I 10-2-1 +I 12-2 +I 13 , current I 14 The current flows through the first fuse F1 and then is grounded.

[0079] I 14 =I8+I 12 , the I 12 is the current of the third trigger signal, I 12 The order of magnitude is very small, generally in microamperes (μA), and the current I8 is very large, which can reach several hundred milliamperes (mA). Therefore, the current I flowing through the first fuse F1 is 14 The current I is much larger than the third trigger signal 12 .

[0080] The current I of the third trigger signal 12 Is a transient weak current. When I 12 When the product of R2 is greater than the threshold voltage of the first NPN transistor NPN1, the first fuse F1 is blown.

[0081] In the fuse unit of this embodiment, the first PNP transistor PNP1 and the first NPN transistor NPN1 convert the weak current I 12 The weak current is greatly amplified, and the existence of the weak current is monitored by judging whether the weak current after being greatly amplified has blown the first fuse F1, so as to protect important components in the circuit.

[0082] Figure 4 It is a structural schematic diagram of another fuse unit according to an embodiment of the present invention.

[0083] Please refer to Figure 4 , the fuse unit includes: the first base b12 is connected to the second monitored device D2.

[0084] When the first base b12 is connected to the second monitored device D2, the weak current flowing through the second monitored device D2 can be monitored, thereby protecting precision instruments.

[0085] When the weak current I flowing through the second monitored device D2 16-1 When the current is small, it is difficult to detect the existence of the current, which is not conducive to the protection of precision instruments. In this embodiment, the fourth trigger signal is input to the first base b12. When the weak current I 16-1After two amplifications by the first NPN transistor NPN1 and the first PNP transistor PNP1, a larger current can be obtained. By judging whether the amplified current blows the first fuse F1 and monitoring whether a weak current flows through the second monitored device D2, it is beneficial to protect precision devices.

[0086] In this embodiment, the fusing current of the first fuse F1 is 50 mA.

[0087] The on-state voltage of the first PNP transistor PNP1 is in the range of 0.3V to 0.6V.

[0088] The on-state voltage of the first NPN transistor NPN1 is in the range of 0.3V to 0.6V.

[0089] When the current value of the fourth trigger signal I 16-1 When the product of the current I of the first power supply terminal Vpp1 is greater than the turn-on voltage of the first PNP transistor PNP1 and the first NPN transistor NPN1, the first PNP transistor PNP1 and the first NPN transistor NPN1 are turned on. 15 Divide into I 16 and I 17 Two branch currents, current I 16 Flowing through the first resistor R1, the current I 17 Flows into the first PNP transistor PNP1 through the first emitter e12. 15 =I 16 +I 17 Current I 16 The current I is divided by the first resistor R1 into a current I flowing through the second monitored device D2 16-1 , the current I flowing through the first base b12 16-2 and the current I flowing through the second collector c22 16-3 Current I 17 and the current I flowing through the first base b12 16-2 The current I 18 , current I 18 The current I flows through the second resistor. 18-2 and the current I flowing through the second base b22 18-1 Current I 16-3 With current I 18-1 The current I flowing through the second emitter 19 , the I 19 =I 18-1 +I 16-3 Current I 19 The current I flowing through the second resistor R2 18-2 The current is combined into current I 20 , the I20 =I 18-2 +I 19 Current I 20 The current flows through the first fuse F1 and then is grounded.

[0090] The current I of the fourth trigger signal 16-1 Is a transient weak current. When I 16-1 When the product of the voltage and R1 is greater than the threshold voltage of the first NPN transistor NPN1, the first fuse F1 is blown.

[0091] In the fuse unit of this embodiment, the first PNP transistor PNP1 and the first NPN transistor NPN1 convert the weak current I 16-1 The weak current is greatly amplified, and the existence of the weak current is monitored by judging whether the weak current after being greatly amplified has blown the first fuse F1, so as to protect important components in the circuit.

[0092] Figure 5 It is a structural schematic diagram of another fuse unit according to an embodiment of the present invention.

[0093] Please refer to Figure 5 The fuse unit includes: a second fuse F2 having a fifth end c and a sixth end d, and the sixth end d is grounded.

[0094] The second fuse F2 is a programmable fuse, and the programmable fuse stores information according to whether the electric fuse is blown by current.

[0095] The resistance range of the second fuse F2 is 70Ω to 120Ω.

[0096] The fuse unit includes: a second amplifying unit, the second amplifying unit includes: a second PNP transistor PNP2 and a second NPN transistor NPN2, the second PNP transistor PNP2 has a third emitter e31, a third collector c31 and a third base b31, the third emitter e31 is connected to the second power supply terminal Vpp2, and the third base b31 is used to input a second trigger signal; the second NPN transistor NPN2 has a fourth emitter e41, a fourth collector c41 and a fourth base b41, the fourth base b41 is connected to the third collector c31, the fourth emitter e41 is connected to the fifth terminal c, and the fourth collector c41 is used to input a current signal from the second power supply terminal Vpp2.

[0097] The on-state voltage of the second PNP transistor PNP2 is in the range of 0.3V to 0.6V.

[0098] The on-state voltage of the second NPN transistor NPN2 is in the range of 0.3V to 0.6V.

[0099] The current I 21 Divide into I 22 and I 23 The two branch currents, the I 21 =I 22 +I 23 , current I 22 The current I flows through the third emitter e31 into the second PNP transistor PNP2 and is divided into a current I flowing through the third base b31. 22-1 and the current I flowing through the third collector c31 22-2 , the I 22 =I 22-1 +I 22-2 , current I 22-1 The current I flowing through the collector c41 of the second NPN transistor NPN2 is diverted. 22-1-2 , current I 22-2 The current I flowing through the base b41 of the second NPN transistor NPN2 is diverted. 22-2-1 .

[0100] The second PNP transistor PNP2 and the second NPN transistor NPN2 both have the function of amplifying current, and the second NPN transistor NPN2 and the second PNP transistor PNP2 are connected in series, so as to perform secondary amplification on the input current. Specifically, in this embodiment, the I 22-2 =βI 22-1 , the I 22-1-2 +I 23-2 =βI 22-2-1 , where 60<β<80.

[0101] In this embodiment, on the one hand, the secondary amplification of the two transistors in series can obtain a larger fuse current, which overcomes the problem of too many parallel MOS tubes resulting in an excessively large fuse unit area in the method of connecting multiple MOS tubes in parallel to obtain a larger fuse current; on the other hand, the cost of the transistor is relatively low, which saves manufacturing costs while reducing the fuse unit area.

[0102] Specifically, in this embodiment, when the parasitic resistances of the second NPN transistor NPN2 and the second PNP transistor PNP2 are both 0, the maximum current in the circuit is: the ratio of the voltage value of the second power supply terminal Vpp2 to the resistance value of the second fuse F2.

[0103] Specifically, in this embodiment, the voltage range of the second power supply terminal Vpp2 is 1.0V to 1.8V.

[0104] The fuse unit includes: a third resistor R3, which is connected between the third collector c31 and the fifth end c; and a fourth resistor R4, which is connected between the third emitter e31 and the fourth collector c41.

[0105] The third resistor R3 is a bias resistor, and the function of the third resistor R3 is to share the voltage in the circuit and protect the second PNP transistor PNP2.

[0106] The resistance range of the third resistor R3 is 100Ω to 500Ω.

[0107] The fourth resistor R4 is a bias resistor, and the function of the fourth resistor R4 is to share the voltage in the circuit and protect the second NPN transistor NPN2.

[0108] The resistance range of the fourth resistor R4 is 80 kΩ to 120 kΩ.

[0109] In this embodiment, the fuse unit includes: a second MOS tube, a seventh end v of the second MOS tube is connected to the third base b31, an eighth end w of the second MOS tube is used to input a second trigger signal, the seventh end v is one of the source and the drain of the second MOS tube, the eighth end w is the other of the source and the drain of the second MOS tube, and the second gate of the second MOS tube is used to input a second switching signal; when the second MOS tube is a PMOS, the seventh end v is the drain of the PMOS tube, and the eighth end w is the source of the PMOS tube; when the second MOS tube is an NMOS, the seventh end v is the source of the NMOS tube, and the eighth end w is the drain of the NMOS tube.

[0110] When the voltage value Vg2 of the second switch signal is greater than the threshold voltage value of the second MOS transistor, the second MOS transistor is turned on. The second gate of the second MOS transistor plays the role of controlling the switch.

[0111] Specifically, in this embodiment, the threshold voltage of the second MOS tube is 0.75V.

[0112] When the current value of the second trigger signal I 26 When the product of the current I of the second power supply terminal Vpp2 and the fourth resistor R4 is greater than the turn-on voltage of the second PNP transistor PNP2 and the second NPN transistor NPN2, the second PNP transistor PNP2 and the second NPN transistor NPN2 are turned on. 21 Divide into I 22 and I 23 The two branch currents, the I 21 =I 22 +I 23 Current I22 The current I flows through the third emitter e31 into the second PNP transistor PNP2 and is divided into a current I flowing through the third base b31. 22-1 and the current I flowing through the third collector c31 22-2 , the I 22 =I 22-1 +I 22-2 And the I 22-2 =βI 22-1 , where 60<β<80, current I 22-1 The current I flows through the collector c41 of the second NPN transistor NPN2. 22-1-2 and the current I flowing through the seventh terminal v of the second MOS tube 22-1-1 , the I 22-1 =I 22-1-1 +I 22-1-2 , current I 22-2 The current I flows through the fourth base b41 of the second NPN transistor NPN2. 22-2-1 and the current I flowing through the third resistor R3 22-2-2 , the I 22-2 =I 22-2-1 +I 22-2-2 ; Current I 23 After flowing through the fourth resistor R4, the current I flows through the collector c41 of the second NPN transistor NPN2. 23-2 and the current I flowing through the seventh terminal v of the second MOS tube 23-1 , the I 23 =I 23-1 +I 23-2 , the I 22-1-2 +I 23-2 =βI 22-2-1 , where 60<β<80. The current I 22-1-1 and current I 23-1 The current I 26 , the I 26 =I 22-1-1 +I 23-1 , the current I 22-2-1 、Current I 22-1-2 And the current I 23-2 The current I 24 , the I 24 =I 22-2-1 +I 22-1-2 +I 23-2 , the current I 22-2-2 and current I 24 The current I 25 , the I 25 =I 22-2-2 +I 24 , the current I25 The current flows through the second fuse F2 and then is grounded.

[0113] I 25＝ I 21 —I 26 , the I 26 is the current of the second trigger signal, I 26 The magnitude is very small, usually in microamperes (μA). 21 The current is very large, which can reach several hundred milliamperes (mA), so the current I flowing through the second fuse F2 is 25 The current I is much larger than the second trigger signal 26 .

[0114] The current I of the second trigger signal 26 Can be a transient current, when I 26 When the product of R and R4 is greater than the threshold voltage of the second NPN transistor NPN2, the second fuse F2 is blown.

[0115] When the second MOS tube is a PMOS, the drain of the PMOS tube is connected to the third base b31; the source of the PMOS tube is used to input the second trigger signal.

[0116] When the second MOS tube is an NMOS, the source of the NMOS tube is connected to the third base b31; the drain of the NMOS tube is used to input the second trigger signal.

[0117] In the fuse unit of this embodiment, the third base b31 is connected to the fourth collector c41 and the third collector c31 is connected to the fourth base b41, so the second PNP transistor PNP2 and the second NPN transistor NPN2 are connected in series to form a common emitter amplifier circuit, so that the input current is amplified several times, and the area of ​​the fuse unit is reduced while obtaining a high fuse current. Correspondingly, an embodiment of the present invention also provides a memory, including several as Figure 2 The fuse unit is shown.

[0118] In this embodiment, on the one hand, since the area of ​​the fuse unit of two transistors connected in series is smaller than the area of ​​the fuse unit of multiple MOS tubes connected in parallel, the area of ​​the memory including the plurality of fuse units is smaller, thereby reducing the area of ​​the memory; on the other hand, the cost of the transistor is low, thereby reducing the process cost compared to the memory composed of multiple MOS tubes connected in parallel.

[0119] Accordingly, an embodiment of the present invention also provides a memory operation method. Figure 6 The schematic flow diagram of the memory working method shown includes:

[0120] S101, inputting a first switching signal to a first gate of a first MOS transistor, and when a voltage value Vg of the first switching signal is greater than a threshold voltage value of the MOS transistor, the first MOS transistor is turned on;

[0121] S102, inputting a first trigger signal to a fourth terminal of the first MOS transistor;

[0122] S103, determining whether the current value of the first trigger signal is greater than a threshold current;

[0123] When the current value of the first trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the fusing current, the first fuse is blown and logic 1 is written;

[0124] S104, when the current value of the first trigger signal is less than the threshold current, the current flowing through the first fuse is less than the blowing current, the first fuse is not blown and a logic 0 is written.

[0125] The following will be combined with the attached Figure 2 and Figure 6 Provide detailed explanation.

[0126] In this embodiment, the threshold voltage of the first MOS transistor is 0.75 V. When the voltage value Vg1 of the first switch signal is greater than the threshold voltage 0.75 V of the first MOS transistor, the first MOS transistor is turned on.

[0127] In this embodiment, the threshold current is the threshold current of the first NPN transistor NPN1; the threshold current of the first NPN transistor NPN1 is 10 μA; and the magnitude of the fuse current is 50 mA.

[0128] When the voltage value Vg1 of the first switch signal is greater than the threshold voltage 0.75V of the first MOS transistor, the first MOS transistor is turned on. A first trigger signal is input to the fourth terminal y of the first MOS transistor. When the product of the current value I5 of the first trigger signal and the second resistor R2 is greater than the turn-on voltage of the first PNP transistor PNP1 and the first NPN transistor NPN1, the first PNP transistor PNP1 and the first NPN transistor NPN1 are turned on. The current I1 of the first power supply terminal Vpp1 is divided into two branch currents I2 and I3. The current I2 flows through the first resistor R1, and the current I3 flows into the first PNP transistor PNP1 through the first emitter e11, and the I1=I2+I3. The current I3 is divided into the current I flowing through the first base b11 through the first PNP transistor PNP1. 3-1 and the current I flowing through the first collector c11 3-2 , said I3=I 3-1 +I 3-2 And the I 3-2 =βI3-1 , where 60<β<80. Current I 3-1 The current I4 is combined with the current I2 flowing through the first resistor R1 to form a current I4, and the current I4 flows into the first NPN transistor NPN1 through the second collector c21. 3-1 +I2. Current I 3-2 The current I flows through the second base b21. 3-2-2 The current I flowing through the second resistor R2 3-2-1 , the I 3-2 =I 3-2-1 +I 3-2-2 The current I5 of the first trigger signal is input, and the current I5 is divided into the current I flowing through the first NPN transistor NPN1. 5-1 and the current I flowing through the second resistor 5-2 , said I5=I 5-1 +I 5-2 , said I4=β(I 3-2-2 +I 5-1 ), where 60<β<80. Current I4, current I 3-2-2 And the current I 5-1 The current I6 is collected into I4+I 3-2-2 +I 5-1 , current I 3-2-1 、Current I 5-2 And the current I6 is integrated into the current I7, where I7=I 3-2-1 +I 5-2 +I6, current I7 flows through the first fuse F1 and then goes to ground.

[0129] The I7=I1+I5, where I5 ​​is the current of the first trigger signal. The magnitude of I5 is very small, generally in microamperes (μA). The current I1 is very large, which can reach several hundred milliamperes (mA). Therefore, the current I7 flowing through the first fuse F1 is much larger than the current I5 of the first trigger signal.

[0130] The current I5 of the first trigger signal may be a transient current. When the product of I5 and R2 is greater than the threshold voltage of the first NPN transistor NPN1, the first fuse F1 is blown.

[0131] In this embodiment, the voltage of the first power supply terminal Vpp1 ranges from 1.0V to 1.8V.

[0132] In this embodiment, the turn-on voltage of the first PNP transistor PNP1 ranges from 0.3V to 0.6V.

[0133] In this embodiment, the on-state voltage of the first NPN transistor NPN1 is in the range of 0.3V to 0.6V.

[0134] In this embodiment, the resistance range of the second resistor R2 is 80 kΩ to 120 kΩ.

[0135] In this embodiment, the resistance range of the first resistor R1 is 100Ω to 500Ω.

[0136] Specifically, in this embodiment, when the current value I5 of the first trigger signal is greater than the threshold current 10μA of the first NPN transistor NPN1, the current I5 of the first trigger signal is amplified twice by the two transistors, and the current flowing through the first fuse F1 is greater than the melting current of the first fuse, the first fuse is melted, and logic 1 is written at this time; when the current value I5 of the first trigger signal is less than the threshold current 10μA of the first NPN transistor NPN1, the current I5 of the first trigger signal is amplified twice by the two transistors, and the current flowing through the first fuse F1 is less than the melting current of the first fuse F1, the first fuse F1 is not melted, and logic 0 is written at this time.

[0137] Specifically, in this embodiment, the memory stores information by recording whether the current amplified by the two transistors blows the first fuse F1 and performs programming and writing.

[0138] The embodiment of the present invention also provides another memory, including several Figure 5 The fuse unit is shown.

[0139] In this embodiment, on the one hand, since the area of ​​the fuse unit of two transistors connected in series is smaller than the area of ​​the fuse unit of multiple MOS tubes connected in parallel, the area of ​​the memory including the plurality of fuse units is smaller, thereby reducing the area of ​​the memory; on the other hand, the cost of the transistor is low, thereby reducing the process cost compared to the memory composed of multiple MOS tubes connected in parallel.

[0140] Accordingly, the embodiment of the present invention also provides another memory operation method. Figure 7 The schematic flow diagram of the memory working method shown includes:

[0141] S201, inputting a second switching signal to a second gate of a second MOS transistor, and when a voltage value Vg of the second switching signal is greater than a threshold voltage value of the MOS transistor, the second MOS transistor is turned on;

[0142] S202, inputting a second trigger signal to the eighth terminal of the second MOS transistor;

[0143] S203, determining whether the current value of the second trigger signal is greater than a threshold current;

[0144] When the current value of the second trigger signal is greater than the threshold current, the current flowing through the second fuse is greater than the fusing current, the second fuse is blown and logic 1 is written;

[0145] S204, when the current value of the second trigger signal is less than the threshold current, the current flowing through the second fuse is less than the blowing current, the second fuse is not blown and a logic 0 is written.

[0146] The following will be combined with the attached Figure 5 and Figure 7 Provide detailed explanation.

[0147] In this embodiment, the threshold voltage of the second MOS transistor is 0.75 V. When the voltage value Vg2 of the second switch signal is greater than the threshold voltage 0.75 V of the second MOS transistor, the second MOS transistor is turned on.

[0148] In this embodiment, the threshold current is the threshold current of the second NPN transistor NPN2; the threshold current of the second NPN transistor NPN2 is 10 μA; and the magnitude of the fusing current is 50 mA.

[0149] When the voltage value Vg2 of the second switch signal is greater than the threshold voltage 0.75V of the second MOS tube, the second MOS tube is turned on. A second trigger signal is input to the eighth terminal w of the second MOS tube. When the current value I 26 When the product of the current I of the second power supply terminal Vpp2 and the fourth resistor R4 is greater than the turn-on voltage of the second PNP transistor PNP2 and the second NPN transistor NPN2, the second PNP transistor PNP2 and the second NPN transistor NPN2 are turned on. 21 Divide into I 22 and I 23 The two branch currents, the I 21 =I 22 +I 23 Current I 22 The current I flows through the third emitter e31 into the second PNP transistor PNP2 and is divided into a current I flowing through the third base b31. 22-1 and the current I flowing through the third collector c31 22-2 , the I 22 =I 22-1 +I 22-2 And the I 22-2 =βI 22-1 , where 60<β<80, current I 22-1 The current I flows through the collector c41 of the second NPN transistor NPN2. 22-1-2 and the current I flowing through the seventh terminal v of the second MOS tube 22-1-1 , the I 22-1 =I22-1-1 +I 22-1-2 , current I 22-2 The current I flows through the fourth base b41 of the second NPN transistor NPN2. 22-2-1 and the current I flowing through the third resistor R3 22-2-2 , the I 22-2 =I 22-2-1 +I 22-2-2 ; Current I 23 After flowing through the fourth resistor R4, the current I flows through the collector c41 of the second NPN transistor NPN2. 23-2 and the current I flowing through the seventh terminal v of the second MOS tube 23-1 , the I 23 =I 23-1 +I 23-2 , the I 22-1-2 +I 23-2 =βI 22-2-1 , where 60<β<80. The current I 22-1-1 and current I 23-1 The current I 26 , the I 26 =I 22-1-1 +I 23-1 , the current I 22-2-1 、Current I 22-1-2 And the current I 23-2 The current I 24 , the I 24 =I 22-2-1 +I 22-1-2 +I 23-2 , the current I 22-2-2 and current I 24 The current I 25 , the I 25 =I 22-2-2 +I 24 , the current I 25 The current flows through the second fuse F2 and then is grounded.

[0150] In this embodiment, the voltage of the second power supply terminal Vpp2 ranges from 1.0V to 1.8V.

[0151] In this embodiment, the turn-on voltage range of the second PNP transistor PNP2 is: 0.3V to 0.6V.

[0152] In this embodiment, the turn-on voltage of the second NPN transistor NPN2 is in the range of 0.3V to 0.6V.

[0153] In this embodiment, the resistance range of the third resistor R3 is 80 kΩ to 120 kΩ.

[0154] In this embodiment, the resistance range of the fourth resistor R4 is 100Ω to 500Ω.

[0155] Specifically, in this embodiment, when the current value I of the second trigger signal 26 When the current of the second trigger signal I is greater than the threshold current of the second NPN transistor NPN2 by 10μA, the current of the second trigger signal I 26 After secondary amplification by the two transistors, the current flowing through the second fuse F2 is greater than the fusing current of the second fuse, and the second fuse F2 is blown, and logic 1 is written at this time; when the current value I 26 When the current of the second trigger signal I is less than the threshold current of the second NPN transistor NPN2 of 10μA, the current of the second trigger signal I 26 After secondary amplification by the two transistors, the current flowing through the second fuse F2 is less than the fusing current of the second fuse F2, and the second fuse F2 is not blown, and logic 0 is written at this time.

[0156] Specifically, in this embodiment, the memory stores information by recording whether the current amplified by the two transistors blows the second fuse F2 and performs programming and writing.

[0157] Accordingly, an embodiment of the present invention also provides a working method of a monitoring circuit. Figure 8 The schematic flow diagram of the monitoring circuit working method shown includes:

[0158] S301, connecting the first device to be monitored to a second base;

[0159] S302, the first monitored device inputs a third trigger signal to the second base;

[0160] S303, determining whether the current value of the third trigger signal is greater than a threshold current;

[0161] When the current value of the third trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the fusing current, and the first fuse is blown;

[0162] S304: When the current value of the third trigger signal is less than the threshold current, the current flowing through the first fuse is less than the blowing current, and the first fuse is not blown.

[0163] The following will be combined with the attached Figure 3 and Figure 8 Provide detailed explanation.

[0164] In this embodiment, the threshold current is the threshold current of the first NPN transistor NPN1; the threshold current of the first NPN transistor NPN1 is 10 μA; and the magnitude of the fuse current is 50 mA.

[0165] In this embodiment, when the current value I 12 When the product of the current I8 and the second resistor R2 is greater than the on-state voltage of the first PNP transistor PNP1 and the first NPN transistor NPN1, the first PNP transistor PNP1 and the first NPN transistor NPN1 are turned on. The current I8 at the first power supply terminal Vpp1 is divided into I9 and I 10 There are two branch currents, current I9 flows through the first resistor R1, and current I 10 Flows into the first PNP transistor PNP1 through the first emitter e12, and I8=I9+I 10 Current I 10 The current I is divided into the current I flowing through the first base b12 by the first PNP transistor PNP1. 10-1 and the current I flowing through the first collector c12 10-2 , the I 10 =I 10-1 +I 10-2 And the I 10-2 =βI 10-1 , where 60<β<80. Current I 10-1 The current I9 flowing through the first resistor is combined into a current I 11 , current I 11 The current flows into the first NPN transistor NPN1 through the second collector c22. 11 =I9+I 10-1 Current I 10-2 The current I flows through the second base b22. 10-2-2 The current I flowing through the second resistor R2 10-2-1 , the I 10-2 =I 10-2-2 +I 10-2-1 The weak current I of the third trigger signal 12 Input, current I 12 The current I flows through the first NPN transistor NPN1. 12-1 and the current I flowing through the second resistor R2 12-2 , the I 12 =I 12-1 +I 12-2 , the I 11 =β(I 10-2-2 +I 12-1 ), where 60<β<80. Current I 11 、Current I 10-2-2 And the current I 12-1 The current I 13 , the I 13 =I 11 +I 10-2-2 +I12-1 , current I 10-2-1 、Current I 12-2 And the current I 13 The current I 14 , the I 14 =I 10-2-1 +I 12-2 +I 13 , current I 14 The current flows through the first fuse F1 and then is grounded.

[0166] I 14 =I8+I 12 , the I 12 is the current of the third trigger signal, I 12 The order of magnitude is very small, generally in microamperes (μA), and the current I8 is very large, which can reach several hundred milliamperes (mA). Therefore, the current I flowing through the first fuse F1 is 14 The current I is much larger than the third trigger signal 12 .

[0167] The current I of the third trigger signal 12 Is a transient weak current. When I 12 When the product of R2 is greater than the threshold voltage of the first NPN transistor NPN1, the first fuse F1 is blown.

[0168] In the monitoring circuit of this embodiment, the first PNP transistor PNP1 and the first NPN transistor NPN1 convert the weak current I 12 The weak current is greatly amplified, and the existence of the weak current is monitored by judging whether the weak current after being greatly amplified has blown the first fuse F1, so as to protect important components in the circuit.

[0169] Accordingly, an embodiment of the present invention also provides a working method of a monitoring circuit. Fig. 9 The schematic flow diagram of the monitoring circuit working method shown includes:

[0170] S401, connecting the second monitored device to the first base;

[0171] S402, the second monitored device inputs a fourth trigger signal to the first base;

[0172] S403, determining whether the current value of the fourth trigger signal is greater than a threshold current;

[0173] When the current value of the fourth trigger signal is greater than the threshold current, the current flowing through the second fuse is greater than the fusing current, and the second fuse is blown;

[0174] S404, when the current value of the fourth trigger signal is less than the threshold current, the current flowing through the second fuse is less than the blowing current, and the second fuse is not blown.

[0175] The following will be combined with the attached Figure 4 and Fig. 9 Provide detailed explanation.

[0176] In this embodiment, the threshold current is the threshold current of the first NPN transistor NPN1; the threshold current of the first NPN transistor NPN1 is 10 μA; and the magnitude of the fuse current is 50 mA.

[0177] In this embodiment, when the current value I 16-1 When the product of the current I of the first power supply terminal Vpp1 is greater than the turn-on voltage of the first PNP transistor PNP1 and the first NPN transistor NPN1, the first PNP transistor PNP1 and the first NPN transistor NPN1 are turned on. 15 Divide into I 16 and I 17 Two branch currents, current I 16 Flowing through the first resistor R1, the current I 17 Flows into the first PNP transistor PNP1 through the first emitter e12. 15 =I 16 +I 17 Current I 16 The current I is divided by the first resistor R1 into a current I flowing through the second monitored device D2 16-1 , the current I flowing through the first base b12 16-2 and the current I flowing through the second collector c22 16-3 Current I 17 and the current I flowing through the first base b12 16-2 The current I 18 , current I 18 The current I flows through the second resistor. 18-2 and the current I flowing through the second base b22 18-1 Current I 16-3 With current I 18-1 The current I flowing through the second emitter 19 , the I 19 =I 18-1 +I 16-3 Current I 19 The current I flowing through the second resistor R2 18-2 The current is combined into current I 20 , the I 20 =I 18-2 +I 19 Current I20 The current flows through the first fuse F1 and then is grounded.

[0178] In the monitoring circuit of this embodiment, the first PNP transistor PNP1 and the first NPN transistor NPN1 convert the weak current I 16-1 The weak current is greatly amplified, and the existence of the weak current is monitored by judging whether the weak current after being greatly amplified has blown the first fuse F1, so as to protect important components in the circuit.

[0179] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A fuse unit, characterized in that: include: A first fuse having a first end and a second end, wherein the second end is grounded; A first amplifying unit, the first amplifying unit comprising: a first PNP transistor and a first NPN transistor, the first PNP transistor having a first emitter, a first collector and a first base, the first emitter being connected to the first power supply terminal, and the first collector being used to output a current signal to the first terminal; The first NPN transistor has a second emitter, a second collector and a second base, the second collector is connected to the first base, the second emitter is connected to the first end, and the second base is used to input a first trigger signal.

2. The fuse unit according to claim 1, characterized in that: Also includes: A second resistor, wherein the second resistor is connected between the first collector and the first end; and a first resistor, wherein both ends of the first resistor are respectively connected to the first emitter and the first base.

3. The fuse unit according to claim 1, wherein: Also includes: A first MOS tube, wherein the third end of the first MOS tube is connected to the second base, the fourth end of the first MOS tube is used to input a first trigger signal, the third end is one of the source and the drain of the first MOS tube, the fourth end is the other of the source and the drain of the first MOS tube, and the first gate of the first MOS tube is used to input a first switch signal; when the first MOS tube is a PMOS, the third end is the drain of the PMOS tube, and the fourth end is the source of the PMOS tube; when the first MOS tube is an NMOS, the third end is the source of the NMOS tube, and the fourth end is the drain of the NMOS tube.

4. The fuse unit according to claim 1, wherein: Also includes: The second base is connected to the first device to be monitored.

5. The fuse unit according to claim 1, wherein: Also includes: The first base is connected to a second device to be monitored.

6. A fuse unit, characterized in that: include: A second fuse having a fifth end and a sixth end, wherein the sixth end is grounded; The second amplifying unit comprises: a second PNP transistor and a second NPN transistor, the second PNP transistor having a third emitter, a third collector and a third base, the third emitter is connected to the second power supply terminal, and the third base is used to input a second trigger signal; the second NPN transistor has a fourth emitter, a fourth collector and a fourth base, the fourth base is connected to the third collector, the fourth emitter is connected to the fifth terminal, and the fourth collector is used to input a current signal from the second power supply terminal.

7. The fuse unit according to claim 6, characterized in that: Also includes: a third resistor connected between the third collector and the fifth terminal; and a fourth resistor connected between the third emitter and the fourth collector.

8. The fuse unit according to claim 6, characterized in that: Also includes: A second MOS tube, wherein the seventh end of the second MOS tube is connected to the third base, the eighth end of the second MOS tube is used to input a second trigger signal, the seventh end is one of the source and the drain of the second MOS tube, the eighth end is the other of the source and the drain of the second MOS tube, and the second gate of the second MOS tube is used to input a second switch signal; when the second MOS tube is a PMOS, the seventh end is the drain of the PMOS tube, and the eighth end is the source of the PMOS tube; when the second MOS tube is an NMOS, the seventh end is the source of the NMOS tube, and the eighth end is the drain of the NMOS tube.

9. A memory, characterized in that: include: A plurality of fuse units, each of the fuse units being as described in any one of claims 1 to 3.

10. A method for operating a memory as claimed in claim 9, characterized in that: include: A first switching signal is inputted into a first gate of the first MOS tube, and when a voltage value of the first switching signal is greater than a threshold voltage value of the first MOS tube, the first MOS tube is turned on; A first trigger signal is input at the fourth end of the first MOS tube. When the current value of the first trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the blowing current, the first fuse blows and logic 1 is written; when the current value of the first trigger signal is less than the threshold current, the current flowing through the first fuse is less than the blowing current, the first fuse does not blow and logic 0 is written.

11. The memory operating method according to claim 10, characterized in that: The threshold current is the threshold current of the first NPN transistor; the threshold current of the first NPN transistor is 10 μA; and the magnitude of the fuse current is 50 mA.

12. The memory operating method according to claim 10, characterized in that: The voltage of the first power supply terminal ranges from 1.0V to 1.8V; the threshold voltage of the first MOS tube is 0.75V; and the voltage value of the first trigger signal is greater than 0.1V.

13. A memory, characterized in that: include: A plurality of fuse units, each of the fuse units being as described in any one of claims 6 to 8.

14. A method for operating a memory as claimed in claim 13, characterized in that: include: A second switching signal is inputted into a second gate of the second MOS tube, and when a voltage value of the second switching signal is greater than a threshold voltage value of the second MOS tube, the second MOS tube is turned on; A second trigger signal is input at the eighth end of the second MOS tube. When the current value of the second trigger signal is greater than the threshold current, the current flowing through the second fuse is greater than the blowing current, the second fuse blows and logic 1 is written; when the current value of the second trigger signal is less than the threshold current, the current flowing through the second fuse is less than the blowing current, the second fuse does not blow and logic 0 is written.

15. The memory operating method according to claim 14, characterized in that: The threshold current is the threshold current of the second PNP transistor; the threshold current of the second PNP transistor is 10 μA; and the magnitude of the fuse current is 50 mA.

16. The memory operating method according to claim 14, characterized in that: The voltage of the second power supply terminal ranges from 1.0V to 1.8V; the threshold voltage of the second MOS tube is 0.75V; and the voltage value of the second trigger signal is greater than 0.1V.

17. A working method of a monitoring circuit, the monitoring circuit comprising the fuse unit according to any one of claims 1 to 2 and a first device to be monitored, the first device to be monitored being connected to a second base, characterized in that: include: The first monitored device inputs a third trigger signal to the second base; When the current value of the third trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the blowing current, and the first fuse blows.

18. The operating method of the monitoring circuit according to claim 17, characterized in that: The threshold current is the threshold current of the first NPN transistor; the threshold current of the first NPN transistor is 10 μA; The magnitude of the fusing current is 50 mA.

19. A working method of a monitoring circuit, the monitoring circuit comprising the fuse unit according to any one of claims 1 to 2 and a second device to be monitored, the second device to be monitored being connected to a first base, characterized in that: include: The second monitored device inputs a fourth trigger signal to the first base; When the current value of the fourth trigger signal is greater than the threshold current, the current flowing through the first fuse is greater than the blowing current, and the first fuse blows.

20. The operating method of the monitoring circuit according to claim 19, characterized in that: The threshold current is the threshold current of the first PNP transistor; the threshold current of the first PNP transistor is 10 μA; The magnitude of the fusing current is 50 mA.

Images