Level shift circuit for improving reliability of gallium nitride half-bridge power chip

Abstract

The invention discloses a level shift circuit for improving the reliability of a gallium nitride half-bridge power chip. The level shift circuit comprises a pulse generation circuit, a level conversion branch, a noise elimination circuit, a negative VS tolerance lifting circuit and a latch module, the noise elimination circuit can effectively suppress the influence of dVS / dt noise, the negative VS tolerance boosting circuit can boost the tolerance of the circuit to VS negative voltage, it is guaranteed that an input signal can be accurately transmitted into the latch module to be output, and the reliability of the gallium nitride half-bridge power chip is improved.

Description

Technical Field

[0001] The present invention belongs to the field of power integrated circuits based on gallium nitride technology, and in particular relates to a level shifting circuit for improving the reliability of a gallium nitride half-bridge power chip. Background Art

[0002] Nowadays, with the continuous development of power integrated circuits, the industry's requirements for circuit speed, power consumption and stability are constantly increasing. Compared with silicon (Si)-based transistors, gallium nitride transistors have the characteristics of high electron mobility, high critical electric field strength and low thermal conductivity. The use of gallium nitride power devices in power conversion systems can show the advantages of fast response, high stability and low energy consumption, and significantly improve the performance of the system. However, due to the large parasitic capacitance of silicon-based materials, the discrete drive solution of using silicon-based half-bridge driver chips to drive gallium nitride devices will limit the potential of gallium nitride devices in high-frequency applications. As the switching speed increases, the parasitic inductance problem of the discrete drive solution will also seriously affect the reliability of the system. In order to cope with this problem, leadless packaging technology is usually required, but at the same time it will increase the cost of chip packaging. In order to fundamentally solve these problems, the gallium nitride process can be used to integrate the half-bridge drive circuit and the power device on the same chip. This method can not only give full play to the high-frequency characteristics of gallium nitride devices, but also improve the reliability of the system, achieving the dual advantages of high-frequency application and stability.

[0003] like Figure 1 As shown, the core of the half-bridge drive circuit is the high-voltage level shift circuit, which can convert the low-voltage domain power rail to the high-voltage domain power rail to achieve the control of the high-voltage circuit system by the low-voltage signal. However, P-type transistors cannot be made in the existing commercial GaN process, so the circuit of the fully integrated GaN half-bridge power chip can only be realized by using N-type GaN high electron mobility transistors (NHEMT). Therefore, the traditional CMOS level shift circuit structure cannot be directly applied to the GaN half-bridge power chip.

[0004] In addition, there are two main challenges faced in GaN integrated level shift circuits:

[0005] 1. In a bridge circuit, the alternating turn-on of the high-side and low-side power tubes will cause the potential of the half-bridge switch node VS to switch back and forth between the bus voltage VBUS and GND. Since the GaN device switches quickly, the VS changes quickly, and the parasitic capacitance of the high-voltage tube will introduce greater dVS / dt noise in the high-side circuit of the half-bridge chip, affecting the circuit operation.

[0006] 2. During the dead time of the normal operation of the power supply system, the high-side and low-side power tubes are turned off at the same time. Due to the freewheeling effect of the inductor of the peripheral circuit, the inductor current will continue to discharge the VS node, causing VS to drop until the low-side power tube is reversed. During the reverse conduction of the low-side power tube, the VS point is a negative voltage. In traditional Si-based systems, due to the presence of the parasitic body diode of the silicon power tube, its reverse conduction voltage drop is very small and has little effect on the circuit. However, gallium nitride transistors have no parasitic body diodes, and their reverse conduction voltage drop is large (about 3-5V), which will cause the negative voltage value of VS to be lower, making it more difficult to trigger the high-side circuit, and even unable to respond to the input signal.

[0007] In the GaN half-bridge circuit, the above two phenomena will lead to signal loss, chip logic errors, and circuit abnormality. Summary of the invention

[0008] The present invention aims to provide a level shift circuit for improving the reliability of a gallium nitride half-bridge power chip, which can effectively suppress the influence of dVS / dt noise and solve the problem of VS negative voltage, thereby ensuring the reliability of a power integrated circuit system.

[0009] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0010] A level shifting circuit for improving the reliability of a gallium nitride half-bridge power chip, comprising: a pulse generating circuit, a first level conversion branch, a second level conversion branch, a noise elimination circuit, a first negative VS tolerance improving circuit, a second negative VS tolerance improving circuit, and a latch module;

[0011] The input signal VIN is connected to the input end of the pulse generating circuit; the input signal of the pulse generating circuit is VIN, which is used to convert the input signal VIN into two narrow pulse signals RESET and SET, the output point of the narrow pulse signal RESET is connected to the input end of the first level conversion branch, and the output point of the narrow pulse signal SET is connected to the input end of the second level conversion branch; the input signals of the first level conversion branch and the second level conversion branch are the output signals RESET and SET of the pulse generating circuit, the first level conversion branch and the second level conversion branch are used to convert the input two pulse signals from the low voltage domain to the high voltage domain, the output end of the first level conversion branch is point X, and the output end of the second level conversion branch is point Y, and points X and Y are respectively connected to the two input ends of the noise elimination circuit; the input signal of the noise elimination circuit is the output of the first level conversion branch and the output of the second level conversion branch. The latch module comprises a first level conversion branch and a second level conversion branch, wherein the output ends of the noise elimination circuit are respectively the input ends of the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit; the input signals of the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit are two output signals of the noise elimination circuit, which are used to improve the negative VS tolerance capability of the level shifting circuit; the output current signals are respectively IRESET and ISET, and the output points of the current signals IRESET and ISET are respectively connected to the two input ends of the latch module; the input signals of the latch module are the current signals IRESET and ISET output by the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit, which are used to convert the current signals IRESET and ISET into the output voltage signal VOUT.

[0012] Furthermore, the pulse generating circuit includes enhanced NHEMT tubes MN21 and MN22, current sources I5 and I6, capacitors C3 and C4, inverters INV1 to INV3, and NAND gates NAND1 and NAND2;

[0013] The gate of the enhanced NHEMT tube MN21 is connected to the input signal VIN and an input end of the NAND gate NAND1. The drain of the enhanced NHEMT tube MN21 is connected to the output end of the current source I5, the input end of the inverter INV2, and one end of the capacitor C3. The source of the enhanced NHEMT tube MN21 is connected to the ground signal GND of the low-voltage domain power rail. The gate of the enhanced NHEMT tube MN22 is connected to the output end of the inverter INV1 and an input end of the NAND gate NAND2. The drain of the enhanced NHEMT tube MN22 is connected to the output end of the current source I6, the input end of the inverter INV3, and one end of the capacitor C4. The source of the enhanced NHEMT tube MN22 is connected to the ground signal GND of the low-voltage domain power rail. The ground signal GND, the input end of the current source I5 is connected to the power signal VDD of the low-voltage domain power rail, the input end of the current source I6 is connected to the power signal VDD of the low-voltage domain power rail, the other end of the capacitor C3 is connected to the ground signal GND of the low-voltage domain power rail, the other end of the capacitor C4 is connected to the ground signal GND of the low-voltage domain power rail, the input end of the inverter INV1 is connected to the input signal VIN, the output end of the inverter INV2 is connected to the other input end of the NAND gate NAND1, the output end of the inverter INV3 is connected to the other input end of the NAND gate NAND2, the output end of the NAND gate NAND1 is connected to the input end of the first level conversion branch, and the output end of the NAND gate NAND2 is connected to the input end of the second level conversion branch.

[0014] Further, the first level conversion branch and the second level conversion branch both include enhanced NHEMT tubes MN17-MN20, high-voltage enhanced NHEMT tubes HMN1, HMN2, and resistors R1, R2;

[0015] The gate of the high-voltage enhanced NHEMT tube HMN1 is connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NHEMT tube HMN1 is connected to one end of the resistor R1, the drain of the enhanced NHEMT tube MN17, the source of the enhanced NHEMT tube MN19, the gate of the enhanced NHEMT tube MN19, the source of the enhanced NHEMT tube MN1, and the source of the enhanced NHEMT tube MN2. The source of the high-voltage enhanced NHEMT tube HMN1 is connected to the output end of the NAND gate NAND1, the gate of the enhanced NHEMT tube MN17 is connected to the source of the enhanced NHEMT tube MN17 and the ground signal VS of the high-voltage domain power rail, the drain of the enhanced NHEMT tube MN19 is connected to the power signal VBSTH of the high-voltage domain power rail, and the other end of the resistor R1 is connected to the power signal VBST of the high-voltage domain power rail. H, the gate of the high-voltage enhanced NHEMT tube HMN2 is connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NHEMT tube HMN2 is connected to one end of the resistor R2, the drain of the enhanced NHEMT tube MN18, the source of the enhanced NHEMT tube MN20, the gate of the enhanced NHEMT tube MN20, the source of the enhanced NHEMT tube MN3, and the source of the enhanced NHEMT tube MN4, the source of the high-voltage enhanced NHEMT tube HMN2 is connected to the output end of the NAND gate NAND2, the gate of the enhanced NHEMT tube MN18 is connected to the source of the enhanced NHEMT tube and the ground signal VS of the high-voltage domain power rail, the drain of the enhanced NHEMT tube MN20 is connected to the power signal VBSTH of the high-voltage domain power rail, and the other end of the resistor R2 is connected to the power signal VBSTH of the high-voltage domain power rail.

[0016] Further, the noise elimination circuit includes: enhancement-type NHEMT tubes MN1-MN4, depletion-type NHEMT tubes MN9-MN12, and resistors R5-R8;

[0017] The gate of the enhanced NHEMT tube MN1 is connected to the gate of the enhanced NHEMT tube MN4 and the drain of the enhanced NHEMT tube MN1. The drain of the enhanced NHEMT tube MN1 is connected to the gate of the depletion-type NHEMT tube MN9 and one end of the resistor R5. The source of the enhanced NHEMT tube MN1 is connected to the source of the enhanced NHEMT tube MN2 and the drain of the high-voltage enhanced NHEMT tube HMN1. The gate of the enhanced NHEMT tube MN2 is connected to the gate of the enhanced NHEMT tube MN3 and the drain of the enhanced NHEMT tube MN3. The drain of the enhanced NHEMT tube MN2 is connected to the gate of the depletion-type NHEMT tube MN10, one end of the resistor R6, one end of the resistor R3, and one end of the capacitor C1. The drain of the enhanced NHEMT tube MN3 is connected to the gate of the depletion-type NHEMT tube MN11 and one end of the resistor R7. The source of the enhanced NHEMT tube MN3 is connected to the source of the enhanced NHEMT tube MN4. , the drain of the high-voltage enhancement type NHEMT tube HMN2, the drain of the enhancement type NHEMT tube MN4 is connected to the gate of the depletion type NHEMT tube MN12, one end of the resistor R8, one end of the resistor R4, and one end of the capacitor C2, the drain of the depletion type NHEMT tube MN9 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN9 is connected to the other end of the resistor R5, the drain of the depletion type NHEMT tube MN10 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN10 is connected to the other end of the resistor R6, the drain of the depletion type NHEMT tube MN11 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN11 is connected to the other end of the resistor R7, the drain of the depletion type NHEMT tube MN12 is connected to the power signal VBSTH of the high-voltage domain power rail, and the source of the depletion type NHEMT tube MN12 is connected to the other end of the resistor R8.

[0018] Furthermore, the depletion-type NHEMT transistors MN9 ˜ MN12 respectively form current sources I1 ˜ I4 with the resistors R5 ˜ R8 .

[0019] Furthermore, the current values ​​of the current source I1 and the current source I3 are equal, and the current values ​​of the current source I2 and the current source I4 are equal; the sizes of the enhanced NHEMT tube MN1 and the enhanced NHEMT tube MN3 are equal, and the sizes of the enhanced NHEMT tube MN2 and the enhanced NHEMT tube MN4 are equal.

[0020] Further, the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit both include: enhanced NHEMT tubes MN5-MN8, MN13-MN16, resistors R3, R4, capacitors C1, C2;

[0021] The connection mode of the first negative VS tolerance improvement circuit is as follows: the gate of the enhanced NHEMT tube MN5 is connected to the drain of the enhanced NHEMT tube MN5, the source of the enhanced NHEMT tube MN14, the gate of the enhanced NHEMT tube MN6, and the other end of the capacitor C1; the source of the enhanced NHEMT tube MN5 is connected to the ground signal VS of the high-voltage domain power rail; the source of the enhanced NHEMT tube M6 is connected to the IRESET end of the latch module; the source of the enhanced NHEMT tube MN6 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN13 is connected to the drain of the enhanced NHEMT tube MN13 and the other end of the resistor R3; the source of the enhanced NHEMT tube MN13 is connected to the drain of the enhanced NHEMT tube MN14 and the gate of the enhanced NHEMT tube MN14;

[0022] The connection method of the second negative VS tolerance improvement circuit is as follows: the gate of the enhanced NHEMT tube MN7 is connected to the drain of the enhanced NHEMT tube MN7, the source of the enhanced NHEMT tube MN16, the gate of the enhanced NHEMT tube MN8, and the other end of the capacitor C2; the source of the enhanced NHEMT tube MN7 is connected to the ground signal VS of the high-voltage domain power rail; the source of the enhanced NHEMT tube M8 is connected to the ISET end of the latch module; the source of the enhanced NHEMT tube MN8 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN15 is connected to the drain of the enhanced NHEMT tube MN15 and the other end of the resistor R4; the drain of the enhanced NHEMT tube MN15 is connected to the gate of the enhanced NHEMT tube MN16, and the drain of the enhanced NHEMT tube MN15 is connected to the drain of the enhanced NHEMT tube MN16.

[0023] Furthermore, the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit are symmetrical in structure, and the resistors R3 and R4 have the same device size, the capacitors C1 and C2 have the same size, the enhanced NHEMT tubes MN5 and MN7 have the same size, and the enhanced NHEMT tubes MN6 and MN8 have the same size.

[0024] Further, the latch module includes: enhanced NHEMT tubes MN23-MN26, resistors R9-R12, and an inverter INV4;

[0025] The connection mode of the latch module is as follows: the gate of the enhanced NHEMT tube MN23 is connected to the drain of the enhanced NHEMT tube MN6 and one end of R9; the drain of the enhanced NHEMT tube MN23 is connected to the drain of the enhanced NHEMT tube MN24, the gate of the enhanced NHEMT tube MN26, and one end of the resistor R10; the source of the enhanced NHEMT tube MN23 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN24 is connected to the drain of the enhanced NHEMT tube MN26, the drain of the enhanced NHEMT tube MN25, the input end of the inverter INV4, and one end of the resistor R12; the source of the enhanced NHEMT tube MN24 is connected to the ground signal VS of the high-voltage domain power rail; The gate of the enhanced NHEMT tube MN25 is connected to the ground signal VS of the high-voltage domain power rail, the gate of the enhanced NHEMT tube MN25 is connected to the drain of the enhanced NHEMT tube MN8 and one end of the resistor R11, the source of the enhanced NHEMT tube MN25 is connected to the ground signal VS of the high-voltage domain power rail, the source of the enhanced NHEMT tube MN26 is connected to the ground signal VS of the high-voltage domain power rail, the other end of the resistor R9 is connected to the power signal VBSTL of the high-voltage domain power rail, the other end of the resistor R10 is connected to the power signal VBSTL of the high-voltage domain power rail, the other end of the resistor R11 is connected to the power signal VBSTL of the high-voltage domain power rail, and the other end of the resistor R12 is connected to the power signal VBSTL of the high-voltage domain power rail.

[0026] A level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to the present invention has the following advantages:

[0027] (1) It can effectively improve the anti-dVS / dt noise capability of GaN half-bridge power chips. dVS / dt noise mainly exists in the form of common mode. When the noise comes, the potential of points X and Y changes synchronously, transistors MH2 and MH4 remain closed, and current flows to nodes N3 and N4. The noise signal will not propagate to the next level, so OUT will not be affected by the noise, thus eliminating the influence of dVS / dt noise.

[0028] (2) It can effectively improve the negative VS tolerance capability of the GaN half-bridge power chip. The signal is converted into current by the noise elimination circuit and propagated. When VS becomes negative voltage, the voltage difference on both sides of the negative VS tolerance enhancement circuit is not enough to turn on the module. The three transistors are connected in series to expand the negative VS tolerance, and the capacitors C1 and C2 are used to quickly reduce the gate voltage of MN6 and MN8 to improve the signal transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a typical application diagram of the present invention in a half-bridge driver chip and a power supply system based on gallium nitride technology;

[0030] Figure 2 is a structural diagram of a traditional level shift circuit;

[0031] FIG3( a ) is a working waveform diagram of a conventional level shift circuit under dVS / dt noise;

[0032] FIG3( b ) is a working waveform diagram of a conventional level shift circuit under the influence of negative VS;

[0033] Figure 4 This is a structural diagram of a level shift circuit for improving the reliability of a gallium nitride half-bridge power chip proposed by the present invention;

[0034] FIG5( a ) is a structural diagram of a level shift circuit for improving the reliability of a GaN half-bridge power chip according to an embodiment of the present invention;

[0035] FIG5( b ) is a block diagram of a pulse generating circuit according to an embodiment of the present invention;

[0036] FIG5( c ) is a structural diagram of a latch module according to an embodiment of the present invention;

[0037] Figure 6 is a working waveform diagram of an embodiment of the present invention; DETAILED DESCRIPTION

[0038] In order to better understand the purpose, structure and function of the present invention, a level shifting circuit for improving the reliability of a gallium nitride half-bridge power chip according to the present invention is further described in detail below in conjunction with the accompanying drawings.

[0039] The present invention provides a high-reliability GaN process integrated circuit level shift circuit, comprising:

[0040] Pulse generation circuit, level conversion branch, noise elimination circuit, negative VS tolerance improvement circuit, latch module.

[0041] The pulse generating circuit includes enhanced NHEMT tubes MN21 and MN22, current sources I5 and I6, capacitors C3 and C4, inverters INV1 to INV3, and NAND gates NAND1 and NAND2. The connection mode of the pulse generating circuit is as follows: the gate of the enhanced NHEMT tube MN21 is connected to the input signal VIN and one input end of the NAND gate NAND1, the drain of the enhanced NHEMT tube MN21 is connected to the output end of the current source I5, the input end of the inverter INV2, and one end of the capacitor C3, the source of the enhanced NHEMT tube MN21 is connected to the ground signal GND of the low-voltage domain power rail, the gate of the enhanced NHEMT tube MN22 is connected to the output end of the inverter INV1 and one input end of the NAND gate NAND2, the drain of the enhanced NHEMT tube MN22 is connected to the output end of the current source I6 and the input end of the inverter INV3. The input end of the current source I5 is connected to the power signal VDD of the low-voltage domain power rail, the input end of the current source I6 is connected to the power signal VDD of the low-voltage domain power rail, the other end of the capacitor C3 is connected to the ground signal GND of the low-voltage domain power rail, the other end of the capacitor C4 is connected to the ground signal GND of the low-voltage domain power rail, the input end of the inverter INV1 is connected to the input signal VIN, the output end of the inverter INV2 is connected to the other input end of the NAND gate NAND1, the output end of the inverter INV3 is connected to the other input end of the NAND gate NAND2, the output end of the NAND gate NAND1 is connected to the source of the high-voltage enhanced NHEMT tube HMN1, and the output end of the NAND gate NAND2 is connected to the source of the high-voltage enhanced NHEMT tube HMN2.

[0042] The level conversion branch is composed of a first level conversion branch and a second level conversion branch. The first level conversion branch includes enhanced NHEMT tubes MN17 and MN19, a high-voltage enhanced NHEMT tube HMN1, and a resistor R1. The second level conversion branch includes enhanced NHEMT tubes MN18 and MN20, a high-voltage enhanced NHEMT tube HMN2, and a resistor R2. The connection mode of the first level conversion branch is as follows: the gate of the high-voltage enhanced NHEMT tube HMN1 is connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NHEMT tube HMN1 is connected to one end of the resistor R1, the drain of the enhanced NHEMT tube MN17, the source of the enhanced NHEMT tube MN19, the gate of the enhanced NHEMT tube MN19, the source of the enhanced NHEMT tube MN1, and the source of the enhanced NHEMT tube MN2, the source of the high-voltage enhanced NHEMT tube HMN1 is connected to the output end of the NAND gate NAND1, the gate of the enhanced NHEMT tube MN17 is connected to the source of the enhanced NHEMT tube MN17 and the ground signal VS of the high-voltage domain power rail, the drain of the enhanced NHEMT tube MN19 is connected to the power signal VBSTH of the high-voltage domain power rail, and the other end of the resistor R1 is connected to the power signal VBSTH of the high-voltage domain power rail. The connection method of the second level conversion branch is as follows: the gate of the high-voltage enhanced NHEMT tube HMN2 is connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NHEMT tube HMN2 is connected to one end of the resistor R2, the drain of the enhanced NHEMT tube MN18, the source of the enhanced NHEMT tube MN20, the gate of the enhanced NHEMT tube MN20, the source of the enhanced NHEMT tube MN3, and the source of the enhanced NHEMT tube MN4, the source of the high-voltage enhanced NHEMT tube HMN2 is connected to the output end of the NAND gate NAND2, the gate of the enhanced NHEMT tube MN18 is connected to the source of the enhanced NHEMT tube and the ground signal VS of the high-voltage domain power rail, the drain of the enhanced NHEMT tube MN20 is connected to the power signal VBSTH of the high-voltage domain power rail, and the other end of the resistor R2 is connected to the power signal VBSTH of the high-voltage domain power rail.

[0043] The noise elimination circuit includes: enhancement-type NHEMT tubes MN1-MN4, depletion-type NHEMT tubes MN9-MN12, and resistors R5-R8. The connection mode of the noise elimination circuit is as follows: the gate of the enhanced NHEMT tube MN1 is connected to the gate of the enhanced NHEMT tube MN4 and the drain of the enhanced NHEMT tube MN1; the drain of the enhanced NHEMT tube MN1 is connected to the gate of the depletion type NHEMT tube MN9 and one end of the resistor R5; the source of the enhanced NHEMT tube MN1 is connected to the source of the enhanced NHEMT tube MN2 and the drain of the high-voltage enhanced NHEMT tube HMN1; the gate of the enhanced NHEMT tube MN2 is connected to the gate of the enhanced NHEMT tube MN3 and the drain of the enhanced NHEMT tube MN3; the drain of the enhanced NHEMT tube MN2 is connected to the gate of the depletion type NHEMT tube MN10, one end of the resistor R6, one end of the resistor R3 and one end of the capacitor C1; the drain of the enhanced NHEMT tube MN3 is connected to the gate of the depletion type NHEMT tube MN11 and one end of the resistor R7; the source of the enhanced NHEMT tube MN3 is connected to the source of the enhanced NHEMT tube MN2 and the drain of the high-voltage enhanced NHEMT tube HMN1; The source of MN4 and the drain of the high-voltage enhancement type NHEMT tube HMN2, the drain of the enhancement type NHEMT tube MN4 is connected to the gate of the depletion type NHEMT tube MN12, one end of the resistor R8, one end of the resistor R4, and one end of the capacitor C2, the drain of the depletion type NHEMT tube MN9 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN9 is connected to the other end of the resistor R5, the drain of the depletion type NHEMT tube MN10 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN10 is connected to the other end of the resistor R6, the drain of the depletion type NHEMT tube MN11 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN11 is connected to the other end of the resistor R7, the drain of the depletion type NHEMT tube MN12 is connected to the power signal VBSTH of the high-voltage domain power rail, and the source of the depletion type NHEMT tube MN12 is connected to the other end of the resistor R8.

[0044] The negative VS tolerance improvement circuit is composed of a first negative VS tolerance improvement circuit and a second negative VS tolerance improvement circuit. The first negative VS tolerance improvement circuit includes: enhanced NHEMT tubes MN5, MN6, MN13, MN14, resistor R3, capacitor C1. The second negative VS tolerance improvement circuit includes: enhanced NHEMT tubes MN7-MN8, MN15-MN16, resistor R4, capacitor C2. The connection mode of the first negative VS tolerance enhancement circuit is as follows: the gate of the enhanced NHEMT tube MN5 is connected to the drain of the enhanced NHEMT tube MN5, the source of the enhanced NHEMT tube MN14, the gate of the enhanced NHEMT tube MN6, and the other end of the capacitor C1; the source of the enhanced NHEMT tube MN5 is connected to the ground signal VS of the high-voltage domain power rail; the source of the enhanced NHEMT tube M6 is connected to the IRESET end of the latch module; the source of the enhanced NHEMT tube MN6 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN13 is connected to the drain of the enhanced NHEMT tube MN13 and the other end of the resistor R3; the source of the enhanced NHEMT tube MN13 is connected to the drain of the enhanced NHEMT tube MN14 and the gate of the enhanced NHEMT tube MN14. The connection method of the second negative VS tolerance improvement circuit is as follows: the gate of the enhanced NHEMT tube MN7 is connected to the drain of the enhanced NHEMT tube MN7, the source of the enhanced NHEMT tube MN16, the gate of the enhanced NHEMT tube MN8, and the other end of the capacitor C2; the source of the enhanced NHEMT tube MN7 is connected to the ground signal VS of the high-voltage domain power rail; the source of the enhanced NHEMT tube M8 is connected to the ISET end of the latch module; the source of the enhanced NHEMT tube MN8 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN15 is connected to the drain of the enhanced NHEMT tube MN15 and the other end of the resistor R4; the source of the enhanced NHEMT tube MN15 is connected to the drain of the enhanced NHEMT tube MN16 and the gate of the enhanced NHEMT tube MN16.

[0045] The latch module includes: enhanced NHEMT tubes MN23 to MN26, resistors R9 to R12, and an inverter INV4. The connection method of the latch module is: the gate of the enhanced NHEMT tube MN23 is connected to the drain of the enhanced NHEMT tube MN6 and one end of R9, the drain of the enhanced NHEMT tube MN23 is connected to the drain of the enhanced NHEMT tube MN24, the gate of the enhanced NHEMT tube MN26, and one end of the resistor R10, the source of the enhanced NHEMT tube MN23 is connected to the ground signal VS of the high-voltage domain power rail, the gate of the enhanced NHEMT tube MN24 is connected to the drain of the enhanced NHEMT tube MN26, the drain of the enhanced NHEMT tube MN25, the input end of the inverter INV4, one end of the resistor R12, and the source of the enhanced NHEMT tube MN24 is connected to the ground signal VS of the high-voltage domain power rail. The gate of the enhanced NHEMT tube MN25 is connected to the ground signal VS of the high-voltage domain power rail, the gate of the enhanced NHEMT tube MN25 is connected to the drain of the enhanced NHEMT tube MN8 and one end of the resistor R11, the source of the enhanced NHEMT tube MN25 is connected to the ground signal VS of the high-voltage domain power rail, the source of the enhanced NHEMT tube MN26 is connected to the ground signal VS of the high-voltage domain power rail, the other end of the resistor R9 is connected to the power signal VBSTL of the high-voltage domain power rail, the other end of the resistor R10 is connected to the power signal VBSTL of the high-voltage domain power rail, the other end of the resistor R11 is connected to the power signal VBSTL of the high-voltage domain power rail, and the other end of the resistor R12 is connected to the power signal VBSTL of the high-voltage domain power rail.

[0046] Figure 1 This is a typical application diagram of the present invention in a gallium nitride half-bridge power chip. Except that the high-voltage level shift circuit adopts a level shift circuit proposed by the present invention to improve the reliability of the gallium nitride half-bridge power chip, the rest of the structure is the same as the prior art. The interior of the gallium nitride half-bridge power chip can be divided into a half-bridge drive circuit and power tubes T1 and T2. The half-bridge drive circuit has a high-voltage basin area and a low-voltage basin area. The gallium nitride power tubes T1 and T2 are respectively used as high-side power tubes and low-side power tubes. VBUS is the bus voltage of the T1 tube, and VS is the switch node of the T1 and T2 tubes and is connected to the peripheral inductor. The diode D1 and the capacitor C1 constitute a floating power supply VBST to supply power to the high-voltage basin area. The microcontroller unit MCU transmits input signals HIN and LIN, which pass through the drive circuit of the gallium nitride half-bridge power chip to control the opening and closing of the power tubes T1 and T2, wherein the VS point potential floats between the low basin low signal and the high basin low signal. The core of the half-bridge drive circuit is the high-voltage level shift circuit, which can convert the signal from the low-voltage domain power rail to the high-voltage domain power rail to achieve the control of the high-voltage circuit system by the low-voltage signal.

[0047] Figure 2It is a structural diagram of a traditional level shift circuit, including a pulse generating circuit, a level conversion branch, an RC filter circuit, and an RS trigger circuit. The input signal VIN is a pulse width modulation signal generated by the previous control circuit. The pulse generating circuit detects the rising and falling edges of VIN, and generates two sets of narrow pulse signals, SET and RESET, respectively. The narrow pulse signal RESET corresponding to the rising edge of VIN is input to the gate of MN2, and the narrow pulse signal SET corresponding to the falling edge of VIN is input to the gate of MN1. The level conversion branch can convert the original low-voltage domain signal into a high-voltage domain signal VS-VBSTH. When the pulse reaches the gate of MN1 or MN2, it turns it on, pulls the corresponding drain end to a low potential, and turns on HMN1 or HMN2. Among them, HMN1 and HMN2 are high-voltage enhanced NHEMT tubes, and their function is to prevent the VDS voltage at both ends of MN1 and MN2 from being too large and causing breakdown. Due to the large parasitic capacitance of the high-voltage tube, the rapid change of VS under high-frequency operation will generate dVS / dt noise at the X and Y nodes due to the large drain-source parasitic capacitance of HMN1 and HMN2. The RC filter circuit can eliminate part of the dVS / dt noise, but it will produce a large delay, affecting the transmission speed of the circuit. Finally, the RS trigger circuit restores the pulse signal after filtering to a level signal output to complete the level shift. Among them, D1 and D2 clamp the potential of the X and Y points so that it will not be too much lower than VS.

[0048] Figure 3(a) is a working waveform diagram of a traditional level shift circuit under the influence of dVS / dt noise. When VIN is high or low, both ports of the pulse generation circuit output low, and MN1 and MN2 remain in the off state. The source ends of HMN1 and HMN2 are at a high potential, and the two high-voltage tubes remain off. At this time, points X and Y remain at a high level. When the rising edge of VIN arrives, a pulse signal is generated through the pulse generation circuit, which turns on MN2 and pulls the source end of HMN2 to a low potential. The HMN2 tube is turned on to pull point Y to a low potential. After the pulse ends, point Y becomes high again. Similarly, when the falling edge of VIN arrives, the MN1 tube is turned on to pull down the source end of HMN1 to make it conductive, and the potential of point X is pulled down to ground. When the pulse ends, point X returns to a high level. When VS rises from GND to VS, positive dVS / dt noise is generated, which will cause the potentials of points X and Y to decrease at the same time. When the RS trigger circuit receives this signal, it will enter an indeterminate state, which may cause the circuit output logic to be disordered and affect the normal operation of the chip. When VS drops from GND to VS, negative dVS / dt noise is generated, which causes the potentials at points X and Y to rise simultaneously. From the perspective of circuit logic, this does not affect the operation of the RS trigger circuit.

[0049] Figure 3(b) shows the working waveform of the traditional level shift circuit under the influence of negative VS. Under the inductance of the power system, VS will generate negative voltage during the dead zone. If the absolute value of the VS negative voltage exceeds the threshold of the RC filter circuit, the output signal of the previous level conversion branch is low level GND, which will exceed the trigger voltage of the RC filter circuit. At this time, the RC filter circuit will misjudge the low level signal as a high level signal, causing the subsequent circuit to no longer respond to the input of the previous stage.

[0050] Figure 4 This is a specific structural diagram of the level shifting circuit for improving the reliability of the gallium nitride half-bridge power chip proposed in the present invention. The pulse generating circuit and the first level conversion branch and the second level conversion branch with similar functions in the traditional level shifting circuit are retained, and a noise elimination circuit, a first negative VS tolerance improvement circuit, a second negative VS tolerance improvement circuit and a latch module are newly added.

[0051] The noise elimination circuit is composed of current sources I1 to I4 and enhanced NHEMT tubes MN1 to MN4. The current sources I1, I4 and MN1, MN4 form a common gate comparison circuit, and similarly, the current sources I2, I3 and MN2, MN3 form a common gate comparison circuit. In particular, the current values ​​of the current sources I1 and I3 are equal, and the current values ​​of the current sources I2 and I4 are equal; the sizes of MN1 and MN3 are equal, and the sizes of MN2 and MN4 are equal.

[0052] The first negative VS tolerance improvement circuit is composed of a resistor R3, an enhanced NHEMT tube MN5, an enhanced NHEMT tube MN6, and a capacitor C1. The second negative VS tolerance improvement circuit is composed of a resistor R4, an enhanced NHEMT tube MN7, an enhanced NHEMT tube MN8, and a capacitor C2. The first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit are symmetrical in structure, and the resistor R3 and the resistor R4 have the same device size, the capacitor C1 and the capacitor C2 have the same size, the enhanced NHEMT tube MN5 and the enhanced NHEMT tube MN7 have the same size, and the enhanced NHEMT tube MN6 and the enhanced NHEMT tube MN8 have the same size.

[0053] Table 1 is a truth table of the latch module, and the working principle of the structure of the present invention is explained in conjunction with the truth table.

[0054] ISET IRESET VOUT 0 1 0 1 0 1 1 1 Keep 0 0 Unsteady state

[0055] When the input VIN remains unchanged, the voltage values ​​at points X and Y are the same and both are high, and transistors MN1 to MN4 remain closed. The current of the current source I2 flows to the first negative VS tolerance boosting circuit, MN5 and MN6 form a current mirror circuit, and the current is copied to the input of the latch module through MN5. Similarly, the current of the current source I4 flows to the second negative VS tolerance boosting circuit, MN7 and MN8 form a current mirror circuit, and the current is copied to the input of the latch module through MN7. When current flows into both ports of the latch module, that is, ISET and IRESET are both 1, the output VOUT state remains unchanged.

[0056] When the falling edge of the input VIN arrives, a pulse signal will pass through the R1 branch through the pulse generating circuit. During the duration of the pulse signal, the potential at point X is low and point Y remains high, that is, VX is less than VY. Transistor MN2 will turn on, and the current of the current mirror I2 will no longer flow to the first negative VS tolerance boosting circuit, but will flow to the MN2 branch with a smaller impedance, and then flow to GND through point X. Therefore, there is no more current flowing into the left latch module, but there is still current flowing into the right side, that is, IRSET is 0, ISET is 1, and after receiving the signal, the latch module sets the output VOUT to low. After the pulse ends, the potential at point X returns to a high level, and there is no longer a voltage difference between points X and Y. The MN2 tube is turned off, and I2 flows into the first negative VS tolerance boosting circuit again, but the latch module still maintains the previous state.

[0057] When the rising edge of input VIN arrives, similar to the falling edge, transistor MN4 turns on, point Y is pulled low, and the current of current mirror I4 flows from point Y to GND through MN4, and no longer flows to the second negative VS tolerance boosting circuit. There is no more current flowing into the latch module on the right, but there is still current flowing into the left, that is, IRSET is 1, ISET is 0, and after receiving the signal, the latch module sets the output VOUT to high. After the pulse ends, the potential at point Y returns to a high level, MN4 is turned off, and I4 flows into the second negative VS tolerance boosting circuit again, but the latch module still maintains the previous state.

[0058] dVS / dt noise exists in the form of common mode. When positive dVS / dt noise is generated, the potentials of points X and Y drop at the same time, that is, points X and Y still maintain the same potential. Therefore, transistors MN2 and MN4 will not turn on, and the latch module will continue to be in the hold state. When negative dVS / dt noise is generated, the voltages of points X and Y rise at the same time, and the potentials of the two points remain the same. The latch module is in the hold state, thereby eliminating the influence of dVS / dt noise.

[0059] When the edge of VIN comes, the potential at point X or Y is pulled down to GND. Even if the inductance of the peripheral circuit causes VS to generate negative voltage, the potential at VS is less than the potential at point X or Y. However, since the voltage signals at points VX and VY are converted into current signals flowing through MN5 and MN7, the triggering of the latch module will not be affected by the voltage difference between VS and GND. In particular, in order to ensure that when VX or VY is at a low level, the current of I2 or I4 is shunted by MN2 or MN4 as much as possible, the number of transistors in series in the R3 and MN5 branches in the first negative VS tolerance boosting circuit can be appropriately increased, for example, a transistor with a gate-drain short circuit is added to R3 or MN5. To maintain symmetry, components of the same size also need to be added to the corresponding positions in the second negative VS tolerance boosting circuit.

[0060] FIG5(a) is a specific embodiment of a level shift circuit for improving the reliability of a gallium nitride half-bridge power chip proposed by the present invention, which is used to realize the conversion of a signal in a low-voltage domain to a high-voltage domain, including a pulse generating circuit, a first level conversion branch, a second level conversion branch, a noise elimination circuit, a first negative VS tolerance enhancement circuit, a second negative VS tolerance enhancement circuit, and a latch module. Among them, the low-voltage domain power rail is the ground signal GND-power signal VDD, and the high-voltage domain power rail is the half-bridge switch node signal VS-bootstrap power signal VBSTH. Among them, the latch module may use a different power rail as the half-bridge switch node signal VS-bootstrap power signal VBSTL, which can be generated by the power rail VS-VBSTH, and the voltage value of the power rail VS-VBSTL is usually lower than VS-VBSTH.

[0061] The first level conversion branch and the second level conversion branch are completely symmetrical, including enhanced NHEMT tubes MN17 to MN20, high-voltage enhanced NHEMT tubes HMN1 and HMN2, and resistors R1 and R2. Taking the first level conversion branch and the second level conversion branch as an example, the working principle is as follows: the gate of the HMN1 tube is connected to VDD. When the RESET pulse signal arrives, the source of the HMN1 tube is pulled down to GND, then HMN11 is turned on, and point X is pulled down to GND. When the pulse ends, the source of the HMN1 tube becomes a high level VDD, HMN1 is turned off, and point X becomes a high level. MN17 adopts a diode connection method, and its function is to clamp the voltage at point X so that it will not be too much lower than VS, preventing the subsequent stage devices from overvoltage breakdown. MN19 adopts a diode connection method, and its function is to clamp the voltage at point X so that it will not be too much higher than VBSTH, preventing the subsequent stage devices from overvoltage breakdown.

[0062] The noise elimination circuit includes enhanced NHEMT tubes MN1 to MN4, depletion NHEMT tubes MN9 to MN12, and resistors R5 to R8. NHEMT tubes MN1, MN4, MN9, MN12 and resistors R5 and R8 form a first pair of common-gate comparison circuits, in which depletion-type NHEMT tubes MN9 and MN12 respectively form current sources with R5 and R8. Similarly, NHEMT tubes MN2, MN3, MN10, MN11 and resistors R6 and R7 form a second pair of common-gate comparison circuits, in which depletion-type NHEMT tubes MN10 and MN11 respectively form current sources with R6 and R7. The above structure controls the on and off of MN2 and MN4 by comparing the potentials of points X and Y, and converts the voltage pulse signal of the previous stage into a current signal to be transmitted to the next stage. The working principle is as follows: when the input voltage VIN remains unchanged, the potentials of point X and point Y are equal, then MN1 and MN4 are turned off, the left current source is turned off, and the current of the right current source flows to the second negative VS tolerance boosting circuit; when the rising edge of VIN arrives, a pulse arrives at point Y, during the pulse, point Y is at a low potential, and point X maintains a high potential. At this time, MN4 is turned on, and the current of the right current source flows to point Y through MN4, and no longer flows to the second negative VS tolerance boosting circuit with higher impedance. MN1 continues to remain off. After the pulse ends, MN4 is turned off and returns to the previous state, but the latch module maintains the changed state; when the falling edge of VIN arrives, a pulse arrives at point X. During the pulse, point X is at a low potential, and point Y maintains a high potential. At this time, MN2 is turned on, and the current of the left current source flows to point X through MN2, and MN4 remains off. After the pulse ends, MN2 is turned off and returns to the previous state.

[0063] The first negative VS tolerance boosting circuit and the second negative VS tolerance boosting circuit are completely symmetrical, including enhanced NHEMT tubes MN5-MN8, MN13-MN16, resistors R3-R4, and capacitors C1 and C2. As mentioned above, the first negative VS tolerance boosting circuit increases the number of HEMT transistors on the basis of the previous one, and the second negative VS tolerance boosting circuit increases the number of HEMT transistors on the basis of the previous one. Taking the first negative VS tolerance boosting circuit on the left as an example, MN5, MN13, and MN14 are connected in series, and MN5 and MN6 form a current mirror structure. When MN2 is turned off, the current source current flows into the branch where R3, MN13, MN14 and MH5 are located, and MN5, MN13, and MN14 are turned on. After the current mirror, the current is copied as the input current IRESET of the latch module; when MN2 is turned on, the potential of point N3 is VBSTH, and there is no input current IRESET at this time. MN5, MN13, and MN14 are connected in series using diodes. When the input is a voltage signal, the branch will only be turned on when the potential on both sides is greater than three times VTH. If the negative voltage value that VS can withstand needs to be adjusted, it can be adjusted by adjusting the number of MOS tubes in series or changing the resistance value of resistor R3. Capacitor C1 can store charge and accelerate the reduction of the gate voltage of MN6 when a pulse is triggered, thereby accelerating the closing of MN6.

[0064] FIG5(b) is a specific circuit diagram of a pulse generating circuit, which is used to convert an input signal into pulse signals SET and RESET, and includes enhanced NHEMT tubes MN21-MN22, capacitors C3-C4, inverters INV1-INV3, NAND gates NAND1-NAND2, and current sources I5-I6. The working principle is as follows: the current source I3, transistor MN21, and capacitor C3 form an inverter that can generate a falling edge delay. The input signal VIN passes through the inverter to generate a falling edge delayed signal, and then passes through the inverter INV2 to restore it to a signal with the same direction as VIN and a falling edge delay, and is transmitted to one input end of the NAND gate NAND1. The other input end of NAND1 is connected to the input signal VIN to generate a pulse signal RESET of the falling edge of VIN. Similarly, the input signal VIN passes through the inverter INV1 to generate a reverse signal, and then passes through the above structure to generate a rising edge pulse signal SET of VIN.

[0065] Figure 5(c) is a specific circuit diagram of the latch module, which is used to convert the current signals IRESET and ISET into voltage and output it, including enhanced NHEMT tubes MN23~MN26, resistors R9~R12, and inverter INV4. The power signal of the high-voltage domain power rail of the latch module is VBSTL, and the working principle is as follows: when the input currents IRESET and ISET are both 1, MN23 and MN25 are both kept off, and VOUT is in a holding state; when IRESET is 1 and ISET is 0, MN25 is turned on, and the input end of INV4 is pulled down to a low level, and INV4 outputs a high level. At the same time, the gate of MN24 is low, MN24 is turned off, and the gate of MN26 is high, MN26 is turned on, and the drain potential of MN26 increases, forming a positive feedback; similarly, when IRESET is 0 and ISET is 1, a low level is output.

[0066] Figure 6 It is a working waveform diagram of a level shifting circuit for improving the reliability of a gallium nitride half-bridge power chip proposed by the present invention, wherein VOUT1 is an output waveform diagram without a noise elimination circuit, VOUT2 is an output waveform diagram without a negative VS tolerance enhancement circuit, and VOUT3 is an output waveform diagram of this circuit. When the input signal is at a low level, the potential of VS is less than 0 at this time. When the input signal VIN changes from a low level to a high level, the pulse generating circuit outputs a SET pulse signal. During the pulse, HMN2 is turned on, and the potential of point Y is pulled down to a low level. The potential of point X is higher than the potential of point Y. The second negative VS tolerance enhancement circuit has no more current flowing into the negative VS tolerance enhancement circuit, and the potential of point N4 decreases, and the signal is transmitted to the latch module, and a high level is output. If there is no second negative VS tolerance enhancement circuit, transistor MN8 will still remain turned on, and ISET current will flow in, and the latch module will still be in a holding state, as shown in VOUT2, and the output signal will be lost. After the pulse ends, point Y changes back to a high level, point N4 changes back to a high level, and VOUT enters a latched state. Under the action of the peripheral circuit, VS rises rapidly from GND to VS, generating positive dVS / dt noise, and the potentials of X and Y points drop synchronously. The potentials of points X and Y remain the same. Under the action of the second negative VS tolerance enhancement circuit, the false start signal will not be transmitted to the next stage to eliminate the influence of dVS / dt noise. If there is no noise elimination circuit, the potentials of points X and Y drop synchronously, and the ISET and IRESET received by the latch module are both 0, and the output VOUT1 enters an indeterminate state. For negative dVS / dt noise, due to the action of transistors MN17 to MN20, the potentials of points X and Y are between VS-VTH and VBSTH+VTH, preventing the subsequent circuit from breaking down. The same is true when the input signal VIN changes from a high level to a low level.

[0067] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A level shift circuit for improving the reliability of a gallium nitride half-bridge power chip, characterized in that: include: A pulse generating circuit, a first level conversion branch, a second level conversion branch, a noise elimination circuit, a first negative VS tolerance improvement circuit, a second negative VS tolerance improvement circuit, and a latch module; The input signal VIN is connected to the input end of the pulse generating circuit; the input signal of the pulse generating circuit is VIN, which is used to convert the input signal VIN into two narrow pulse signals RESET and SET, the output point of the narrow pulse signal RESET is connected to the input end of the first level conversion branch, and the output point of the narrow pulse signal SET is connected to the input end of the second level conversion branch; the input signals of the first level conversion branch and the second level conversion branch are the output signals RESET and SET of the pulse generating circuit, the first level conversion branch and the second level conversion branch are used to convert the input two pulse signals from the low voltage domain to the high voltage domain, the output end of the first level conversion branch is point X, and the output end of the second level conversion branch is point Y, and point X and point Y are respectively connected to the two input ends of the noise elimination circuit; the input signal of the noise elimination circuit is the output of the first level conversion branch and the second level conversion branch. The output signal is used to suppress the influence of dVS / dt noise and convert the output signals of the first level conversion branch and the second level conversion branch into current signals. The output ends of the noise elimination circuit are respectively the input ends of the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit; the input signals of the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit are the two output signals of the noise elimination circuit, which are used to improve the negative VS tolerance capability of the level shifting circuit. The output current signals are IRESET and ISET, respectively. The output points of the current signals IRESET and ISET are respectively connected to the two input ends of the latch module; the input signals of the latch module are the current signals IRESET and ISET output by the first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit, which are used to convert the current signals IRESET and ISET into the output voltage signal VOUT.

2. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 1, characterized in that: The pulse generating circuit includes enhanced NHEMT tubes MN21 and MN22, current sources I5 and I6, capacitors C3 and C4, inverters INV1 to INV3, and NAND gates NAND1 and NAND2; The gate of the enhanced NHEMT tube MN21 is connected to the input signal VIN and an input end of the NAND gate NAND1. The drain of the enhanced NHEMT tube MN21 is connected to the output end of the current source I5, the input end of the inverter INV2, and one end of the capacitor C3. The source of the enhanced NHEMT tube MN21 is connected to the ground signal GND of the low-voltage domain power rail. The gate of the enhanced NHEMT tube MN22 is connected to the output end of the inverter INV1 and an input end of the NAND gate NAND2. The drain of the enhanced NHEMT tube MN22 is connected to the output end of the current source I6, the input end of the inverter INV3, and one end of the capacitor C4. The source of the enhanced NHEMT tube MN22 is connected to the ground signal GND of the low-voltage domain power rail. The ground signal GND, the input end of the current source I5 is connected to the power signal VDD of the low-voltage domain power rail, the input end of the current source I6 is connected to the power signal VDD of the low-voltage domain power rail, the other end of the capacitor C3 is connected to the ground signal GND of the low-voltage domain power rail, the other end of the capacitor C4 is connected to the ground signal GND of the low-voltage domain power rail, the input end of the inverter INV1 is connected to the input signal VIN, the output end of the inverter INV2 is connected to the other input end of the NAND gate NAND1, the output end of the inverter INV3 is connected to the other input end of the NAND gate NAND2, the output end of the NAND gate NAND1 is connected to the input end of the first level conversion branch, and the output end of the NAND gate NAND2 is connected to the input end of the second level conversion branch.

3. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 2, characterized in that: The first level conversion branch and the second level conversion branch both include enhanced NHEMT tubes MN17-MN20, high-voltage enhanced NHEMT tubes HMN1, HMN2, and resistors R1, R2; The gate of the high-voltage enhanced NHEMT tube HMN1 is connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NHEMT tube HMN1 is connected to one end of the resistor R1, the drain of the enhanced NHEMT tube MN17, the source of the enhanced NHEMT tube MN19, the gate of the enhanced NHEMT tube MN19, the source of the enhanced NHEMT tube MN1, and the source of the enhanced NHEMT tube MN2. The source of the high-voltage enhanced NHEMT tube HMN1 is connected to the output end of the NAND gate NAND1, the gate of the enhanced NHEMT tube MN17 is connected to the source of the enhanced NHEMT tube MN17 and the ground signal VS of the high-voltage domain power rail, the drain of the enhanced NHEMT tube MN19 is connected to the power signal VBSTH of the high-voltage domain power rail, and the other end of the resistor R1 is connected to the power signal VBST of the high-voltage domain power rail. H, the gate of the high-voltage enhanced NHEMT tube HMN2 is connected to the power signal VDD of the low-voltage domain power rail, the drain of the high-voltage enhanced NHEMT tube HMN2 is connected to one end of the resistor R2, the drain of the enhanced NHEMT tube MN18, the source of the enhanced NHEMT tube MN20, the gate of the enhanced NHEMT tube MN20, the source of the enhanced NHEMT tube MN3, and the source of the enhanced NHEMT tube MN4, the source of the high-voltage enhanced NHEMT tube HMN2 is connected to the output end of the NAND gate NAND2, the gate of the enhanced NHEMT tube MN18 is connected to the source of the enhanced NHEMT tube and the ground signal VS of the high-voltage domain power rail, the drain of the enhanced NHEMT tube MN20 is connected to the power signal VBSTH of the high-voltage domain power rail, and the other end of the resistor R2 is connected to the power signal VBSTH of the high-voltage domain power rail.

4. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 3, characterized in that: The noise elimination circuit includes: enhanced NHEMT tubes MN1-MN4, depletion NHEMT tubes MN9-MN12, and resistors R5-R8; The gate of the enhanced NHEMT tube MN1 is connected to the gate of the enhanced NHEMT tube MN4 and the drain of the enhanced NHEMT tube MN1. The drain of the enhanced NHEMT tube MN1 is connected to the gate of the depletion-type NHEMT tube MN9 and one end of the resistor R5. The source of the enhanced NHEMT tube MN1 is connected to the source of the enhanced NHEMT tube MN2 and the drain of the high-voltage enhanced NHEMT tube HMN1. The gate of the enhanced NHEMT tube MN2 is connected to the gate of the enhanced NHEMT tube MN3 and the drain of the enhanced NHEMT tube MN3. The drain of the enhanced NHEMT tube MN2 is connected to the gate of the depletion-type NHEMT tube MN10, one end of the resistor R6, one end of the resistor R3, and one end of the capacitor C1. The drain of the enhanced NHEMT tube MN3 is connected to the gate of the depletion-type NHEMT tube MN11 and one end of the resistor R7. The source of the enhanced NHEMT tube MN3 is connected to the source of the enhanced NHEMT tube MN4. , the drain of the high-voltage enhancement type NHEMT tube HMN2, the drain of the enhancement type NHEMT tube MN4 is connected to the gate of the depletion type NHEMT tube MN12, one end of the resistor R8, one end of the resistor R4, and one end of the capacitor C2, the drain of the depletion type NHEMT tube MN9 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN9 is connected to the other end of the resistor R5, the drain of the depletion type NHEMT tube MN10 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN10 is connected to the other end of the resistor R6, the drain of the depletion type NHEMT tube MN11 is connected to the power signal VBSTH of the high-voltage domain power rail, the source of the depletion type NHEMT tube MN11 is connected to the other end of the resistor R7, the drain of the depletion type NHEMT tube MN12 is connected to the power signal VBSTH of the high-voltage domain power rail, and the source of the depletion type NHEMT tube MN12 is connected to the other end of the resistor R8.

5. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 4, characterized in that: The depletion-type NHEMT tubes MN9 to MN12 and the resistors R5 to R8 respectively form current sources I1 to I4.

6. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 5, characterized in that: The current values ​​of the current source I1 and the current source I3 are equal, and the current values ​​of the current source I2 and the current source I4 are equal; the sizes of the enhanced NHEMT tube MN1 and the enhanced NHEMT tube MN3 are equal, and the sizes of the enhanced NHEMT tube MN2 and the enhanced NHEMT tube MN4 are equal.

7. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 4, characterized in that: The first negative VS tolerance improvement circuit and the second negative VS tolerance improvement circuit both include: enhanced NHEMT tubes MN5-MN8, MN13-MN16, resistors R3, R4, capacitors C1, C2; The connection mode of the first negative VS tolerance improvement circuit is as follows: the gate of the enhanced NHEMT tube MN5 is connected to the drain of the enhanced NHEMT tube MN5, the source of the enhanced NHEMT tube MN14, the gate of the enhanced NHEMT tube MN6, and the other end of the capacitor C1; the source of the enhanced NHEMT tube MN5 is connected to the ground signal VS of the high-voltage domain power rail; the source of the enhanced NHEMT tube M6 is connected to the IRESET end of the latch module; the source of the enhanced NHEMT tube MN6 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN13 is connected to the drain of the enhanced NHEMT tube MN13 and the other end of the resistor R3; the source of the enhanced NHEMT tube MN13 is connected to the drain of the enhanced NHEMT tube MN14 and the gate of the enhanced NHEMT tube MN14; The connection method of the second negative VS tolerance improvement circuit is as follows: the gate of the enhanced NHEMT tube MN7 is connected to the drain of the enhanced NHEMT tube MN7, the source of the enhanced NHEMT tube MN16, the gate of the enhanced NHEMT tube MN8, and the other end of the capacitor C2; the source of the enhanced NHEMT tube MN7 is connected to the ground signal VS of the high-voltage domain power rail; the source of the enhanced NHEMT tube M8 is connected to the ISET end of the latch module; the source of the enhanced NHEMT tube MN8 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN15 is connected to the drain of the enhanced NHEMT tube MN15 and the other end of the resistor R4; the drain of the enhanced NHEMT tube MN15 is connected to the gate of the enhanced NHEMT tube MN16, and the drain of the enhanced NHEMT tube MN15 is connected to the drain of the enhanced NHEMT tube MN16.

8. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 7, characterized in that: The first negative VS tolerance boosting circuit and the second negative VS tolerance boosting circuit have symmetrical structures, and the resistors R3 and R4 have the same device size, the capacitors C1 and C2 have the same size, the enhanced NHEMT tubes MN5 and MN7 have the same size, and the enhanced NHEMT tubes MN6 and MN8 have the same size.

9. The level shift circuit for improving the reliability of a gallium nitride half-bridge power chip according to claim 7, characterized in that: The latch module includes: enhanced NHEMT tubes MN23-MN26, resistors R9-R12, and an inverter INV4; The connection mode of the latch module is as follows: the gate of the enhanced NHEMT tube MN23 is connected to the drain of the enhanced NHEMT tube MN6 and one end of R9; the drain of the enhanced NHEMT tube MN23 is connected to the drain of the enhanced NHEMT tube MN24, the gate of the enhanced NHEMT tube MN26, and one end of the resistor R10; the source of the enhanced NHEMT tube MN23 is connected to the ground signal VS of the high-voltage domain power rail; the gate of the enhanced NHEMT tube MN24 is connected to the drain of the enhanced NHEMT tube MN26, the drain of the enhanced NHEMT tube MN25, the input end of the inverter INV4, and one end of the resistor R12; the source of the enhanced NHEMT tube MN24 is connected to the ground signal VS of the high-voltage domain power rail; The gate of the enhanced NHEMT tube MN25 is connected to the ground signal VS of the high-voltage domain power rail, the gate of the enhanced NHEMT tube MN25 is connected to the drain of the enhanced NHEMT tube MN8 and one end of the resistor R11, the source of the enhanced NHEMT tube MN25 is connected to the ground signal VS of the high-voltage domain power rail, the source of the enhanced NHEMT tube MN26 is connected to the ground signal VS of the high-voltage domain power rail, the other end of the resistor R9 is connected to the power signal VBSTL of the high-voltage domain power rail, the other end of the resistor R10 is connected to the power signal VBSTL of the high-voltage domain power rail, the other end of the resistor R11 is connected to the power signal VBSTL of the high-voltage domain power rail, and the other end of the resistor R12 is connected to the power signal VBSTL of the high-voltage domain power rail.

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