Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes a substrate portion including a first insulating layer and a first wiring layer disposed on or in the first insulating layer; the connecting structure is arranged on the base plate part or in the base plate part; the connecting structure comprises a plurality of first dielectric layers, a first metal layer and a second metal layer which are respectively arranged on the plurality of first dielectric layers or in the plurality of first dielectric layers, and a second insulating layer arranged on the plurality of first dielectric layers, and a second wiring layer disposed on or in the second insulating layer. Each of the plurality of first dielectric layers includes an organic material. The distance between the first metal layer and the second metal layer is smaller than the distance between the first metal layer and the second wiring layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0091781 filed on July 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Multi-chip packages including memory chips such as high bandwidth memory (HBM), processor chips such as central processing units (CPUs), graphics processing units (GPUs), application specific integrated circuits (ASICs), and / or field programmable gate arrays (FPGAs) have been used to process data and have grown exponentially due to recent developments in artificial intelligence (AI) technology. In particular, as the number of CPU cores and GPU cores of server products has rapidly increased, die segmentation technology that can effectively increase the number of cores has become prevalent, and thus die-to-die interconnection is required. Research has been conducted to design a board including a connection structure that performs die-to-die interconnection, thereby achieving a simplified board and package structure, improving the reliability of the connection structure, and increasing yield. Summary of the invention

[0004] An aspect of the present disclosure provides a printed circuit board on which electronic components and semiconductor chips are mounted, the printed circuit board being capable of performing die-to-die interconnection.

[0005] Another aspect of the present disclosure provides a printed circuit board including a connection structure, which can implement a device function in addition to die-to-die interconnection.

[0006] Another aspect of the present disclosure provides a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a substrate portion, comprising a first insulating layer and a first wiring layer disposed on or in the first insulating layer; and a connection structure disposed on or in the substrate portion, the connection structure comprising a plurality of first dielectric layers, a first metal layer and a second metal layer respectively disposed on or in the plurality of first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on or in the second insulating layer. Each of the plurality of first dielectric layers may include an organic material. The distance between the first metal layer and the second metal layer may be smaller than the distance between the first metal layer and the second wiring layer.

[0008] According to another aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a substrate portion, comprising a first insulating layer and a first wiring layer disposed on or in the first insulating layer; and a connection structure disposed on or in the substrate portion, the connection structure comprising a capacitor portion and a wiring portion, the capacitor portion comprising a dielectric layer and a first metal layer disposed on or in the dielectric layer, the wiring portion comprising a second insulating layer and a second wiring layer disposed on or in the second insulating layer. The first metal layer may include a pair of metal plates facing each other. The dielectric layer may include an organic material.

[0009] According to example embodiments of the present disclosure, a printed circuit board on which electronic components and semiconductor chips are mounted may perform die-to-die interconnection.

[0010] According to example embodiments of the present disclosure, a printed circuit board including a connection structure may implement a device function in addition to die-to-die interconnection.

[0011] According to example embodiments of the present disclosure, a printed circuit board may have improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram illustrating an example of an electronic device system; Figure 2 is a schematic perspective view showing an example of an electronic device; Figure 3A and Figure 3B is a schematic cross-sectional view showing a printed circuit board according to an example; Figure 4 is a schematic cross-sectional view showing a printed circuit board according to another example; Figure 5 is a schematic cross-sectional view showing a printed circuit board according to another example; Fig. 6A is a schematic cross-sectional view showing a connection structure of a printed circuit board according to an example; Figure 6B is a schematic perspective view showing a capacitor portion of a connection structure of a printed circuit board according to an example; Fig. 7A is a schematic cross-sectional view showing a connection structure according to another example; Figure 7B is a schematic perspective view showing a capacitor portion of a connection structure according to another example; Fig. 8Ais a schematic cross-sectional view showing a connection structure according to another example; and Figure 8B is a schematic perspective view of a capacitor portion according to a connection structure of another example. DETAILED DESCRIPTION

[0013] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer explanation, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0014] Electronic Devices Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0015] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. These components may be connected to other components to be described below through various signal lines 1090.

[0016] The chip-related components 1020 may include a memory chip (such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM) or a flash memory)), an application processor chip (such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor or a microcontroller), and a logic chip (such as an analog-to-digital converter or an application-specific integrated circuit (ASIC)). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0017] The network-related component 1030 may implement or be compatible with protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data Rates for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth®, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G), Fourth Generation Mobile Communication Technology (4G) and Fifth Generation Mobile Communication Technology (5G) protocols, and any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also implement or be compatible with various other wireless or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0018] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or the network-related components 1030.

[0019] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that are physically or electrically connected to the main board 1010. The other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may further include other components for various purposes.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0021] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0022] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board, and the electronic components including active components and / or passive components are surface-mounted on the printed circuit board. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0023] Printed Circuit Board Figure 3A and Figure 3B is a schematic cross-sectional view illustrating a printed circuit board according to an example.

[0024] Reference Figure 3A , a printed circuit board according to an example may include a substrate portion 100 and a connection structure 200. The substrate portion 100 may be a portion that implements a signal path of the printed circuit board, and the connection structure 200 may be a portion that connects components such as chips to each other. The connection structure 200 may be a portion that implements a fine signal path in response to an electronic component such as a fine chip. An electronic component such as a plurality of chips may be provided with the connection structure 200 interposed therebetween. The connection structure 200 may be a portion that maintains an electrical signal path by interconnecting electronic components such as chips.

[0025] The substrate portion 100 may include a first insulating layer 110, a first wiring layer 120 disposed on or in the first insulating layer 110, and a cavity passing through at least a portion of the first insulating layer 110. The substrate portion 100 may further include a first via layer 130 passing through at least a portion of the first insulating layer 110 to connect the first wiring layers 120 to each other.

[0026] The first insulating layer 110 may include a plurality of insulating layers, and each of the first insulating layers 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (glass cloth and / or glass fabric) and such a resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 110 may be a prepreg (PPG), a resin coated copper (RCC), etc., but the present disclosure is not limited thereto, and may be an Ajinomoto build-up film (ABF, Ajinomoto build-up film), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, the present disclosure is not limited thereto. Other polymer materials with excellent rigidity may be used as needed.

[0027] The first wiring layer 120 may include a plurality of wiring layers, and each of the first wiring layers 120 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The first wiring layer 120 may include an electroless plating layer (e.g., chemical copper plating) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper plating) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the chemical copper plating layer as a seed layer. Copper foil may also be included as needed. The first wiring layer 120 may perform various functions according to the design of the corresponding layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Here, the signal pattern may include various signal patterns other than the ground pattern, the power pattern, etc., such as a data signal pattern, etc. Such patterns may include line patterns, plane patterns, and / or pad patterns, respectively.

[0028] The first via layer 130 may include a plurality of via layers, and each first via layer 130 may include a micro via. The micro via may be a filled via that fills the via hole, or a conformal via formed along the wall surface of the via hole. The micro via may be provided as a stacked via and / or a staggered via. Each first via layer 130 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The via layer may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of a chemical copper plating layer as a seed layer. The first via layer 130 may perform various functions according to the design of the corresponding layer. For example, a ground via, a power via, a signal via, etc. may be included. Here, the signal via may include various signal vias other than a ground via, a power via, etc., for example, a via for transmitting a data signal, etc.

[0029] Each first wiring layer 120 and each first via layer 130 may be formed integrally with each other, but the present disclosure is not limited thereto. The first wiring layer 120 and / or the first via layer 130 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, and a subtractive process, but the present disclosure is not limited thereto, and any method capable of forming a circuit in a printed circuit board may be used without limitation.

[0030] The first wiring layer 120 is disposed on the first insulating layer 110 or in the first insulating layer 110 may mean that the first wiring layer 120 may be disposed on the first insulating layer 110 or in the first insulating layer 110, or the first wiring layer 120 may have a coreless plate structure in which the first wiring layer 120 is buried in the first insulating layer 110. Specifically, referring to Figure 3A and Figure 3B , the lowermost first wiring layer 120 may be buried in the first insulating layer 110 .

[0031] exist Figure 3A and Figure 3B , it is shown that the first insulating layer 110 includes four layers, and the substrate portion 100 includes a first wiring layer 120 and a first via layer 130 of a corresponding number of layers, but the present disclosure is not limited thereto, and the number of the first insulating layer 110, the first wiring layer 120, and the first via layer 130 may vary according to their design. Specifically, the first insulating layer 110 may also include a core insulating layer containing a core, the first wiring layer 120 may include a copper foil, and the first via layer 130 may also include a through-hole that passes through the core insulating layer. Therefore, the first insulating layer 110, the first wiring layer 120, and the first via layer 130 of the printed circuit board according to the example include components that can be used by technicians in the field of printed circuit board technology.

[0032] The cavity may pass through at least a portion of the first insulating layer 110. The cavity may correspond to a location where the connection structure 200 is installed. Passing through at least a portion of the first insulating layer 110 may mean passing through any continuous first insulating layer 110 among the plurality of first insulating layers 110, or passing through only a portion of any first insulating layer 110, but the present disclosure is not limited thereto, and may mean passing through any continuous first insulating layer 110 while passing through a portion of any other first insulating layer 110. Although not described in detail, Figure 3A and Figure 3B As shown in FIG. 1 , when the cavity passes through only a portion of any first insulating layer 110 , the upper surface of the first insulating layer 110 may have a step.

[0033] Any known cavity forming process may be used without limitation. For example, a mechanical drilling process such as laser processing or a sandblasting process may be used, but the present disclosure is not limited thereto. In this case, a portion of the first wiring layer 120 disposed on the first insulating layer 110 may be used as a barrier layer, and the barrier layer may be disposed on the upper surface of the first insulating layer 110 and then may be removed by etching or the like after the cavity processing. When forming the barrier layer, the barrier layer may be formed simultaneously with the first wiring layer 120. The wall surface of the cavity passing through at least a portion of the first insulating layer 110 may be configured as a side surface of the first insulating layer 110, and the bottom surface of the cavity may be configured as an upper surface of the first insulating layer 110. Although not described in detail in detail, the present disclosure may be described in detail in detail. Figure 3A and Figure 3B , but the bottom surface of the cavity may include a barrier layer.

[0034] The printed circuit board according to the example may include the connection structure 200. Referring to the detailed description later FIG. 6A to FIG. 8B , the connection structure 200 disposed in the cavity may include a wiring portion 201 and a capacitor portion 202 .

[0035] The wiring portion 201 of the connection structure 200 may include a second insulating layer 210 , a second wiring layer 220 disposed on or in the second insulating layer 210 , and a second via layer 230 passing through at least a portion of the second insulating layer 210 to connect the second wiring layers 220 to each other.

[0036] The capacitor portion 202 of the connection structure 200 may include a plurality of first dielectric layers 240 and a first metal layer 251 and a second metal layer 252 disposed on or in the plurality of first dielectric layers 240. The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 or may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The capacitor portion 202 may also include a first connection via 281 and a second connection via 282. The first connection via 281 may pass through at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261 to each other. The second connection vias 282 may pass through at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262 to each other. The second connection vias 282 may connect the second wiring layer 220 and the second metal plate 262 to each other through the first connection pads 271.

[0037] The wiring portion 201 of the connection structure 200 may have a wiring density higher than that of the substrate portion 100. The higher wiring density may be based on a relative concept, and may mean, for example, that the average spacing of the wiring included in the second wiring layer 220 may be smaller than the average spacing of the wiring included in the first wiring layer 120. The spacing may be measured by photographing a cut section of the printed circuit board using a scanning microscope, and the average spacing may be the average value of the spacing between the wirings measured at any five points. In addition, the average interlayer insulation distance between the second wiring layers 220 may be smaller than the average interlayer insulation distance between the plurality of first wiring layers 120. The interlayer insulation distance may also be measured by photographing a cut section of the printed circuit board using a scanning microscope, and the average interlayer insulation distance may be the average value of the insulation distance between adjacent wiring layers measured at any five points. That is, the wiring included in the second wiring layer 220 may be a high-density fine wiring having a line / space (L / S) smaller than that of the wiring included in the first wiring layer 120. As a non-limiting example, the line / space of the wiring included in the second wiring layer 220 may be about 2 / 2 μm, but the present disclosure is not limited thereto. Since the wiring portion 201 of the connection structure 200 has a higher density than the density of the wiring of the substrate portion 100, it may be effective when interconnecting electronic components such as semiconductor chips. That is, it may be effective for die-to-die interconnection.

[0038] In this regard, the thickness of the second insulating layer 210 may be less than the thickness of the first insulating layer 110, and the thickness of the second wiring layer 220 may be less than the thickness of the first wiring layer 120. The thickness of the insulating layer may be based on a concept including approximation, and may represent a vertical distance between an upper surface and a lower surface of the insulating layer. The thickness of the second insulating layer 210 being less than the thickness of the first insulating layer 110 may represent that the thickness of one of the plurality of second insulating layers 210 is less than the thickness of one of the plurality of first insulating layers 110, but the present disclosure is not limited thereto. The thickness of the first insulating layer 110 and the thickness of the second insulating layer 210 may be measured by photographing a cut section of the printed circuit board using a scanning microscope, and may be an average value of the values ​​of the thickness of the insulating layer measured at any five points. The thickness of the wiring layer may be interpreted in the same sense as the thickness of the insulating layer.

[0039] Specific details regarding other components of the connection structure will be described below.

[0040] The printed circuit board according to an example may further include an adhesive layer 300 .

[0041] The connection structure 200 may be disposed in the cavity of the substrate part 100, and the connection structure 200 may be attached to the bottom surface of the cavity through the adhesive layer 300. The adhesive layer 300 may be disposed to cover the lower surface of the connection structure 200. As the adhesive layer 300, an adhesive film such as a general die attach film (DAF) may be used, but the present disclosure is not limited thereto, and any member capable of attaching a component such as an electronic component or a connection structure to a printed circuit board (such as a known adhesive tape, etc.) may be used without limitation.

[0042] Reference Figure 3B , a printed circuit board according to an example may include a first semiconductor chip 401 disposed on a portion of a substrate portion 100 and a portion of a connection structure 200 and a second semiconductor chip 402 disposed on a portion of the substrate portion 100 and a portion of the connection structure 200, and may include a connection member 500 connecting the first semiconductor chip 401 and the second semiconductor chip 402 to the substrate portion 100 and the connection structure 200, respectively. The first semiconductor chip 401 may be disposed to be electrically connected to a portion of the substrate portion 100 and a portion of the connection structure 200, and the second semiconductor chip 402 may be disposed to be electrically connected to a portion of the substrate portion 100 and a portion of the connection structure 200 to be electrically connected to the first semiconductor chip 401 through the connection structure 200.

[0043] The first semiconductor chip 401 and the second semiconductor chip 402 may respectively include an integrated circuit (IC) die, in which hundreds to millions of devices are integrated into a single chip. In this case, the IC may be a controller chip, such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, or an application-specific IC (ASIC), but the present disclosure is not limited thereto, and may also be a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory or a high-bandwidth memory (HBM), or a power management IC (PMIC). For example, the first semiconductor chip 401 may include a controller chip such as a GPU, and the second semiconductor chip 402 may include a memory chip such as an HBM. Optionally, the first semiconductor chip 401 and the second semiconductor chip 402 may be controller chips divided by die segmentation, and the divided controller chips have different cores.

[0044] The first semiconductor chip 401 and the second semiconductor chip 402 may be formed based on active wafers, respectively. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as substrates included in each body. Various circuits may be formed in the body. Connecting pads may be formed on each body, and the connecting pads may include conductive materials such as aluminum (Al) or copper (Cu). The first semiconductor chip 401 and the second semiconductor chip 402 may be bare dies. In this case, metal bumps may be provided on the connecting pads. The first semiconductor chip 401 and the second semiconductor chip 402 may be packaged dies. In this case, a redistribution layer may be additionally formed on the connecting pads, and metal bumps may be provided on the redistribution layer.

[0045] The first semiconductor chip 401 and the second semiconductor chip 402 may be connected to the substrate portion 100 and the connection structure 200 of the printed circuit board through a connecting member 500. The connecting member 500 may be formed of a low melting point metal, for example, solder (such as tin (Sn)-aluminum (Al)-copper (Cu)), but the present disclosure is not limited thereto. The connecting member 500 may be formed as a multi-layer or a single layer. When formed as a multi-layer, the connecting member 500 may include copper pillars and solder. When formed as a single layer, the connecting member 500 may include tin-silver solder or copper, but the present disclosure is not limited thereto. In addition, any component that serves as an intermediary for electrically connecting a semiconductor chip or an electronic component to the substrate portion 100 or the connection structure 200 may be used without limitation. Figure 3B In FIG. 2 , two semiconductor chips are shown to be mounted, but the present disclosure is not limited thereto. A greater number of semiconductor chips may be mounted, and a greater number of semiconductor chips may also be electrically connected to each other through the connection structure 200 .

[0046] The printed circuit board according to the example is not limited to Figure 3A and Figure 3B The components shown in the figure may also include common components of a printed circuit board. That is, the printed circuit board may also include components that can be used by those skilled in the art.

[0047] Figure 4 is a schematic cross-sectional view showing a printed circuit board according to another example.

[0048] Reference Figure 4 , the connection structure 200 of the printed circuit board according to another example may be disposed on the substrate part 100. That is, the connection structure 200 may be disposed on the first insulating layer 110 of the substrate part 100, and the first insulating layer 110 may not include a cavity.

[0049] Among components other than the connection structure 200 , the same components as those of the printed circuit board according to the example may be applied to the printed circuit board according to another example, and thus repeated descriptions thereof will be omitted.

[0050] Figure 5 is a schematic cross-sectional view showing a printed circuit board according to another example.

[0051] Reference Figure 5 According to another example, the substrate portion 100 of the printed circuit board may include a core insulating layer 111, and the connection structure 200 may be installed in a cavity formed in the core insulating layer 111. The core insulating layer 111 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler such as silica, or a resin impregnated with a core material such as glass fiber (or glass cloth or glass fabric) and an inorganic filler, such as a copper clad laminate (CCL), etc., but the present disclosure is not limited thereto. The core insulating layer 111 may be thicker than each of the first insulating layers 110, but the present disclosure is not limited thereto. In this case, on the lower surface of the cavity formed in the core insulating layer 111, a portion of the first wiring layer 120 may be used as a barrier layer, but the present disclosure is not limited thereto.

[0052] The same components as those of the printed circuit board according to the example are applicable to the printed circuit board according to another example, except for the arrangement of the core insulating layer 111 of the substrate part 100 and the connection structure 200 , and thus repeated descriptions thereof will be omitted.

[0053] Fig. 6A is a schematic cross-sectional view illustrating a connection structure of a printed circuit board according to an example. Figure 6B is a schematic perspective view showing a capacitor portion of a connection structure of a printed circuit board according to an example.

[0054] Reference Fig. 6A , the connection structure 200 may include a wiring portion 201 and a capacitor portion 202 .

[0055] The wiring portion 201 of the connection structure 200 may include a second insulating layer 210 , a second wiring layer 220 disposed on or in the second insulating layer 210 , and a second via layer 230 passing through at least a portion of the second insulating layer 210 to connect the second wiring layers 220 to each other.

[0056] The second insulating layer 210 may include a plurality of insulating layers, and each second insulating layer 210 may include an insulating material. The insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (glass cloth and / or glass fabric) and these resins. The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the second insulating layer 210 may be PPG, RCC, etc., but the present disclosure is not limited thereto, and may be ABF, PID, FR-4, BT, etc. However, the present disclosure is not limited thereto. Other polymer materials having excellent rigidity may be used as needed. The second insulating layer 210 may include an insulating material formed of an organic material. That is, the connection structure 200 may be an organic bridge. Therefore, even when the connection structure 200 is disposed on the upper side of the substrate portion 100, reliability problems due to thermal expansion coefficient (CTE) mismatch rarely occur, which is different from the case where the connection structure 200 is a silicon bridge. In addition, when the connection structure 200 includes an organic insulating material, the difficulty and cost of the process for molding can be reduced. In order to form a fine circuit, a photosensitive dielectric (PID) may be used as an organic insulating material, but the present disclosure is not limited thereto.

[0057] The second wiring layer 220 may include a plurality of wiring layers, and each second wiring layer 220 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second wiring layer 220 may include an electroless plating layer (e.g., chemical copper plating) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper plating) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the chemical copper plating layer as a seed layer. A copper foil may also be included as needed. The second wiring layer 220 may perform various functions according to the design of the corresponding layer. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. Here, the signal pattern may include various signal patterns other than the ground pattern, the power pattern, etc., such as a data signal pattern, etc. Such patterns may include line patterns, plane patterns, and / or pad patterns, respectively. The uppermost second wiring layer 220 in the second wiring layer 220 may be exposed from the second insulating layer 210, and a surface treatment layer may also be included on the exposed surface.

[0058] The second via layer 230 may include a plurality of via layers, and each second via layer 230 may include a micro via. The micro via may be a filled via that fills the via hole, or a conformal via formed along the wall surface of the via hole. The micro via may be provided as a stacked via and / or a staggered via. Each second via layer 230 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The second via layer 230 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (or an electrolytic copper plating layer) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of a chemical copper plating layer as a seed layer. The second via layer 230 may perform various functions according to the design of the corresponding layer. For example, a ground via, a power via, a signal via, etc. may be included. Here, the signal via may include various signal vias other than a ground via, a power via, etc., for example, a via for transmitting a data signal, etc.

[0059] Each second wiring layer 220 and each second via layer 230 may be formed integrally with each other, but the present disclosure is not limited thereto. The second wiring layer 220 and / or the second via layer 230 may be formed using one of SAP, MSAP, TT, and a subtractive process, but the present disclosure is not limited thereto, and any method capable of forming a circuit in a printed circuit board or a connection structure may be used without limitation.

[0060] exist Fig. 6A , the second wiring layer 220 is shown as being disposed on the second insulating layer 210, but the present disclosure is not limited thereto, and the second wiring layer 220 may be disposed in the second insulating layer 210 to be buried in the second insulating layer 210. In this case, although Fig. 6A Although not shown in the figure, the wiring portion 201 of the connection structure 200 may have a coreless type wiring portion 201 .

[0061] The capacitor portion 202 of the connection structure 200 may include a plurality of first dielectric layers 240 and a first metal layer 251 and a second metal layer 252 disposed on or in the plurality of first dielectric layers 240. The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262. The capacitor portion 202 may also include a first connection via 281 and a second connection via 282. The first connection via 281 may pass through at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261 to each other. The second connection via 282 may pass through at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262 to each other. The second connection via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other through the first connection pad 271. Each of an area of ​​the first metal plate 261 and an area of ​​the second metal plate 262 may be greater than an area of ​​the first connection pad 271.

[0062] The first dielectric layer 240 may include a dielectric material formed of an organic material. The dielectric material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (glass cloth and / or glass fabric) and these resins. The dielectric material may be a photosensitive material and / or a non-photosensitive material. For example, the dielectric material of the first dielectric layer 240 may be PPG, RCC, etc., but may be ABF, PID, FR-4, BT, etc. However, the present disclosure is not limited thereto. Other polymer materials with excellent dielectric properties may be used as needed. In order to realize a fine circuit, realize a fine process, and form a thin first dielectric layer 240, a photosensitive dielectric (PID) (i.e., a photosensitive resin) may be used as an organic insulating material, but the present disclosure is not limited thereto. Any material that can be used as an electrode between the first metal layer 251 and the second metal layer 252 to serve as a dielectric may be used without limitation.

[0063] The first metal layer 251 and the second metal layer 252 may include metal materials, respectively. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second wiring layer 220 may include an electroless plating layer (e.g., chemical copper plating) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper plating) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the chemical copper plating layer as a seed layer. Copper foil may also be included as needed. The first metal layer 251 and the second metal layer 252 may be formed using one of SAP, MSAP, TT, and a subtractive process, but the present disclosure is not limited thereto. Any method of forming a metal layer may be used. The method of forming the metal layer is not limited, such as printing a conductive paste including a metal material on a raw sheet.

[0064] The first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 can be used as the inner electrodes of the capacitor part 202, respectively. That is, the first metal layer 251 and the second metal layer 252 can be charged to have opposite polarities, and thus can have capacitance. The first metal plate 261 and the second metal plate 262 can be arranged to correspond to each other, so that the first metal plate 261 and the second metal plate 262 can form a pair of metal plates. The first metal plate 261 and the second metal plate 262 can be arranged to be opposite to each other, and the first dielectric layer 240 is between the first metal plate 261 and the second metal plate 262. Since the first metal plate 261 and the second metal plate 262 are arranged as described above, each metal plate can be charged with electric charge and used as a capacitor. The first metal plate 261 and the second metal plate 262 can have a rectangular plate shape, that is, can be in the form of a plate, but the present disclosure is not necessarily limited thereto, and can have a polygonal plate shape or a circular plate shape. In addition, the metal plate can have a groove portion, or can be a shape in which a plurality of patterns are densely gathered. Therefore, the first metal plate 261 and the second metal plate 262 may have various designs, such as various shapes, according to the capacitance required by the design of the printed circuit board and the design of the connection structure 200 .

[0065] The first connection pad 271 may be provided to be spaced apart from the first metal plate 261, and may be provided at the same level as that of the first metal plate 261. The first connection pad 271 may be used as an intermediate member provided to connect the second wiring layer 220 and the second metal layer 252 to each other. That is, the first connection pad 271 may be used as an intermediate member so that the second connection via 282 provided at the lower portion of the first metal plate 261 for electrically connecting to the second metal plate 262 does not pass through the plurality of first dielectric layers 240 and the second insulating layer 210 at one time. That is, when the first connection pad 271 is provided at the first metal layer, it may be more conducive to the operation of forming a through hole for forming the second connection via 282. In this case, the first connection pad 271 may be spaced apart from the first metal plate 261, so the first metal plate 261 and the second metal plate 262 may not be directly connected to each other. When the second connection via that passes through the plurality of first dielectric layers 240 and the second insulating layer 210 at one time may be formed, the first connection pad 271 may not be provided.

[0066] The first connection via 281 may pass through at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261 to each other, and the second connection via 282 may pass through at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262 to each other. The second connection via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other through the first connection pad 271. The first connection via 281 and the second connection via 282 may include metal materials, respectively. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second wiring layer 220 may include an electroless plating layer (e.g., chemical copper plating) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper plating) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be formed as a seed layer instead of a chemical copper plating layer. Copper foil may also be included as needed. The first connection via 281 and the second connection via 282 may be formed using one of SAP, MSAP, TT and a subtractive process, but the present disclosure is not limited thereto. Any method for forming vias may be used without limitation. The second connection via 282 and the first connection pad 271 may be formed integrally with each other, but the present disclosure is not limited thereto. According to an example, vias such as the first connection via 281 and the second connection via 282 disposed in the connection structure 200 and connected to the second wiring layer 220 may be tapered in a direction from the second insulating layer 210 to the first dielectric layer 240, and vias disposed in the substrate portion 100 and connected to the first wiring layer 120 may be tapered in the same direction as the tapered direction of the vias disposed in the connection structure 200.

[0067] The distance d1 between the first metal layer 251 and the second metal layer 252 may be smaller than the distance d2 between the first metal layer 251 and the second wiring layer 220. The distance d1 between the first metal layer 251 and the second metal layer 252 may be understood to represent the distance between the lower surface of the first metal layer 251 and the upper surface of the second metal layer 252. More specifically, the distance d1 may represent the insulation distance between the first metal layer 251 and the second metal layer 252. The distance d1 between the first metal layer 251 and the second metal layer 252 may be measured by photographing a cut section of a printed circuit board or a connection structure using a scanning microscope, and may be the average value of the values ​​of the distance d1 between the first metal layer 251 and the second metal layer 252 measured at any five points. The distance d2 between the first metal layer 251 and the second wiring layer 220 may also be interpreted in the same manner. The distance d2 between the first metal layer 251 and the second wiring layer 220 may represent the distance between the first metal layer 251 and the second wiring layer 220 closest to the first metal layer 251.

[0068] As the distance d1 between the first metal layer 251 and the second metal layer 252 gradually decreases, the first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 may be used as electrodes of a capacitor. The distance d1 between the first metal layer 251 and the second metal layer 252 may be 1 μm or less. When the distance d1 between the first metal layer 251 and the second metal layer 252 is further reduced, the distance d1 may also be set to have a value of 0.33 μm or less. However, the distance d1 between the first metal layer 251 and the second metal layer 252 may be freely designed according to the capacitance required by the capacitor portion 202 of the connection structure 200. In order to ensure capacitance, the first metal layer 251 and the second metal layer 252 may need to be set close to each other so that the distance d1 between the first metal layer 251 and the second metal layer 252 has a value less than a predetermined value. However, the distance d1 between the first metal layer 251 and the second metal layer 252 may also have a value greater than 0. This may be because when the first metal layer 251 and the second metal layer 252 contact each other, a short circuit occurs, and thus capacitance cannot be obtained.

[0069] In a similar sense that the distance d1 between the first metal layer 251 and the second metal layer 252 is smaller than the distance d2 between the first metal layer 251 and the second wiring layer 220, the thickness t1 of the first dielectric layer 240 may be formed to be smaller than the thickness t2 of the second insulating layer 210. The thickness of the first dielectric layer 240 may be formed to be smaller than the thickness of the second insulating layer 210 may mean that the thickness of one of the plurality of first dielectric layers 240 may be formed to be smaller than the thickness of one of the plurality of second insulating layers 210. The thickness of the first dielectric layer 240 may be based on a concept including approximation, and may mean a vertical distance between the upper surface and the lower surface of the first dielectric layer 240. The thickness of the first dielectric layer 240 may be measured by photographing a cut cross section of the printed circuit board using a scanning microscope, and may be an average value of values ​​of the thickness of the dielectric layer measured at any five points. The thickness of the second insulating layer 210 may be interpreted in the same sense as the thickness of the first dielectric layer 240 , and may be understood in the same sense as described above with respect to the measurement of the thickness of the first insulating layer 110 .

[0070] In order to form the first dielectric layer 240 to be thinner than the second insulating layer 210, the first dielectric layer 240 may be formed by performing spin coating on an insulating material, rather than forming the first dielectric layer 240 by laminating an insulating material to form a film. When the first dielectric layer 240 is formed by performing spin coating, the insulating distance (the distance d1 between the first metal layer 251 and the second metal layer 252) may be formed shorter, and the insulating distance may be easily adjusted. However, the method or means for forming the first dielectric layer 240 is not limited thereto, and any method for forming an insulating material or a dielectric in a printed circuit board may be used without limitation, and any method that easily adjusts the thickness and forms a small thickness may be used without limitation. For example, when the insulating film for the first dielectric layer 240 is formed to have a small thickness, the insulating film may be formed using a lamination method.

[0071] The first dielectric layer 240 may include an organic material of the same type as that of the second insulating layer 210. As described above, the first dielectric layer 240 may include a photosensitive dielectric (PID) (i.e., a photosensitive resin) to form a thin dielectric layer, and the second insulating layer 210 may include a photosensitive insulating material to implement a fine circuit. However, the materials of the first dielectric layer 240 and the second insulating layer 210 are not limited thereto, and may include various types of organic materials as described above. Even when the first dielectric layer 240 includes an organic material, the capacitor portion 202 may have capacitance by disposing the first metal layer 251 and the second metal layer 252 close to each other.

[0072] Reference Figure 6B, the capacitor part 202 may include a pair of metal layers facing each other. The first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 may face each other, and capacitance may be generated in an effective area where the first metal plate 261 and the second metal plate 262 face each other. Therefore, the first metal plate 261 and the second metal plate 262 may be designed to increase the effective area. Figure 6B , it is shown that protrusions are formed at both ends of the metal plate, and the protrusions are connected to the first connection via 281 or the second connection via 282. However, Figure 6B Examples of various designs of the first metal plate 261 and the second metal plate 262 are shown. As necessary, the shape of the protrusion of the metal plate may be changed, and the position of the first connection pad 271 may also be changed.

[0073] Reference Figure 6B , the first metal plate 261 and the second metal plate 262 may include a first hole 291 and a second hole 292 therein, respectively. The first hole 291 and the second hole 292 may correspond to the exhaust hole in the printed circuit board. The first hole 291 and the second hole 292 may be configured for exhaust, and may be used as a path for exhausting and removing unnecessary moisture or gas generated in the operation of manufacturing the connection structure 200 and the operation of manufacturing the printed circuit board. In a general printed circuit board or other connection structure, exhaust holes are set at different positions of each layer to efficiently exhaust. However, in the connection structure 200 of the printed circuit board according to the example, the position of the first hole 291 formed in the first metal plate 261 may correspond to the position of the second hole 292 formed in the second metal plate 262. That is, since the positions of the first hole 291 and the second hole 292 are formed to correspond to each other, it is easier to adjust the effective area of ​​the area where the first metal plate 261 and the second metal plate 262 overlap each other. Since it is easy to adjust the effective area between the first metal plate 261 and the second metal plate 262, it is easy to design the capacitor part 202 to have the necessary capacitance. Figure 6B , it is shown that one first hole 291 and one second hole 292 are formed, but the size, number, shape and position of the first hole 291 and the second hole 292 are not limited and may be changed according to the design.

[0074] Despite Fig. 6A and Figure 6B Although not shown in the figure, the connection structure 200 may have a buried pattern structure. For example, the upper surface of the uppermost second wiring layer 220 may be buried in the upper surface of the uppermost second insulating layer 210, and thus may be exposed to the upper surface of the second insulating layer 210. When the connection structure 200 is formed to have such a structure, the wiring can be designed to have a finer pitch. In addition, compared with a silicon bridge, the cost required for manufacturing can be reduced, and the process can be simplified.

[0075] Fig. 7A is a schematic cross-sectional view showing a connection structure according to another example. Figure 7B is a schematic perspective view of a capacitor portion showing a connection structure according to another example.

[0076] Reference Fig. 7A and Figure 7B According to another example, the connection structure may include a plurality of first metal layers 251 and a plurality of second metal layers 252. The first metal layers 251 and the second metal layers 252 may be alternately disposed, and the first dielectric layer 240 is interposed between the first metal layers 251 and the second metal layers 252. That is, the second metal layers may be disposed between the first metal layers 251, and the first metal layers 251 may be disposed between the second metal layers 252.

[0077] The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The first connection via 281 may connect the second wiring layer 220 and the first metal plate 261 to each other, and may also connect the second wiring layer 220 to another first metal plate 261 through the second connection pad 272. The second connection via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other, and may also connect the second wiring layer 220 to another second metal plate 262 through the first connection pad 271. The second connection pad 272 may be provided to be spaced apart from the second metal plate 262, and may have the same characteristics as those of the first connection pad 271, and thus repeated description will be omitted.

[0078] exist Fig. 7A and Figure 7B , it is shown that the first metal layer 251 and the second metal layer 252 include two metal layers respectively, so a total of four metal layers are included. However, the number of metal layers is not limited thereto, and a larger number of metal layers may be provided. That is, the number of metal layers may be designed in various ways according to the capacitance of the capacitor unit 202.

[0079] Among components except the first metal layer 251 and the second metal layer 252 , the components of the connection structure according to an example may be applied to a connection structure according to another example, and thus repeated descriptions related thereto will be omitted.

[0080] Fig. 8A is a schematic cross-sectional view showing a connection structure according to another example. Figure 8B is a schematic perspective view of a capacitor portion showing a connection structure according to another example.

[0081] Reference Fig. 8A and Figure 8BIn a connection structure according to another example, a first metal layer 251 and a second metal layer 252 may include a plurality of first metal plates 261 and a plurality of second metal plates 262, respectively. In this case, each first metal plate 261 may be arranged to be spaced apart from each other, and each second metal plate 262 may be arranged to be spaced apart from each other. That is, in a connection structure 200 according to another example, the capacitor unit 202 may be arranged in parallel. Therefore, the capacitor unit 202 may be designed to be a necessary capacitance in various ways.

[0082] exist Fig. 8A and Figure 8B , it is shown that the first metal layer 251 and the second metal layer 252 include two metal plates respectively. However, the number of metal plates is not limited thereto, and more metal plates may be arranged in parallel. The first metal layer 251 and the second metal layer 252 are respectively shown as being configured as one metal layer. However, the first metal layer 251 and the second metal layer 252 may be configured as a plurality of first metal layers 251 and a plurality of second metal layers 252, respectively. That is, the number of metal plates and the number of metal layers may be designed in various ways according to the capacitance of the capacitor unit 202.

[0083] Among components other than the first metal plate 261 and the second metal plate 262 , the components of the connection structure according to the example may be applied to the connection structure according to another example, and thus repeated descriptions thereof will be omitted.

[0084] In the present disclosure, the cross-sectional shape may refer to the cross-sectional shape of an object when the object is cut vertically or the cross-sectional shape of an object when the object is observed from a side perspective. In addition, the shape on a plane may be the plane shape of an object when the object is cut horizontally or the plane shape of an object when the object is observed from a top-down perspective or an upward-looking perspective.

[0085] In the present disclosure, for the sake of convenience, the upper side, upper part, upper surface, etc. are used to refer to the direction toward the surface on which the electronic components can be mounted based on the cross section of the drawings, and the lower side, lower part, lower surface, etc. are used to refer to the opposite direction. However, the above directions are defined for the convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions.

[0086] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" by means of an adhesive layer or the like. The term "electrical connection" may include both a case where components are "physically connected" and a case where components are "not physically connected." In addition, the terms "first," "second," and the like may be used to distinguish a component from another component, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the claims.

[0087] As used herein, the term "exemplary embodiment" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same exemplary embodiment. In addition, in one or more exemplary embodiments, the particular characteristics or features may be combined in any suitable manner. For example, unless the context described in a particular exemplary embodiment is described as being contrary to or inconsistent with the context in other exemplary embodiments, the context described in a particular exemplary embodiment may be used in other exemplary embodiments even if not described in other exemplary embodiments.

[0088] The terms used herein are intended to describe only specific example embodiments, and the present disclosure is not limited thereto. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0089] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A substrate portion including a first insulating layer and a first wiring layer disposed on or in the first insulating layer; as well as a connection structure, arranged on or in the substrate portion, and comprising a plurality of first dielectric layers, a first metal layer and a second metal layer respectively arranged on or in the plurality of first dielectric layers, a second insulating layer arranged on the plurality of first dielectric layers, and a second wiring layer arranged on or in the second insulating layer, wherein each of the plurality of first dielectric layers comprises an organic material, and A distance between the first metal layer and the second metal layer is smaller than a distance between the first metal layer and the second wiring layer.

2. The printed circuit board according to claim 1, wherein: The first metal layer includes a first metal plate and a first connection pad spaced apart from the first metal plate, and The second metal layer includes a second metal plate.

3. The printed circuit board according to claim 2, wherein: The connection structure also includes a first connection via and a second connection via, wherein the first connection via passes through at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate to each other, and the second connection via passes through at least a portion of the multiple first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate to each other.

4. The printed circuit board according to claim 3, wherein: The second connection via connects the second wiring layer and the second metal plate to each other through the first connection pad.

5. The printed circuit board according to claim 2, wherein: The first metal layer and the second metal layer include a plurality of first metal layers and a plurality of second metal layers respectively. One of the plurality of second metal layers further includes a second connection pad spaced apart from the second metal plate, and The plurality of first metal layers and the plurality of second metal layers are alternately arranged, and the first dielectric layer is interposed therebetween.

6. The printed circuit board according to claim 5, wherein: The connection structure further includes a first connection via and a second connection via, the first connection via passing through at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate to each other, and the second connection via passing through at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate to each other, The first connection via connects the second wiring layer and the first metal plate to each other through the second connection pad, and The second connection via connects the second wiring layer and the second metal plate to each other through the first connection pad.

7. The printed circuit board according to claim 2, wherein: Each of an area of ​​the first metal plate and an area of ​​the second metal plate is larger than an area of ​​the first connection pad.

8. The printed circuit board according to claim 1, wherein: The first metal layer includes a plurality of first metal plates spaced apart from each other and a plurality of first connection pads spaced apart from the plurality of first metal plates, and The second metal layer includes a plurality of second metal plates spaced apart from each other.

9. The printed circuit board according to claim 8, wherein: The connection structure further includes a first connection via and a second connection via, the first connection via passing through at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate to each other, the second connection via passing through at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate to each other, and The second connection vias connect the second wiring layer and the plurality of second metal plates to each other through the plurality of first connection pads, respectively.

10. The printed circuit board according to claim 1, wherein The thickness of the first dielectric layer is smaller than the thickness of the second insulating layer.

11. The printed circuit board according to claim 1, wherein: The first dielectric layer includes a photosensitive resin.

12. The printed circuit board according to claim 1, wherein: The first dielectric layer includes an organic material of the same type as that of the second insulating layer.

13. The printed circuit board according to claim 1, further comprising: The adhesive layer is disposed between the substrate portion and the connection structure.

14. The printed circuit board according to claim 1, wherein: The wiring density of the first wiring layer is smaller than the wiring density of the second wiring layer.

15. The printed circuit board according to claim 2, wherein: The first metal plate includes a first hole disposed therein, and The second metal plate includes a second hole provided therein corresponding to the first hole.

16. The printed circuit board according to claim 1, further comprising: a first electronic component connected to a portion of the substrate portion and a portion of the connection structure; as well as A second electronic component is connected to another portion of the substrate portion and another portion of the connection structure.

17. The printed circuit board according to claim 1, wherein: The second insulating layer is in contact with the first metal layer and the second wiring layer.

18. The printed circuit board according to claim 1, wherein The vias provided in the connection structure and connected to the second wiring layer are tapered in a direction from the second insulating layer to the plurality of first dielectric layers, and A via provided in the substrate portion and connected to the first wiring layer tapers in the same direction as a taper direction of a via provided in the connection structure.

19. A printed circuit board comprising: A substrate portion including a first insulating layer and a first wiring layer disposed on or in the first insulating layer; as well as a connection structure disposed on or in the substrate portion, the connection structure comprising a capacitor portion and a wiring portion, the capacitor portion comprising a dielectric layer and a first metal layer disposed on or in the dielectric layer, the wiring portion comprising a second insulating layer and a second wiring layer disposed on or in the second insulating layer, Wherein, the first metal layer comprises a pair of metal plates facing each other, and The dielectric layer includes an organic material.

20. The printed circuit board according to claim 19, wherein The wiring density of the first wiring layer is smaller than the wiring density of the second wiring layer.

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