Current regulation diode and preparation method and application circuit thereof

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a current regulation diode and a preparation method and application circuit thereof, and the current regulation diode comprises an N + substrate which comprises a first surface and a second surface; the first N-epitaxial layer is arranged on the first surface of the N + substrate; the second N-epitaxial layer is arranged on the surface of the first N-epitaxial layer, grooves are etched in the two sides of the second N-epitaxial layer, a channel is formed between the two grooves, two Pwell regions are formed after P-type doping agents are injected into the two grooves respectively, and an N + region is formed at the top of the channel in a doping mode; the first metal layer is arranged on the surface of the second N-epitaxial layer and is used for being connected with a cathode; the second metal layer is arranged on the second surface of the N + substrate and is used for being connected with the anode; wherein the doping concentration of the second N-epitaxial layer is higher than that of the first N-epitaxial layer. The current regulation diode has good volt-ampere characteristics and a wide regulation range.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, for example, to a current regulating diode and a preparation method and application circuit thereof. Background Art

[0002] At present, LED (Light Emitting Diode) has been widely used in the fields of automobile, industry and general lighting due to its advantages of high light efficiency, small size, long life and low power consumption. Traditional LED driving current regulator is implemented by integrated circuit, which is usually complex in structure, expensive and noisy. In recent years, lateral current regulating diode (CRD) based on lateral JFET (Junction Field-Effect Transistor) structure has been applied to LED lighting. This diode is simple and economical. However, since a long drift region is required to withstand the high applied voltage, a large area is required.

[0003] In the related art, compared with the lateral JFET structure, the vertical JFET structure can save area.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] Due to channel length modulation, the saturation characteristics of the vertical JFET structure are poor. When the channel length is short and the channel doping is light, the channel length modulation effect is more serious. Therefore, the current regulating diode based on the vertical JFET structure does not have good volt-ampere characteristics and a suitable regulation range.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a current regulating diode and a preparation method and an application circuit thereof, so that the current regulating diode based on the vertical JFET structure also has good volt-ampere characteristics and a wider adjustment range.

[0009] In some embodiments, a current regulating diode includes: an N+ substrate, including a first surface and a second surface; a first N-epitaxial layer, arranged on the first surface of the N+ substrate; a second N-epitaxial layer, arranged on the surface of the first N-epitaxial layer, grooves are etched on both sides of the second N-epitaxial layer, a channel is formed between the two grooves, two Pwell regions are formed by respectively injecting P-type dopants into the two grooves, and an N+ region is also doped at the top of the channel; a first metal layer, arranged on the surface of the second N-epitaxial layer, for connecting to a cathode; a second metal layer, arranged on the second surface of the N+ substrate, for connecting to an anode; wherein the doping concentration of the second N-epitaxial layer is higher than the doping concentration of the first N-epitaxial layer.

[0010] Optionally, the thickness of the first N-epitaxial layer is in the range of [10 μm, 15 μm], and the doping concentration is in the range of [1.0×10 15 cm -3 , 1.4×10 15 cm -3 ].

[0011] Optionally, the thickness of the second N-epitaxial layer is in the range of [5 μm, 10 μm], and the doping concentration is in the range of [4.8×10 15 cm -3 , 5.2×10 15 cm -3 ].

[0012] Optionally, the depth of the trench is in the range of [3 μm, 4 μm].

[0013] Optionally, a Pwell junction depth range of the Pwell region is [4.5 μm, 5 μm].

[0014] Optionally, the channel has a length in the range of [4 μm, 6 μm] and a width in the range of [2 μm, 4 μm].

[0015] In some embodiments, a method for preparing a current regulating diode includes: continuously forming a first N-epitaxial layer and a second N-epitaxial layer on a first surface of an N+ substrate; etching two grooves on both sides of the second N-epitaxial layer; respectively injecting P-type dopants into the two grooves to form two Pwell regions, and the two Pwell regions are independent of each other; injecting N-type dopants into the top of the channel formed between the two grooves to form an N+ region; performing metal contact and metal deposition on the surface of the second N-epitaxial layer to form a first metal layer; performing metal contact and metal deposition on the second surface of the N+ substrate to form a second metal layer.

[0016] Optionally, the open window range of trench etching is [4 μm, 6 μm].

[0017] Optionally, the open window range for P-type dopant implantation is [3 μm, 5 μm].

[0018] In some embodiments, the application circuit of the current regulating diode includes: multiple current regulating diodes as described above connected in parallel, the anodes of all current regulating diodes are connected to the positive electrode of the power supply; multiple LED lamps connected in series, the first LED lamp is connected to the cathodes of all current regulating diodes, and the last LED lamp is connected to the negative electrode of the power supply.

[0019] The current regulating diode and its preparation method and application circuit provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The current regulating diode provided by the embodiment of the present disclosure includes an N+ substrate, a first N-epitaxial layer, a second N-epitaxial layer, a first metal layer and a second metal layer, and the doping concentration of the second N-epitaxial layer is higher than the doping concentration of the first N-epitaxial layer. The first N-epitaxial layer has a relatively low doping concentration in order to withstand a high reverse bias and thus achieve a high breakdown voltage, and the second N-epitaxial layer has a relatively high doping concentration in order to reduce the channel length modulation effect and thus improve the saturation characteristics of the diode. A long channel is achieved by injecting P-type dopants on both sides of the second N-epitaxial layer after trench etching, further improving the volt-ampere characteristics. Compared with conventional diodes that require a long drift region to withstand a high applied voltage, the embodiment of the present disclosure saves area through a vertical JFET structure and trench technology. In addition, through simulation studies, the current regulating diode provided by the embodiment of the present disclosure exhibits good volt-ampere characteristics and a wide adjustment range.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic diagram of a cross-sectional structure of a current regulating diode provided by an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a structural cross-section of another current regulating diode provided by an embodiment of the present disclosure;

[0025] Figure 3 is a volt-ampere characteristic diagram of a current regulating diode provided by an embodiment of the present disclosure;

[0026] Figure 4(a) is a volt-ampere characteristic diagram of a current regulating diode provided by an embodiment of the present disclosure under different second N-epitaxial layer doping concentration conditions;

[0027] Figure 4 (b) is a graph of the volt-ampere characteristics of a current regulating diode provided by an embodiment of the present disclosure under different trench depth conditions analyzed and simulated;

[0028] Figure 5 is a schematic diagram of a method for preparing a current regulating diode provided by an embodiment of the present disclosure;

[0029] Figure 6 (a) is a schematic diagram of etching a groove in a method for preparing a current regulating diode provided in an embodiment of the present disclosure;

[0030] Figure 6 (b) is a schematic diagram of injecting a P-type dopant in a method for preparing a current regulating diode provided in an embodiment of the present disclosure;

[0031] Figure 6 (c) is a schematic diagram of forming a metal layer in a method for preparing a current regulating diode provided by an embodiment of the present disclosure;

[0032] Figure 7 It is a schematic diagram of an application circuit of a current regulating diode provided in an embodiment of the present disclosure.

[0033] Reference numerals: 10, N+ substrate; 20, first N-epitaxial layer; 30, second N-epitaxial layer; 31, Pwell region; 32, N+ region; 40, first metal layer; 50, second metal layer. DETAILED DESCRIPTION

[0034] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0035] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] Unless otherwise stated, the term "plurality" means two or more.

[0037] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0038] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0039] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0040] Combination Figure 1 As shown, the embodiment of the present disclosure provides a current regulating diode, including: an N+ substrate 10 , a first N-epitaxial layer 20 , a second N-epitaxial layer 30 , a first metal layer 40 and a second metal layer 50 .

[0041] The N+ substrate 10 includes a first surface and a second surface. The first N-epitaxial layer 20 is arranged on the first surface of the N+ substrate 10. The second N-epitaxial layer 30 is arranged on the surface of the first N-epitaxial layer 20, and grooves are etched on both sides of the second N-epitaxial layer 30. A channel is formed between the two grooves. Two Pwell regions 31 are formed by injecting P-type dopants into the two grooves respectively. At the top of the channel, an N+ region 32 is also doped. The first metal layer 40 is arranged on the surface of the second N-epitaxial layer 30 for connecting to the cathode. The second metal layer 50 is arranged on the second surface of the N+ substrate 10 for connecting to the anode. Among them, the doping concentration of the second N-epitaxial layer 30 is higher than the doping concentration of the first N-epitaxial layer 20.

[0042] In the embodiment of the present disclosure, a double epitaxial layer is introduced on the N+ substrate 10. The first N-epitaxial layer 20 has a relatively low doping concentration in order to withstand a high reverse bias and thus achieve a high breakdown voltage. The second N-epitaxial layer 30 has a relatively high doping concentration in order to reduce the channel length modulation effect and thus improve the saturation characteristics of the diode. A long channel is achieved by implanting P-type dopants on both sides of the second N-epitaxial layer 30 after trench etching, further improving the volt-ampere characteristics. Compared with conventional diodes that require a long drift region to withstand a high applied voltage, the embodiment of the present disclosure saves area through a vertical JFET structure and trench technology. In addition, through simulation studies, the current regulating diode provided by the embodiment of the present disclosure exhibits good volt-ampere characteristics and a wide adjustment range.

[0043] The N+ substrate 10 is a highly doped N-type silicon substrate used in semiconductor devices, which is achieved by doping N ions in the silicon substrate, such as phosphorus, arsenic or antimony. The N+ substrate 10 has a high doping concentration in the range of 1017 cm -3 to 10 19 cm -3 or higher to provide good conductivity and low resistivity. In the disclosed embodiment, the N+ substrate 10 in the current regulating diode structure serves as the basis of the device, and together with other epitaxial layers and structures, achieves high breakdown voltage, good volt-ampere characteristics and a wide adjustment range. The specific doping concentration of the N+ substrate 10 can also be determined to a more accurate doping concentration according to the design requirements and performance targets of the device.

[0044] In the first N-epitaxial layer 20 and the second N-epitaxial layer 30, the N-epitaxial layer refers to a layer of semiconductor material with N-type conductive properties formed on the N+ substrate 10 by epitaxial growth technology. This layer of material is doped with N-type dopants, such as pentavalent elements such as phosphorus, arsenic or antimony, to provide additional electrons and increase the conductivity of the material. However, relative to the N+ substrate 10, the doping concentration of the N-epitaxial layer is relatively low. In the embodiment of the present disclosure, the first N-epitaxial layer 20 and the second N-epitaxial layer 30 in the current regulating diode structure work together to achieve the reduction of the channel length modulation effect and improve the saturation characteristics and voltage resistance of the device.

[0045] Optionally, combined Figure 2 As shown, the thickness T of the first N-epitaxial layer 20 is n1 The range is [10μm, 15μm], and the doping concentration range is [1.0×10 15 cm -3 , 1.4×10 15 cm -3 ].

[0046] In this embodiment, the main function of the first N-epitaxial layer 20 is to withstand high reverse bias (VB), as the drift region of the device, allowing current to be blocked at high voltage. The thicker first N-epitaxial layer 20 can ensure that the first N-epitaxial layer 20 can withstand a higher reverse bias, thereby increasing the breakdown voltage of the device. Moderate doping concentration helps to balance conductivity and reverse leakage current, ensuring the stability of the device under high voltage. The thickness and doping concentration of the first N-epitaxial layer 20 directly affect the breakdown voltage, conductivity, thermal stability and reverse leakage current of the device. The design conditions in this embodiment can ensure that the device works stably at high voltage while having lower on-resistance and good thermal performance.

[0047] Optionally, combined Figure 2 As shown, the thickness T of the second N-epitaxial layer 30 is n2 The range is [5μm, 10μm], and the doping concentration range is [4.8×10 15 cm -3 , 5.2×10 15cm -3 ].

[0048] In this embodiment, the main function of the second N-epitaxial layer 30 is to reduce the channel length modulation effect, thereby improving the saturation characteristics of the diode. Compared with the first N-epitaxial layer 20, the doping concentration of the second N-epitaxial layer 30 is relatively high, which helps to improve the conductivity of the channel region and reduce the channel resistance. The thickness of the second N-epitaxial layer 30 is usually thinner than the first N-epitaxial layer 20, because the second N-epitaxial layer 30 does not need to withstand high reverse bias, and the specific value of the thickness depends on the design requirements and manufacturing process. The design of the second N-epitaxial layer 30 can improve the volt-ampere characteristics and adjustment range of the device. By optimizing the doping concentration and thickness, the current adjustment ability and stability of the device can be improved. The second N-epitaxial layer 30 works together with the first N-epitaxial layer 20 to achieve high breakdown voltage and good current adjustment characteristics. The first N-epitaxial layer 20 is mainly responsible for withstanding high reverse bias, while the second N-epitaxial layer 30 is responsible for improving the saturation characteristics of the device.

[0049] Optionally, combined Figure 2 As shown, the depth of the groove T t The range is [3μm, 4μm].

[0050] Grooves are etched on both sides of the second N-epitaxial layer 30 by photolithography and etching processes. These grooves will serve as the basis for subsequent processes to form conductive channels. After the trench etching is completed, a P-type dopant, such as boron, is injected into the trench by an ion implantation process. Boron atoms will occupy the interstitial positions of the silicon lattice to form a Pwell region 31. The Pwell region 31 plays a role in controlling the flow of current in the device. In the middle of the two Pwell regions 31, an N-type channel is formed due to the higher doping concentration of the second N-epitaxial layer 30. This channel is the main conductive path of the device. The PN junction between the Pwell region 31 and the N-epitaxial layer can withstand a higher reverse bias, thereby improving the voltage resistance of the device. The design of the trench and the Pwell region 31 helps to reduce the channel length modulation effect and improve the saturation characteristics of the device.

[0051] Optionally, combined Figure 2 As shown, the Pwell junction depth T p The range is [4.5μm, 5μm].

[0052] In this embodiment, the Pwell junction depth refers to the depth of the PN junction formed by the P-type doped region (Pwell region) and the N-type epitaxial layer (second N-epitaxial layer). The Pwell junction depth of [4.5μm, 5μm] can provide sufficient voltage resistance. The deeper PN junction helps to block the current at high voltage and reduce reverse leakage current. Within this depth range, the Pwell region 31 can effectively control the current in the channel, and the interaction between the Pwell region 31 and the N-type channel can form good current control.

[0053] Optionally, combined Figure 2 As shown, the length of the channel L ch The range is [4μm, 6μm], and the width W ch The range is [2μm, 4μm].

[0054] In this embodiment, by adjusting the length and width of the channel, the on-resistance, switching speed and thermal management can be balanced to meet the requirements of a specific application. This design flexibility helps improve the overall performance of the device, including improving the current regulation capability, reducing the dynamic resistance in the saturation region and improving thermal stability. At the top of the channel, there is also a highly doped N+ region 32 formed by injecting N-type dopants. The N+ region 32 can be used as a contact layer in the current regulating diode to improve the conductivity and performance of the device. The N+ region 32 also has a high doping concentration in the range of 10 16 cm -3 to 10 18 cm -3 or higher, therefore, the N+ region 32 has a very high electron concentration, which can significantly reduce the contact resistance between the metal contact and the semiconductor. The N+ region 32 increases the number of electrons in the channel region, thereby increasing the current capacity of the device. Therefore, the N+ region 32 at the top of the channel helps to improve the current regulation capability and stability of the device. By optimizing the doping concentration and position of the N+ region 32, the overall performance of the device can be further improved, including improving the current regulation capability, reducing the dynamic resistance in the saturation region, and improving thermal stability.

[0055] Combination Figure 3 As shown in the figure, it is a volt-ampere characteristic diagram of the current regulating diode provided by the embodiment of the present disclosure. It can be found that the current regulating diode has a low knee voltage (Vk) and a wide range of stable regulating current (IS). The volt-ampere characteristic of the current regulating diode is similar to that of JFET and can be divided into two parts: the linear region and the saturation region. Figure 2As shown, in order to obtain a more saturated characteristic, the current regulating diode is designed so that the two Pwell regions contact each other at point A located in the second N-epitaxial layer 30, so that the current regulating diode can be pinched off at point A. Therefore, considering the channel length modulation after truncation, the IV characteristic can be expressed by the following formula for the I in the linear region and the saturation region: A To analyze:

[0056]

[0057] Where 0≤V A ≤V sat is the linear region, V A >V sat is the saturation region; Z is the device width; q is the electron charge; ε s is the dielectric constant of silicon; μ is the electron mobility; N2 is the doping concentration of the second N-epitaxial layer 30; λ is the channel length modulation factor; V sat is the anode voltage when the pin is disconnected, given by the formula Mb≈0.65V; α describes the proportional share of the voltage at the cutoff point A; L ch is the length of the channel, W ch is the width of the channel. Among the parameters of the analytical model provided in the embodiment of the present disclosure, λ=α=0.5, L ch =T t +1.5μm, T t is the groove depth.

[0058] Saturation region dynamic resistance R d It can be derived from the following formula:

[0059]

[0060] Therefore, the channel length L ch and width W ch In the case of a larger value, a larger R d , thus improving the saturation characteristics.

[0061] Combination Figure 4 As shown, Figure 4 (a) is the volt-ampere characteristics analyzed and simulated under different N2 conditions. Figure 4 (b) For different T t The volt-ampere characteristics of the analytical and simulated conditions, where the dotted line is the analytical data (analytic) and the solid line is the simulation data (simulation). It can be found that the analytical data and the simulation data are in good agreement. With the increase of N2 and T tThe current regulating diode will have better volt-ampere characteristics. In the simulation process, in order to obtain a qualified reverse bias voltage VB, the doping concentration N1 of the first N-epitaxial layer 20 is selected to be 1.2×10 15 cm -3 , the thickness T of the first N-epitaxial layer 20 n1 is 14μm. Figure 4 In the process of (a), by adjusting W ch The current when the cutoff occurs is set to be the same, and the fixed T t =3.5μm, the saturation characteristics are improved with the increase of N2. In addition, for N2=N1=1.2×10 15 cm -3 , it can be regarded as that there is only one epitaxial layer on the N+ substrate 10. It can be found that in the single epitaxial layer structure, a sufficiently good saturation characteristic cannot be achieved. Figure 4 As shown in (b), when N2 is fixed at 5×10 15 cm -3 In the case of T t The increase of L ch It will also increase accordingly, that is, the channel length increases, the saturation current will decrease, and the saturation characteristics will be improved at the same time.

[0062] Combination Figure 5 As shown, the embodiment of the present disclosure provides a method for preparing a current regulating diode, comprising:

[0063] S401 , continuously forming a first N-epitaxial layer and a second N-epitaxial layer on a first surface of an N+ substrate.

[0064] S402, etching two trenches on both sides of the second N-epitaxial layer respectively.

[0065] S403 , implanting P-type dopants into the two trenches respectively to form two Pwell regions, and the two Pwell regions are independent of each other.

[0066] S404 , implanting N-type dopants into the top of the channel formed between the two trenches to form an N+ region.

[0067] S405 , performing metal contact and metal deposition on the surface of the second N-epitaxial layer to form a first metal layer.

[0068] S406 , performing metal contact and metal deposition on the second surface of the N+ substrate to form a second metal layer.

[0069] Combination Figure 6 As shown, in the embodiment of the present disclosure, the N+ substrate (n+Substrate) is the basis of the semiconductor device, made of highly doped N-type silicon material, and serves as the bottom of the device. Figure 6 As shown in (a), the first low-doped first N-epitaxial layer (n-epitaxy1) grown on the N+ substrate is used to withstand high reverse bias. The second relatively highly doped second N-epitaxial layer (n-Epitaxy2) grown on the first N-epitaxial layer is used to reduce the channel length modulation effect and improve the saturation characteristics. Next, two trenches are etched on both sides of the second N-epitaxial layer by etching technology. In a specific embodiment, the depth of the two trenches can be 3.5μm, W t It is an open window for trench etching, which will be used to form the structure of trench diode. Figure 6 As shown in (b), by covering with photoresist, P-type dopants such as boron are implanted into the two trenches respectively. p It is an open window for the injection of P-type dopants, forming two independent Pwell regions, thus forming a PN junction. At the top of the channel formed between the two trenches, N-type dopants are injected to form an N+ region. Figure 6 As shown in (c), metal contact and metal deposition are performed on the surface of the second N- epitaxial layer and the second surface of the N+ substrate, respectively, to form a first metal layer (metal) and a second metal layer, so as to connect various regions of the semiconductor device to external circuits to achieve electrical connection and thermal management.

[0070] Optionally, the open window W of the trench etch t The range is [4μm, 6μm].

[0071] In this embodiment, the size of the open window of the trench etching directly affects the width of the channel. After etching the trench with a depth range of [3μm, 4μm], P-type dopants are injected to form the Pwell region, and the width of the trench open window determines the width of the channel. The wider the trench open window, the wider the channel formed, and the device can carry a larger current. A wider trench open window can realize more current channels, thereby reducing the on-resistance of the device.

[0072] Optionally, the open window W for P-type dopant implantation p The range is [3μm, 5μm].

[0073] In this embodiment, in order to inject P-type dopants into the trench, the open window for P-type dopant injection should be smaller than the width of the trench. The injected P-type dopant will form a PN junction, the depth of which will be affected by the injection energy and dose. The width of the open window will affect the lateral diffusion of the PN junction, thereby affecting the junction depth. A wider P-type dopant injection window may increase the lateral depletion region of the PN junction, thereby improving the withstand voltage capability of the device. The width of the P-type dopant injection window will affect the electric field distribution in the channel region, thereby affecting the current control capability.

[0074] Combination Figure 7 As shown, an embodiment of the present disclosure provides an application circuit of a current regulating diode, including: a plurality of current regulating diodes (CRDs) as described above connected in parallel, the anodes of all the current regulating diodes being connected to the anode of a power supply Vin; a plurality of LED lamps (LEDs) connected in series, the first LED lamp being connected to the cathodes of all the current regulating diodes, and the last LED lamp being connected to the cathode of the power supply Vin.

[0075] In the actual application of current regulating diodes, the current regulating diodes are connected in series with LED lamps. The current regulating diodes can be used to accurately control the current flowing through the LED lamps to prevent damage to the LED lamps due to excessive current. When a single current regulating diode cannot provide sufficient current capacity, the total current capacity can be increased by connecting two or more current regulating diodes in parallel. Current regulating diodes connected in parallel share the same voltage but can carry a larger current. In a parallel configuration, ideally, each current regulating diode should share the current equally, so the electrical characteristics of each current regulating diode (such as resistance and voltage drop) need to be as consistent as possible. Accurately controlling the current through the current regulating diode can ensure the performance, efficiency and reliability of the LED lighting system, help improve the luminous efficacy and life of the LED lamp, and reduce energy consumption.

[0076] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0077] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0078] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0079] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A current regulating diode, characterized in that: include: An N+ substrate including a first surface and a second surface; A first N-epitaxial layer is disposed on a first surface of the N+ substrate; A second N-epitaxial layer is disposed on the surface of the first N-epitaxial layer. Grooves are etched on both sides of the second N-epitaxial layer. A channel is formed between the two grooves. Two Pwell regions are formed by respectively injecting P-type dopants into the two grooves. An N+ region is also doped at the top of the channel. A first metal layer is disposed on the surface of the second N-epitaxial layer and is used to connect to the cathode; A second metal layer is disposed on the second surface of the N+ substrate and is used to connect to the anode; The doping concentration of the second N-epitaxial layer is higher than the doping concentration of the first N-epitaxial layer.

2. The current regulating diode according to claim 1, characterized in that: The thickness of the first N-epitaxial layer ranges from [10 μm, 15 μm] and the doping concentration ranges from [1.0×10 15 cm -3 , 1.4×10 15 cm -3 ].

3. The current regulating diode according to claim 1, characterized in that: The thickness of the second N-epitaxial layer ranges from [5 μm, 10 μm] and the doping concentration ranges from [4.8×10 15 cm -3 , 5.2×10 15 cm -3 ].

4. The current regulating diode according to claim 1, characterized in that: The depth of the grooves ranged from [3 μm, 4 μm].

5. The current regulating diode according to claim 1, characterized in that: The Pwell junction depth range of the Pwell region is [4.5μm, 5μm].

6. The current regulating diode according to claim 1, characterized in that: The channel length ranges from [4 μm, 6 μm] and the width ranges from [2 μm, 4 μm].

7. A method for preparing a current regulating diode, characterized in that: include: successively forming a first N-epitaxial layer and a second N-epitaxial layer on a first surface of the N+ substrate; Etching two trenches on both sides of the second N-epitaxial layer; P-type dopants are respectively implanted into the two trenches to form two Pwell regions, and the two Pwell regions are independent of each other; At the top of the channel formed between the two trenches, N-type dopants are implanted to form an N+ region; Performing metal contact and metal deposition on the surface of the second N-epitaxial layer to form a first metal layer; Metal contact and metal deposition are performed on the second surface of the N+ substrate to form a second metal layer.

8. The preparation method according to claim 7, characterized in that: The open window range for trench etching is [4μm, 6μm].

9. The preparation method according to claim 7, characterized in that: The open window range for P-type dopant implantation is [3μm, 5μm].

10. An application circuit of a current regulating diode, characterized in that: include: A plurality of current regulating diodes as claimed in any one of claims 1 to 6 connected in parallel, wherein the anodes of all the current regulating diodes are connected to the anode of the power supply; For multiple LED lamps connected in series, the first LED lamp is connected to the cathodes of all current regulating diodes, and the last LED lamp is connected to the negative electrode of the power supply.

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