Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the following steps: providing a substrate; performing ion implantation in the transverse diffusion region of the substrate to form a P-type well region and an N-type drift region; etching the P-type well region and the core region of the substrate to form a fin-shaped structure and a planar block-shaped structure; the planar block structure is formed on the basis of the N-type drift region which is not etched in the transverse diffusion region; forming a first transistor based on the first fin-shaped structure; reversing the wafer and removing the substrate; forming a second transistor based on the second fin-shaped structure; performing first fin cutting processing on the first fin-shaped structure to form a first fin cutting groove, and / or performing second fin cutting processing on the second fin-shaped structure to form a second fin cutting groove; the etching depth of the first fin cutting groove is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure; and the etching depth of the second fin cutting groove is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As the performance of fin field-effect transistors (FinFETs) approaches its limit, a laterally-diffused metal-oxide semiconductor (LDMOS) process based on a new structure is to be developed, which will help further shrink the size of transistors. Transistor stacking is considered to be a very promising way to shrink transistors. At present, as a part of the supporting circuit module, how to achieve process compatibility with stacked transistors for FinFET LDMOS is still a problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to achieve process compatibility between a lateral diffusion device and a stacked transistor.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure includes a lateral diffusion device and a core device, wherein the core device includes a first transistor and a second transistor stacked along a first direction; the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; the above method includes: providing a substrate; the substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are adjacently arranged in a second direction; the second direction is perpendicular to the first direction; ion implantation is performed in the lateral diffusion region to form a P-type well region and an N-type drift region; the P-type well region and the core region are etched to form a fin-like structure and a planar block structure; the fin structure includes a first fin structure and a second fin structure stacked along the first direction; the planar block structure is based on the lateral diffusion region. An etched N-type drift region is formed; a planar block structure includes a first planar block structure and a second planar block structure stacked along a first direction; based on the first fin structure, a first transistor is formed; flipping the wafer and removing the substrate; based on the second fin structure, a second transistor is formed; wherein the above method also includes: performing a first fin cut process on the first fin structure to form a first fin cut groove, and / or performing a second fin cut process on the second fin structure to form a second fin cut groove; the first fin cut groove is perpendicular to the extension direction of the first fin structure, and the etching depth of the first fin cut groove is half of the height of the fin structure or equal to the height of the fin structure; the second fin cut groove is perpendicular to the extension direction of the second fin structure, and the etching depth of the second fin cut groove is half of the height of the fin structure or equal to the height of the fin structure.

[0005] In some possible embodiments, the P-type well region and the core region are etched to form a fin-like structure and a planar block structure, including: coating a photoresist on the N-type drift region to form a photoresist layer; under the masking action of the photoresist layer, etching the P-type well region and the core region to form a fin-like structure located in the P-type well region and the core region, and a planar block structure located in the N-type drift region.

[0006] In some possible embodiments, before forming the first transistor based on the first fin structure, the method further includes: depositing oxide on the substrate and the fin structure to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the fin structure; and removing a first portion of the first shallow trench isolation structure to expose the first fin structure.

[0007] In some possible embodiments, when a first fin-like structure is subjected to a first fin-cut process; oxide is deposited on a substrate and the fin-like structure to form a first shallow trench isolation structure, including: depositing oxide on the substrate and the fin-like structure, and depositing oxide in the first fin-cut trench to form a first shallow trench isolation structure; the first shallow trench isolation structure fills the first fin-cut trench.

[0008] In some possible embodiments, when a second fin-cut process is performed on the second fin structure; before forming a second transistor based on the second fin structure, the above method also includes: depositing oxide in the second fin-cut trench to form a second shallow trench isolation structure; the second shallow trench isolation structure fills the second fin-cut trench; removing the second portion of the first shallow trench isolation structure and the third portion of the second shallow trench isolation structure to expose the second fin structure; the height of the second portion is the same as the height of the third portion.

[0009] In some possible embodiments, when the lateral diffusion device and the first transistor are arranged side by side, while forming the first transistor based on the first fin structure, the above method also includes: forming the lateral diffusion device based on the first fin structure and the first planar block structure located in the lateral diffusion region; while forming the second transistor based on the second fin structure, the above method also includes: forming an isolation device based on the second fin structure and the second planar block structure located in the lateral diffusion region; the isolation device and the lateral diffusion device are stacked along the first direction.

[0010] In some possible embodiments, when the lateral diffusion device and the second transistor are arranged side by side, while forming the first transistor based on the first fin structure, the above method also includes: forming an isolation device based on the first fin structure and the first planar block structure located in the lateral diffusion region; while forming the second transistor based on the second fin structure, the method also includes: forming a lateral diffusion device based on the second fin structure and the second planar block structure located in the lateral diffusion region; the isolation device and the lateral diffusion device are stacked along the first direction.

[0011] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method described in the first aspect above, and the semiconductor structure includes: a core device; the core device includes a first transistor and a second transistor stacked along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor; an isolation device; the isolation device and the lateral diffusion device are stacked in the first direction, and the isolation device is arranged side by side with the second transistor or side by side with the first transistor; the lateral diffusion device includes a fin structure and a planar block structure, the fin structure is formed by etching a P-type well region in the lateral diffusion device, and the planar block structure is an N-type drift region in the lateral diffusion device.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0014] In the present application, by forming a fin structure and a planar block structure in the lateral diffusion region, the formed lateral diffusion device can withstand higher voltages while being fully compatible with the process of preparing stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0015] Furthermore, since the lateral diffusion device can be arranged side by side with the first transistor or the second transistor, and the etching depth of the first fin cutting process and the second fin cutting process can be selected as full depth or half depth according to actual needs, the layout of the internal devices of the semiconductor structure is more flexible.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0019] Figure 2 A design layout of a semiconductor structure in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a semiconductor structure in an embodiment of the present application;

[0021] FIG. 4A to FIG. 4D A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of a fourth preparation process of a semiconductor structure in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of a fifth preparation process of a semiconductor structure in an embodiment of the present application;

[0024] The above pictures:

[0025] 10. semiconductor structure; 11. first transistor; 111. first spacer; 112. first source-drain structure; 113. first interlayer dielectric layer; 114. first gate dielectric layer; 115. first gate structure; 116. first source-drain metal; 12. lateral diffusion device; 121. second spacer; 122. second source-drain structure; 123. second interlayer dielectric layer; 124. second gate dielectric layer; 125. second gate structure; 126. second source-drain metal; 13. second transistor; 131. third spacer; 132. third source-drain structure; 133. third interlayer dielectric layer; 134. third gate dielectric layer; 135. third gate structure; pole structure; 136, third source and drain metal; 14, isolation device; 143, fourth interlayer dielectric layer; 15, first insulating layer; 16, carrier wafer; 21, substrate; 22, fin structure; 221, first fin structure; 222, second fin structure; 231, first fin cut groove; 232, second fin cut groove; 24, photoresist layer; 25, planar block structure; 261, first gate oxide layer; 262, second gate oxide layer; 271, first contact layer; 272, second contact layer; 311, first dummy gate structure; 312, second dummy gate structure; 313, third dummy gate structure; 40, shallow trench isolation layer; 41, first shallow trench isolation structure. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0027] In some embodiments, the LDMOS structure seeks to obtain a higher breakdown voltage and a lower on-resistance. In order to increase the breakdown voltage, there is a drift region between the source region and the drain region. The impurity concentration of the drift region is low, presenting a high resistance state, and thus being able to withstand a higher voltage. The LDMOS drift region uses STI (shallow trench isolation) / field oxygen technology, which makes the current path blocked and longer, thereby further improving the voltage resistance. In order to further shrink the size, LDMOS based on FinFET (finfield-effect transistor) technology has received widespread attention. Taking nLDMOS as an example, a P-well and an N-type drift region are injected into a p-type substrate, where the source region is located in the P-well, the drain region and STI are located in the N-type drift region, and the gate covers the channel region, part of the N-type drift region and part of the STI region.

[0028] As FinFET performance approaches its limit, LDMOS processes based on new structures are to be developed, which will help further shrink the size of transistors. Transistor stacking is considered to be a very promising way to shrink transistors, for example, complementary field effect transistor (CFETs) technology. However, there are also some problems, such as: (1) thermal stability of the bottom layer device when making the upper layer device; (2) performance of the top layer device under low thermal budget; (3) metal interconnection between transistors between layers.

[0029] At present, as a part of the supporting circuit module, how to achieve process compatibility with stacked transistors for FinFET LDMOS is still a problem that needs to be solved urgently.

[0030] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to achieve process compatibility between a lateral diffusion device and a stacked transistor.

[0031] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0032] In some possible embodiments, the semiconductor structure includes: a core device; the core device includes a first transistor and a second transistor stacked along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor; an isolation device; the isolation device and the lateral diffusion device are stacked in the first direction, and the isolation device is arranged side by side with the second transistor or side by side with the first transistor; wherein the lateral diffusion device includes a fin structure and a planar block structure, the fin structure in the lateral diffusion device is formed by etching a P-type well region in the lateral diffusion device, and the planar block structure is an N-type drift region in the lateral diffusion device.

[0033] It is understandable that the semiconductor structure mentioned in the embodiment of the present application includes a lateral diffusion device (i.e., LDMOS) and a core device. The lateral diffusion device and the core device can be arranged adjacent to each other, or can be arranged at intervals, or can be arranged in other forms, and the embodiment of the present application does not specifically limit this. It should be noted that the semiconductor structure may include multiple lateral diffusion devices and multiple core devices. The lateral diffusion devices and core devices in the same semiconductor structure are prepared based on the same substrate (i.e., wafer). For ease of explanation, the embodiment of the present application takes the semiconductor structure including a lateral diffusion device and a core device as an example for explanation.

[0034] In some embodiments, the lateral diffusion device in the semiconductor structure is only arranged on the front side or the back side of the semiconductor structure, that is, the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor. The isolation device and the lateral diffusion device are stacked in the first direction, when the lateral diffusion device is arranged side by side with the first transistor, the isolation device is arranged side by side with the second transistor; when the lateral diffusion device is arranged side by side with the second transistor, the isolation device is arranged side by side with the first transistor.

[0035] In the embodiment of the present application, the core device includes a first transistor and a second transistor which are stacked, and the first transistor and the second transistor are arranged back to back to form a stacked transistor. The first transistor and the second transistor can be transistors of the same type, such as fin field effect transistors.

[0036] Figure 2 It is a semiconductor structure composed of fin field effect transistors and lateral diffusion devices. Figure 2 As shown, the semiconductor structure includes a lateral diffusion device and a core device, the core device includes a first transistor and a second transistor stacked along a first direction; the semiconductor structure also includes a lateral diffusion device, the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor. Figure 2 The semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0037] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0038] S101, providing a substrate; wherein the substrate comprises a lateral diffusion region and a core region; the lateral diffusion region and the core region are adjacently arranged in a second direction; and the second direction is perpendicular to the first direction.

[0039] It can be understood that the substrate includes a lateral diffusion region for forming lateral diffusion devices and isolation devices and a core region for forming core devices. The lateral diffusion region and the core region can be arranged adjacent to each other.

[0040] In some embodiments, the semiconductor structure is a stacked transistor, and accordingly, the lateral diffusion device and the isolation device are stacked; the first transistor and the second transistor in the core device are stacked.

[0041] In some embodiments, the substrate may be a Si substrate made of a silicon (Si) material, or other forms of substrates may be selected according to actual needs, such as a silicon on insulator (SOI) substrate.

[0042] S102, performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region.

[0043] It can be understood that, using the mask process, ion implantation can be performed twice in the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region, respectively. In the process of ion implantation, the P-type well region can be formed first, and then the N-type drift region; or the N-type drift region can be formed first, and then the P-type well region. It should be noted that the injection method of the N-type drift region can be selected as the whole piece injection or partial injection according to actual needs, and the embodiment of the present application does not specifically limit this; a PN junction in the horizontal direction (i.e., the second direction mentioned above) can be formed between the N-type drift region and the P-type well region.

[0044] S103, etching the P-type well region and the core region to form a fin-like structure and a planar block structure; wherein the fin-like structure includes a first fin structure and a second fin structure stacked along a first direction; the planar block structure is formed based on the unetched N-type drift region in the lateral diffusion region; the planar block structure includes a first planar block structure and a second planar block structure stacked along the first direction.

[0045] It can be understood that by etching the substrate, a fin-like structure (fin) and a planar block structure can be formed. The fin-like structure in the core area is used to form a core device; the lateral diffusion area includes a fin-like structure and a planar block structure, and the fin-like structure in the lateral diffusion area is formed by etching the P-type well area, and the unetched N-type drift area forms a planar block structure. In the lateral diffusion area, along the extension direction of the fin-like structure, the lateral diffusion area can be divided into a fin-type diffusion area and a planar diffusion area, wherein the fin-type diffusion area is the area where the fin-like structure in the lateral diffusion area is located, and the planar diffusion area is the area where the planar block structure in the lateral diffusion area is located. The fin-like structure and the planar block structure in the lateral diffusion area are used to form lateral diffusion devices and isolation devices. The fin-like structure can be divided into two parts, the upper part is the first fin-like structure, and the lower part is the second fin structure. Among them, the first fin structure located in the lateral diffusion region is used to form a lateral diffusion device or an isolation device, and the second fin structure located in the lateral diffusion region is used to form an isolation device or a lateral diffusion device; the first fin structure located in the core region is used to form a first transistor, and the second fin structure located in the core region is used to form a second transistor.

[0046] In some embodiments, a larger etching depth may be used when etching the substrate. The height of the fin structure should be greater than a preset height threshold, for example, the height of the fin structure may be greater than 100 nm. It should be noted that the height of the fin structure may be designed according to actual needs, and the embodiments of the present application do not specifically limit this.

[0047] S104 , forming a first transistor based on the first fin structure.

[0048] It can be understood that after the first fin structure is formed, the first transistor can be formed according to a standard process for manufacturing transistors.

[0049] S105, flipping the wafer and removing the substrate.

[0050] It can be understood that after the first transistor is formed, in order to prepare the second transistor, the first transistor can be flipped and the substrate can be removed so that the second fin structure is placed upward.

[0051] In some possible implementations, before the above S105, the method for preparing the above semiconductor structure may further include: depositing an insulating material on the upper surface of the first transistor to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0052] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0053] S106 , forming a second transistor based on the second fin structure.

[0054] It can be understood that after flipping the wafer, the second transistor can be formed according to a standard process for manufacturing transistors.

[0055] In some possible embodiments, the preparation method of the above-mentioned semiconductor structure may further include: performing a first fin cutting process on the first fin-shaped structure to form a first fin cutting groove, and / or performing a second fin cutting process on the second fin-shaped structure to form a second fin cutting groove; the first fin cutting groove is perpendicular to the extension direction of the first fin-shaped structure, and the etching depth of the first fin cutting groove is half of the height of the fin-shaped structure or equal to the height of the fin structure; the second fin cutting groove is perpendicular to the extension direction of the second fin structure, and the etching depth of the second fin cutting groove is half of the height of the fin-shaped structure or equal to the height of the fin structure.

[0056] It is understandable that in the process of preparing the semiconductor structure, the first fin cutting process and / or the second fin cutting process can be selected according to actual needs. For example, the first fin-shaped structure can be subjected to the first fin cutting process, and the second fin-shaped structure can be subjected to the second fin cutting process; the first fin-shaped structure can be subjected to the first fin cutting process only; and the second fin-shaped structure can be subjected to the second fin cutting process only.

[0057] In some embodiments, when the first fin-shaped structure is subjected to the first fin-cutting process, the etching depth of the first fin-cutting process may be half depth, that is, the etching depth is half of the height of the fin-shaped structure; the etching depth of the first fin-cutting process may also be full depth, that is, the etching depth is equal to the height of the fin-shaped structure. The etching depth of the first fin-cutting process may be designed according to actual needs, and the embodiments of the present application do not specifically limit this.

[0058] In some embodiments, when the second fin-shaped structure is subjected to a second fin-cutting process, the etching depth of the second fin-cutting process may be half-width depth, that is, the etching depth is half of the height of the fin-shaped structure; the etching depth of the second fin-cutting process may also be full-width depth, that is, the etching depth is equal to the height of the fin-shaped structure. The etching depth of the second fin-cutting process may be designed according to actual needs, and the embodiments of the present application do not specifically limit this.

[0059] In some possible implementations, the above S103 may include: coating a photoresist on the N-type drift region to form a photoresist layer; under the masking action of the photoresist layer, etching the P-type well region and the core region to form a fin structure located in the P-type well region and the core region, and a planar block structure located in the N-type drift region.

[0060] It is understandable that since the fin-like structure in the lateral diffusion region is formed by etching the P-type well region, in order to avoid etching the N-type drift region, a photoresist can be coated on the N-type drift region before etching, and the formed photoresist layer can protect the N-type drift region from being etched. By etching the P-type well region and the core region at the same time, a fin-like structure in the lateral diffusion region and a fin-like structure in the core region can be formed. The N-type drift region that has not been etched forms a planar block structure.

[0061] In some possible embodiments, before the above S104, the method for preparing the above semiconductor structure may include: depositing oxide on the substrate and the fin structure to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the fin structure; and removing a first portion of the first shallow trench isolation structure to expose the first fin structure.

[0062] It can be understood that oxide is deposited on the substrate and the fin structure to form a first shallow trench isolation structure (i.e., STI). The first shallow trench isolation structure wraps the fin structure and covers the substrate. The portion of the first shallow trench isolation structure that wraps the first fin structure (i.e., the first portion) is removed to expose the first fin structure, so as to facilitate the subsequent preparation of the first transistor.

[0063] In some possible embodiments, when a first fin-cut process is performed on a first fin-like structure; the above-mentioned deposition of oxide on the substrate and the fin-like structure to form a first shallow trench isolation structure may include: depositing oxide on the substrate and the fin-like structure, and depositing oxide in the first fin-cut trench to form a first shallow trench isolation structure; the first shallow trench isolation structure fills the first fin-cut trench.

[0064] It can be understood that after forming the first fin-shaped structure and performing the first fin-cutting process on the first fin-shaped structure, a first fin-cutting trench is formed, and in the process of forming the first shallow trench isolation structure, the first fin-cutting trench is simultaneously filled with the above-mentioned oxide.

[0065] In some possible embodiments, when the second fin structure is subjected to a second fin cut process; before the above S106, the method for preparing the above semiconductor structure may further include: depositing oxide in the second fin cut groove to form a second shallow trench isolation structure; the second shallow trench isolation structure fills the second fin cut groove; removing the second portion of the first shallow trench isolation structure and the third portion of the second shallow trench isolation structure to expose the second fin structure; the height of the second portion is the same as the height of the third portion.

[0066] It can be understood that after forming the second fin-cut trench and filling the second fin-cut trench with oxide to form the second shallow trench isolation structure, the second fin-shaped structure is simultaneously wrapped by the second shallow trench isolation structure and the first shallow trench isolation structure. Next, the portion of the second shallow trench isolation structure that wraps the second fin-shaped structure (i.e., the third portion) and the portion of the first shallow trench isolation structure that wraps the second fin-shaped structure (i.e., the second portion) are removed to expose the second fin-shaped structure, so as to facilitate the subsequent preparation of the second transistor.

[0067] In some possible implementations, when the lateral diffusion device and the first transistor are arranged side by side, at the same time as the above S104, the method for preparing the semiconductor structure may further include: forming a lateral diffusion device based on the first fin structure and the first planar block structure located in the lateral diffusion region. At the same time as the above S106, the method for preparing the semiconductor structure may further include: forming an isolation device based on the second fin structure and the second planar block structure located in the lateral diffusion region; and the isolation device and the lateral diffusion device are stacked along the first direction.

[0068] It can be understood that, when the lateral diffusion device and the first transistor are arranged side by side, the lateral diffusion device is prepared while the first transistor is prepared; and the isolation device is prepared while the second transistor is prepared.

[0069] In some possible implementations, when the lateral diffusion device and the second transistor are arranged side by side, at the same time as the above S104, the method for preparing the semiconductor structure may further include: forming an isolation device based on the first fin structure and the first planar block structure located in the lateral diffusion region. At the same time as the above S106, the method for preparing the semiconductor structure may further include: forming a lateral diffusion device based on the second fin structure and the second planar block structure located in the lateral diffusion region; and stacking the isolation device and the lateral diffusion device along the first direction.

[0070] It can be understood that, when the lateral diffusion device and the second transistor are arranged side by side, the isolation device is prepared while the first transistor is prepared; and the lateral diffusion device is prepared while the second transistor is prepared.

[0071] In some embodiments, when the lateral diffusion device is arranged side by side with the first transistor, the above-mentioned steps of forming the first transistor and the lateral diffusion device may include: based on the first fin structure, forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device; etching a portion of the first fin structure to form a first source-drain groove and a second source-drain groove; performing source-drain epitaxial growth in the first source-drain groove and the second source-drain groove to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in the first transistor and a second source-drain metal in the lateral diffusion device on the first source-drain structure and the second source-drain structure; performing post-processing on the first gate structure, the second gate structure, the first source-drain metal, and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0072] It should be noted that the same devices in the first transistor and the lateral diffusion device are formed in the same process, for example, the first dummy gate structure and the second dummy gate structure are formed in the same process, and the first source-drain structure and the second source-drain structure are formed in the same process.

[0073] In one example, after forming a first shallow trench isolation structure, a first portion of the first shallow trench isolation structure is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on the surface of the first fin structure to form a first gate oxide layer, and the first gate oxide layer covers the surface of the first fin structure. Then, a gate groove is opened on the first gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a first pseudo-gate structure in the first transistor and a second pseudo-gate structure in the lateral diffusion device; a dielectric material is deposited on the sidewall of the first pseudo-gate structure to form a first spacer (spcer) in the first transistor, and a dielectric material is deposited on the sidewall of the second pseudo-gate structure to form a second spacer in the lateral diffusion device. A portion of the first fin structure is etched to form a first source-drain groove and a second source-drain groove; source-drain epitaxial growth is performed in the first source-drain groove to form a first source-drain structure in the first transistor, and source-drain epitaxial growth is performed in the second source-drain groove to form a second source-drain structure in the lateral diffusion device. A dielectric material is deposited on the first source-drain structure, the second source-drain structure, and the etched first shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the first interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the first pseudo-gate structure and the second pseudo-gate structure. Next, the first pseudo-gate structure and the second pseudo-gate structure are removed to expose the gate groove, and a metal material is deposited in the gate groove to form a first gate structure in the first transistor and a second gate structure in the lateral diffusion device. An insulating material is deposited on the first interlayer dielectric layer and the second interlayer dielectric layer to form a first contact layer. By photolithography, the first contact layer, the first interlayer dielectric layer and the second interlayer dielectric layer are etched to form a first through hole located on the upper surface of the first source and drain structure and a second through hole located on the upper surface of the second source and drain structure. Metal material is deposited in the first through hole and the second through hole to form a first source and drain metal and a second source and drain metal. Finally, a back-end process is performed on the first contact layer to form a first metal interconnect layer in the first transistor and a second metal interconnect layer in the lateral diffusion device.

[0074] In some embodiments, when the lateral diffusion device is arranged side by side with the first transistor, the above steps of forming the second transistor and the isolation device may include: forming a third pseudo gate structure in the second transistor based on the second fin structure; etching a portion of the second fin structure to form a third source and drain groove; performing source and drain epitaxial growth in the third source and drain groove to form a third source and drain structure in the second transistor; removing the third pseudo gate structure and forming a third gate structure in the second transistor; forming a third source and drain metal in the second transistor on the third source and drain structure; performing post-processing on the third gate structure and the third source and drain metal to form a third metal interconnection layer in the second transistor and a back dielectric layer in the isolation device; and the lateral diffusion device and the isolation device are stacked along the first direction.

[0075] It can be understood that no gate structure, source-drain structure, and source-drain metal are formed in the isolation device.

[0076] In one example, the second part of the first shallow trench isolation structure and the third part of the second shallow trench isolation structure are etched so that the second fin structure is exposed, and the retained (i.e., unetched) first shallow trench isolation structure is used as a shallow trench isolation layer. An oxide of a preset height is deposited on the surface of the second fin structure to form a second gate oxide layer, and the second gate oxide layer covers the surface of the second fin structure. Then, a gate groove is opened on the second gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a third pseudo-gate structure in the second transistor; a dielectric material is deposited on the sidewall of the third pseudo-gate structure to form a third spacer in the second transistor. A portion of the second fin structure is etched to form a third source-drain groove; source-drain epitaxial growth is performed in the third source-drain groove to form a third source-drain structure in the second transistor. A dielectric material is deposited on the third source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the heights of the third interlayer dielectric layer and the fourth interlayer dielectric layer are the same as the height of the third pseudo-gate structure. Next, the third pseudo-gate structure is removed to expose the gate groove, and a metal material is deposited in the gate groove to form a third gate structure in the second transistor. An insulating material is deposited on the third interlayer dielectric layer and the fourth interlayer dielectric layer to form a second contact layer. The second contact layer and the third interlayer dielectric layer are etched by photolithography to form a third through hole located on the upper surface of the third source-drain structure. Metal material is deposited in the third through hole to form a third source-drain metal. Finally, a back-end process is performed on the second contact layer to form a third metal interconnect layer in the second transistor and a back dielectric layer in the isolation device.

[0077] It should be noted that when the lateral diffusion device is arranged side by side with the first transistor, since no gate structure and source-drain structure are formed in the isolation device, only a dielectric layer (i.e., a back dielectric layer) needs to be formed during the back-end process, and there is no need to perform metal interconnection in the back dielectric layer.

[0078] In some embodiments, the metal materials forming the first gate structure, the second gate structure and the third gate structure may include but are not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure, the second gate structure and the third gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0079] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0080] In some embodiments, the oxide forming the first shallow trench isolation structure and the second shallow trench isolation structure may be any one of the following: silicon dioxide (SiO 2 ) or silicon oxycarbide (SiCO), etc.

[0081] In some embodiments, when the lateral diffusion device and the second transistor are arranged side by side, the above steps of forming the first transistor and the isolation device may include: forming a first dummy gate structure in the first transistor based on the first fin structure; etching a portion of the first fin structure to form a first source-drain groove; performing source-drain epitaxial growth in the first source-drain groove to form a first source-drain structure in the first transistor; removing the first dummy gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in the first transistor on the first source-drain structure; performing post-processing on the first gate structure and the first source-drain metal to form a first metal interconnect layer in the first transistor and a front dielectric layer in the isolation device; the isolation device and the lateral diffusion device are stacked along a first direction.

[0082] In one example, a first portion of the first shallow trench isolation structure is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on the surface of the first fin structure to form a first gate oxide layer, and the first gate oxide layer covers the surface of the first fin structure. Then, a gate groove is opened on the first gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a first pseudo-gate structure in the first transistor; a dielectric material is deposited on the sidewall of the first pseudo-gate structure to form a first spacer in the first transistor. A portion of the first fin structure is etched to form a first source-drain groove; and source-drain epitaxial growth is performed in the first source-drain groove to form a first source-drain structure in the first transistor. A dielectric material is deposited on the first source-drain structure and the etched first shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the height of the first interlayer dielectric layer and the fourth interlayer dielectric layer is the same as the height of the first pseudo-gate structure. Then, the first pseudo-gate structure is removed to expose the gate groove, and a metal material is deposited in the gate groove to form a first gate structure in the first transistor. An insulating material is deposited on the first interlayer dielectric layer and the fourth interlayer dielectric layer to form a first contact layer. The first contact layer and the first interlayer dielectric layer are etched by photolithography to form a first through hole located on the upper surface of the first source-drain structure. A metal material is deposited in the first through hole to form a first source-drain metal. Finally, a back-end process is performed on the first contact layer to form a first metal interconnect layer in the first transistor and a front dielectric layer in the isolation device.

[0083] It should be noted that when the lateral diffusion device and the second transistor are arranged side by side, no gate structure and source-drain structure are formed in the isolation device. Therefore, in the process of the back-end process, only a dielectric layer (i.e., a front dielectric layer) needs to be formed, and there is no need to perform metal interconnection in the front dielectric layer.

[0084] In some embodiments, when the lateral diffusion device is arranged side by side with the second transistor, the above steps of forming the second transistor and the lateral diffusion device may include: based on the second fin structure, forming a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device; etching a portion of the second fin structure to form a third source-drain groove and a second source-drain groove; performing source-drain epitaxial growth in the third source-drain groove and the second source-drain groove to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffusion device; removing the third dummy gate structure and the second dummy gate structure, and forming a third gate structure in the second transistor and a second gate structure in the lateral diffusion device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffusion device on the third source-drain structure and the second source-drain structure; performing post-processing on the third gate structure, the second gate structure, the third source-drain metal and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0085] It can be understood that when the lateral diffusion device and the second transistor are arranged side by side, the same devices in the second transistor and the lateral diffusion device are formed in the same process, for example, the third pseudo-gate structure and the second pseudo-gate structure are formed in the same process, and the third source-drain structure and the second source-drain structure are formed in the same process.

[0086] In one example, the second part of the first shallow trench isolation structure and the third part of the second shallow trench isolation structure are etched so that the second fin structure is exposed and a shallow trench isolation layer is formed. An oxide of a preset height is deposited on the surface of the second fin structure to form a second gate oxide layer, and the second gate oxide layer covers the surface of the second fin structure. Then, a gate groove is opened on the second gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a third pseudo-gate structure in the second transistor and a second pseudo-gate structure in the lateral diffusion device; a dielectric material is deposited on the sidewall of the third pseudo-gate structure to form a third spacer in the second transistor, and a dielectric material is deposited on the sidewall of the second pseudo-gate structure to form a second spacer in the lateral diffusion device. A portion of the second fin structure is etched to form a third source-drain groove and a second source-drain groove; a source-drain epitaxial growth is performed in the third source-drain groove to form a third source-drain structure in the second transistor, and a source-drain epitaxial growth is performed in the second source-drain groove to form a second source-drain structure in the lateral diffusion device. A dielectric material is deposited on the third source-drain structure, the second source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the third interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the third pseudo-gate structure and the second pseudo-gate structure. Next, the third pseudo-gate structure and the second pseudo-gate structure are removed to expose the gate groove, and metal material is deposited in the gate groove to form the third gate structure in the second transistor and the second gate structure in the lateral diffusion device. An insulating material is deposited on the third interlayer dielectric layer and the second interlayer dielectric layer to form a second contact layer. By photolithography, the second contact layer, the third interlayer dielectric layer and the second interlayer dielectric layer are etched to form a third through hole located on the upper surface of the third source and drain structure and a second through hole located on the upper surface of the second source and drain structure. Metal material is deposited in the third through hole and the second through hole to form a third source and drain metal and a second source and drain metal. Finally, a back-end process is performed on the second contact layer to form a third metal interconnect layer in the second transistor and a second metal interconnect layer in the lateral diffusion device.

[0087] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 This is a design layout of the semiconductor structure in the embodiment of this application. Figure 2(a) is the design layout of the lateral diffusion device. It should be noted that for ease of understanding, only the fin structure, gate structure and source-drain structure are shown in the design layout; (b) is the design layout of the first transistor; (c) is the design layout of the isolation device; and (d) is the design layout of the second transistor. Figure 3 A schematic diagram of a semiconductor structure in an embodiment of the present application. Figure 3 (a) is a cross-sectional view of the semiconductor structure made along the AA' direction of the lateral diffusion region; (b) is a cross-sectional view of the semiconductor structure made along the BB' direction of the lateral diffusion region; (c) is a cross-sectional view of the semiconductor structure made along the A1-A1' direction of the core region; (d) is a cross-sectional view of the semiconductor structure made along the B1-B1' direction of the core region.

[0088] Figure 3 In the semiconductor structure 10 shown, the lateral diffusion device and the first transistor are arranged side by side, the first fin-shaped structure is subjected to a first fin-cutting process, the etching depth is a full-width depth, and the second fin-shaped structure is not subjected to a fin-cutting process.

[0089] In combination with the above preparation method, Figure 3 The preparation process of the semiconductor structure 10 is described below. Figure 3 The semiconductor structure 10 shown may be FIG. 4A to FIG. 4D The process shown is prepared FIG. 4A to FIG. 4D It is a schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application.

[0090] In one example, a first preparation process of the semiconductor structure 10 may include the following steps:

[0091] Step 1: Provide a Si substrate 21, coat the Si substrate 21 with photoresist, and perform two ion implantations in the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region (see Figure 4A (a) in the figure.

[0092] Step 2: remove the photoresist on the Si substrate 21, apply photoresist on the N-type drift region to form a photoresist layer 24, etch the substrate 21 under the mask of the photoresist layer 24, and form a fin structure 22 in the core region and the P-type well region. The fin structure 22 includes a first fin structure 221 and a second fin structure 222. The N-type drift region that has not been etched forms a planar block structure 25 (see Figure 4A (b) in the above example. Figure 4A As shown in (b), it is a cross-sectional view of the lateral diffusion region in the AA' direction, and the shape of the fin structure in the lateral diffusion region is shown by the dotted line. The fin structure is located in the P-type well region.

[0093] It should be noted that in FIG. 4A to FIG. 4D In the embodiment, the core region includes one fin structure and the lateral diffusion region includes two fin structures for illustration only; the number of fin structures can be set according to actual needs and is not limited to the above. FIG. 4A to FIG. 4D For the structure shown, the embodiment of the present application does not specifically limit the number of fin structures.

[0094] Step 3: Perform a first fin cutting process on the first fin-shaped structure 221 to form a first fin cutting groove 231 (see Figure 4A (c) in the figure). The etching depth is the full-width depth.

[0095] Step 4: Deposit oxide on the substrate 21 and the fin structure 22 to form a first shallow trench isolation structure 41. The first shallow trench isolation structure 41 wraps the fin structure 22, covers the substrate 21, and fills the first fin cut trench 231. Then, a first portion of the first shallow trench isolation structure 41 is etched to expose the first fin structure 221. Deposit oxide on the surface of the first fin structure 221 to form a first gate oxide layer 261. A first dummy gate structure 311, a first spacer 111, a second dummy gate structure 312, and a second spacer 121 are formed on the first gate oxide layer 261 (see Figure 4B (a) in the figure.

[0096] It should be noted that the first gate oxide layer 261 can be made of the same material as the first shallow trench isolation structure 41 .

[0097] Step 5: Etch the first fin structure 221 to form a first source-drain groove and a second source-drain groove, perform source-drain epitaxial growth in the first source-drain groove and the second source-drain groove to form a first source-drain structure 112 and a second source-drain structure 122 (see Figure 4B (b) in the figure.

[0098] Step 6: Deposit dielectric material on the etched first shallow trench isolation structure 41, the first source-drain structure 112, and the second source-drain structure 122 to form a first interlayer dielectric layer 113 and a second interlayer dielectric layer 123. Remove the first dummy gate structure 311 and the second dummy gate structure 312 to expose the gate groove, and deposit insulating material on the surface of the gate groove to form a first gate dielectric layer 114 and a second gate dielectric layer 124; then, deposit metal material in the gate groove to form a first gate structure 115 and a second gate structure 125. Deposit dielectric material on the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 to form a first contact layer 271. Photolithography is performed on the first contact layer 271, the first interlayer dielectric layer 113, and the second interlayer dielectric layer 123 to form a first through hole and a second through hole; deposit metal material in the first through hole and the second through hole to form a first source-drain metal 116 and a second source-drain metal 126 (see Figure 4B(c) in the figure). A back-end process is performed on the first contact layer 271 to form a first metal interconnection layer and a second metal interconnection layer (not shown in the figure).

[0099] It should be noted that the first contact layer 271 can be made of the same material as the spacers (such as the first spacers 111 and the second spacers 121 ).

[0100] Step 7: After forming the first transistor 11 and the lateral diffusion device 12, an insulating material is deposited on the first transistor 11 and the lateral diffusion device 12 to form a first insulating layer 15, and then the carrier wafer 16 is bonded to the first insulating layer 15 (see Figure 4C (a) in the figure.

[0101] Step 8: Flip the first transistor 11 and the lateral diffusion device 12, and remove the substrate 21, so that the second fin structure 222 is placed upward (see Figure 4C (b) in the figure.

[0102] Step 9: Remove the second portion of the first shallow trench isolation structure 41 by etching, so that the second fin structure 222 is exposed, and a shallow trench isolation layer 40 is formed. Oxide is deposited on the surface of the exposed second fin structure 222 to form a second gate oxide layer 262. A third dummy gate structure 313 and a third spacer 131 are formed on the second gate oxide layer 262 in the core region (see FIG. Figure 4C (c) in the figure.

[0103] Step 10: Form the third source-drain structure 132 in the second transistor 13 by referring to the steps in step 5 above (see Figure 4D (a) in the figure.

[0104] Step 11: Referring to the steps of step 6 above, a third interlayer dielectric layer 133, a third gate dielectric layer 134, a third gate structure 135, a second contact layer 272, a third source-drain metal 136 and a fourth interlayer dielectric layer 143 in the isolation device 14 are formed in the second transistor 13 (see Figure 4D and forming a third metal interconnection layer in the second transistor 13 and a back dielectric layer in the isolation device 14 (not shown in the figure).

[0105] At this point, the semiconductor structure 10 is manufactured according to the first manufacturing method.

[0106] In some embodiments, the first preparation method mentioned above only performs fin cutting processing on the first fin structure (i.e., the first fin cutting processing), and the fin cutting depth is the full-width depth; based on the first preparation method, the second preparation method provided in the embodiment of the present application can only perform fin cutting processing on the second fin structure (i.e., the second fin cutting processing), and the fin cutting depth is the full-width depth; the preparation methods of other structures (such as the first source and drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the second preparation method are the same as the first preparation method mentioned above, and the embodiment of the present application does not make specific limitations on this.

[0107] In some embodiments, in the third method for preparing the semiconductor structure, the lateral diffusion device is arranged side by side with the first transistor; during the preparation process, the first fin structure is subjected to a first fin cutting process, and the etching depth of the first fin cutting process is half the depth, and the second fin structure is subjected to a second fin cutting process, and the etching depth of the second fin cutting process is half the depth. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the third preparation method are the same as those of the first preparation method described above, and the embodiments of the present application do not specifically limit this.

[0108] In some embodiments, in a fourth method for preparing a semiconductor structure, a lateral diffusion device is arranged side by side with a first transistor; during the preparation process, a first fin cutting process is performed on the first fin structure, and the etching depth of the first fin cutting process is half the depth, and a second fin cutting process is performed on the second fin structure, and the etching depth of the second fin cutting process is full depth. Figure 5 FIG. 1 is a schematic diagram of the fourth preparation process of the semiconductor structure in the embodiment of the present application, see Figure 5 As shown, after the second fin-shaped structure is subjected to the second fin cutting process, a second fin cutting groove 232 is formed. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the fourth preparation method are the same as the first preparation method mentioned above, and the embodiments of the present application do not specifically limit this.

[0109] In some embodiments, in a fifth method for preparing a semiconductor structure, a lateral diffusion device is arranged side by side with a second transistor; during the preparation process, only the first fin structure is subjected to a first fin cutting process, the etching depth of the first fin cutting process is the full-width depth, and the second fin structure is not subjected to a fin cutting process. Figure 6 FIG. 1 is a schematic diagram of the fifth preparation process of the semiconductor structure in the embodiment of the present application, see Figure 6As shown, when the lateral diffusion device and the second transistor are arranged side by side, the ion implantation depth of the N-type drift region is deeper. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the fifth preparation method are the same as those of the first preparation method, and the embodiments of the present application do not specifically limit this.

[0110] In some embodiments, in the sixth method for preparing the semiconductor structure, the lateral diffusion device is arranged side by side with the second transistor; during the preparation process, only the second fin structure is subjected to the second fin cutting process, the etching depth of the second fin cutting process is the full width depth, and the first fin structure is not subjected to the fin cutting process. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the sixth preparation method are the same as those of the first preparation method described above, and the embodiments of the present application do not specifically limit this.

[0111] In some embodiments, in the seventh preparation method of the semiconductor structure, the lateral diffusion device and the second transistor are arranged side by side; during the preparation process, the first fin structure is subjected to a first fin cutting process, and the etching depth of the first fin cutting process is half the depth, and the second fin structure is subjected to a second fin cutting process, and the etching depth of the second fin cutting process is half the depth. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the seventh preparation method are the same as those of the first preparation method described above, and the embodiments of the present application do not specifically limit this.

[0112] In some embodiments, in the eighth preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the second transistor; during the preparation process, the first fin structure is subjected to a first fin cutting process, and the etching depth of the first fin cutting process is half the depth, and the second fin structure is subjected to a second fin cutting process, and the etching depth of the second fin cutting process is half the depth. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the seventh preparation method are the same as the first preparation method mentioned above, and the embodiments of the present application do not specifically limit this.

[0113] In the embodiment of the present application, by forming a fin structure and a planar block structure in the lateral diffusion region, the formed lateral diffusion device can withstand higher voltages while being fully compatible with the process of preparing stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0114] Furthermore, since the lateral diffusion device can be arranged side by side with the first transistor or the second transistor, and the etching depth of the first fin cutting process and the second fin cutting process can be selected as full depth or half depth according to actual needs, the layout of the internal devices of the semiconductor structure is more flexible.

[0115] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing, such as a lateral diffusion device arranged side by side with the first transistor or arranged side by side with the second transistor, and the lateral diffusion device includes a fin-type diffusion region and a planar diffusion region.

[0116] Furthermore, the method for preparing the semiconductor structure described in the embodiment of the present application can be applied to the next generation integrated circuit process, and is a process-compatible LDMOS transistor solution with great application potential.

[0117] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 3 The semiconductor structure shown will not be described in detail here.

[0118] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 3 and Figure 5 , I will not go into details here.

[0119] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0120] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure comprises a lateral diffusion device and a core device, wherein the core device comprises a first transistor and a second transistor stacked along a first direction; the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; The method comprises: A substrate is provided; the substrate comprises a lateral diffusion region and a core region; the lateral diffusion region and the core region are arranged adjacent to each other in a second direction; the second direction is perpendicular to the first direction; Performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region; Etching the P-type well region and the core region to form a fin structure and a planar block structure; the fin structure includes a first fin structure and a second fin structure stacked along the first direction; the planar block structure is formed based on the N-type drift region that is not etched in the lateral diffusion region; the planar block structure includes a first planar block structure and a second planar block structure stacked along the first direction; Based on the first fin structure, forming the first transistor; flipping the wafer and removing the substrate; Based on the second fin structure, forming the second transistor; The method further includes: performing a first fin-cutting process on the first fin-shaped structure to form a first fin-cutting groove, and / or performing a second fin-cutting process on the second fin-shaped structure to form a second fin-cutting groove; the first fin-cutting groove is perpendicular to the extension direction of the first fin-shaped structure, and the etching depth of the first fin-cutting groove is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure; the second fin-cutting groove is perpendicular to the extension direction of the second fin-shaped structure, and the etching depth of the second fin-cutting groove is half of the height of the fin-shaped structure or equal to the height of the fin structure.

2. The method according to claim 1, characterized in that The etching of the P-type well region and the core region to form a fin-shaped structure and a planar block structure includes: coating a photoresist on the N-type drift region to form a photoresist layer; Under the masking effect of the photoresist layer, the P-type well region and the core region are etched to form a fin structure located in the P-type well region and the core region, and a planar block structure located in the N-type drift region.

3. The method according to claim 1, characterized in that Before forming the first transistor based on the first fin structure, the method further includes: Depositing oxide on the substrate and the fin-shaped structure to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the fin-shaped structure; A first portion of the first shallow trench isolation structure is removed to expose the first fin structure.

4. The method according to claim 3, characterized in that In the case where a first fin cutting process is performed on the first fin-shaped structure; The step of depositing oxide on the substrate and the fin structure to form a first shallow trench isolation structure comprises: Depositing oxide on the substrate and the fin-shaped structure, and depositing oxide in the first fin-cut trench to form a first shallow trench isolation structure; The first shallow trench isolation structure fills the first fin-cut trench.

5. The method according to claim 3, characterized in that: In the case where a second fin cutting process is performed on the second fin-shaped structure; Before forming the second transistor based on the second fin structure, the method further includes: Depositing oxide in the second fin-cut trench to form a second shallow trench isolation structure; the second shallow trench isolation structure fills the second fin-cut trench; The second portion of the first shallow trench isolation structure and the third portion of the second shallow trench isolation structure are removed to expose the second fin structure; the height of the second portion is the same as the height of the third portion.

6. The method according to claim 1, characterized in that In the case where the lateral diffusion device and the first transistor are arranged side by side, While forming the first transistor based on the first fin structure, the method further includes: forming the lateral diffusion device based on the first fin structure and the first planar block structure located in the lateral diffusion region; While forming the second transistor based on the second fin structure, the method further includes: forming an isolation device based on the second fin structure located in the lateral diffusion region and the second planar block structure; and the isolation device and the lateral diffusion device are stacked along the first direction.

7. The method according to claim 1, characterized in that In the case where the lateral diffusion device and the second transistor are arranged side by side, While forming the first transistor based on the first fin structure, the method further includes: forming an isolation device based on the first fin structure located in the lateral diffusion region and the first planar block structure; While forming the second transistor based on the second fin structure, the method further includes: forming the lateral diffusion device based on the second fin structure and the second planar block structure located in the lateral diffusion region; and stacking the isolation device and the lateral diffusion device along the first direction.

8. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method according to any one of claims 1 to 7, wherein the semiconductor structure comprises: A core device; the core device comprises a first transistor and a second transistor stacked along the first direction; A lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; an isolation device; the isolation device and the lateral diffusion device are stacked in the first direction, and the isolation device is arranged side by side with the second transistor or with the first transistor; The lateral diffusion device comprises a fin-shaped structure and a planar block-shaped structure. The fin-shaped structure is formed by etching a P-type well region in the lateral diffusion device, and the planar block-shaped structure is an N-type drift region in the lateral diffusion device.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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