Semiconductor element
By introducing Schottky barrier metal or non-metallic electrode materials into the gate electrode, bilateral carrier depletion is achieved, which solves the problems of limited conductivity and high process accuracy requirements of traditional MOSFETs, and improves the flow capacity and productivity.
Patent Information
- Application Number
- CN202310844907.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-10
- Publication Date
- 2025-01-14
AI Technical Summary
In the conduction state of traditional pn junction MOSFET, the electronic conductive channel needs to pass through the p-type conductive region, resulting in limited flow capacity. In the normal-off function, the width of the n-type semiconductor region is high, which affects process accuracy and batch volume. Productivity yield.
Introducing Schottky barrier metal or non-metallic electrode materials into the gate electrode, increasing carrier depletion effect, achieving bilateral depletion, relaxing the width requirements of n-type semiconductor regions, and reducing lithography and etching technology accuracy requirements.
It improves the flow capacity of the electronic conductive channels, reduces device losses and off-state leakage, expands the process window, and improves the yield of mass production.
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Figure CN119317154A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and in particular, relates to a semiconductor element. Background Art
[0002] In traditional pn junction field effect transistors, taking the enhancement mode pn junction MOSFET as an example, in order to achieve the normally-off function, the p-type well region in the semiconductor layer of the traditional pn junction MOSFET is always in direct contact with the gate insulating film. GS = 0 and the drain-source voltage V DS = 0, the pn junction between the drain and source will form a space charge region; when the gate-source voltage V GS = 0 and the drain-source voltage V DS >0, the pn junction between the drain and source is reverse biased, the space charge region formed is widened, and no complete electronic conduction channel is formed between the drain and source. At this time, no current flows between the drain and source; when the gate-source voltage V GS When the gate-source voltage V GS Continue to increase to V GS(th) (gate voltage when the electron conductive channel is just formed), a complete electron conductive channel is formed between the drain electrode and the source electrode. At this time, the drain-source voltage V DS When >0, a certain current will flow between the drain and the source.
[0003] However, in the on state of the conventional pn junction MOSFET, the electron conduction channel between the drain and the source must pass through both the n-type conduction region and the p-type conduction region of the semiconductor layer. Among them, the electron conduction channel in the p-type conduction region of the semiconductor layer is relatively narrow and has the smallest current capacity, which becomes the bottleneck of the current capacity of the entire electron conduction channel between the drain and the source. This bottleneck hinders the further improvement of the current capacity of the conventional pn junction MOSFET.
[0004] To address this problem, the applicant has optimized the design of the structure of the traditional pn junction MOSFET in the patent application number 202310324836.6, so that the p-type well region is no longer in contact with the gate insulating film, and there is an n-type semiconductor region between the p-type well region and the gate insulating film, so that in the on state, the electron conduction channel between the drain and the source only passes through the n-type semiconductor region and no longer passes through the p-type well region. Through this change in structural details, while maintaining the normally-off function of the device, the bottleneck of the electron conduction channel between the drain and the source is eliminated, the width of the electron conduction channel is widened, thereby improving the flow capacity of the electron conduction channel between the drain and the source, which helps to further reduce device losses.
[0005] However, in the equilibrium state (when V DS =0&V GS =0), the normally-off function is achieved by utilizing the unilateral depletion effect of the pn junction composed of the p-type well region and the n-type semiconductor region in contact therewith on the electron carriers in the n-type semiconductor layer. Since the influence area of the unilateral depletion is limited, it is necessary to make the width of the n-type semiconductor region between the gate insulating film and the p-type well region as small as possible to ensure a good normally-off effect. This places extremely high demands on the wafer manufacturing process, especially the lithography & etching technology and equipment, with a narrow process window and low fault tolerance, which will affect the electrical performance of the device, especially the off-state leakage, and thus affect the yield of mass production. Summary of the invention
[0006] In view of this, the present invention introduces a metal material that can form a Schottky barrier with the semiconductor layer into the gate electrode or adopts a non-metallic electrode material that can deplete the carriers in the semiconductor layer in the gate electrode, thereby increasing the depletion effect of the gate electrode on the carriers in the semiconductor layer, and further realizing bilateral depletion. This can relax the key width dimension requirements, thereby reducing the requirements for lithography & etching technology and equipment and expanding the process window.
[0007] In order to achieve the above object, the present invention provides a semiconductor element, wherein the semiconductor element is a pn junction field effect transistor, and the semiconductor element comprises:
[0008] A first semiconductor layer, which is composed of a semiconductor material of a first conductivity type;
[0009] a second semiconductor layer, which is stacked on one side of the first semiconductor layer, and includes a first semiconductor region and a second semiconductor region, wherein the first semiconductor region is composed of a semiconductor material of a first conductivity type, and the second semiconductor region is composed of a semiconductor material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type;
[0010] Electrodes, including a drain electrode, a source electrode and a gate electrode;
[0011] a gate insulating film disposed between the gate electrode and the second semiconductor layer;
[0012] Features:
[0013] The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer;
[0014] The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, and the source electrode is connected to the first semiconductor region of the second semiconductor layer and the second semiconductor region of the second semiconductor layer respectively;
[0015] The second semiconductor region of the second semiconductor layer connected to the source electrode is not in contact with the gate insulating film, and a third semiconductor region exists between the second semiconductor region of the second semiconductor layer connected to the source electrode and the gate insulating film, and the third semiconductor region is composed of the semiconductor material of the first conductivity type;
[0016] The gate electrode at least includes a metal material having a Schottky barrier with the third semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes an electrode material, the electrode material is in contact with the gate insulating film, and the electrode material is composed of an electrode material of the second conductive type.
[0017] Preferably, the first conductivity type is n-type, and the second conductivity type is p-type.
[0018] Preferably, when the first conductivity type is n-type and the second conductivity type is p-type, the gate electrode includes a metal material having a Schottky barrier with the third semiconductor region (first conductivity type) of the second semiconductor layer, and the metal material is in contact with the gate insulating film.
[0019] Furthermore, the metal material is Pt, Ni, Co, Au, or W.
[0020] Preferably, when the first conductivity type is n-type and the second conductivity type is p-type, the gate electrode uses a p-type conductive electrode material, and the p-type conductive electrode material is in contact with a gate insulating film.
[0021] Furthermore, the p-type conductive electrode material is boron-doped p-type conductive polysilicon.
[0022] Preferably, the width of the third semiconductor region between the second semiconductor region of the second semiconductor layer and the gate insulating film is in the range of 3 nm to 400 nm.
[0023] Furthermore, the width of the third semiconductor region between the second semiconductor region of the second semiconductor layer and the gate insulating film is in the range of 3 nm to 400 nm.
[0024] Preferably, the semiconductor element is a vertical MOSFET.
[0025] Furthermore, the vertical MOSFET is a planar gate MOSFET, a trench gate MOSFET, a shielded gate MOSFET, or a super junction MOSFET.
[0026] The present invention provides a semiconductor element, wherein the semiconductor element is an insulated gate bipolar transistor, and the semiconductor element comprises:
[0027] A first semiconductor layer including a first p-type semiconductor region;
[0028] a second semiconductor layer, stacked on the first semiconductor layer, comprising an n-type semiconductor region and a second p-type semiconductor region;
[0029] Electrodes, including a collector, an emitter, and a gate electrode;
[0030] a gate insulating film disposed between the gate electrode and the second semiconductor layer;
[0031] Features:
[0032] The collector electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer;
[0033] The emitter is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, and the emitter is connected to the n-type semiconductor region of the second semiconductor layer and the second p-type semiconductor region of the second semiconductor layer respectively;
[0034] The second p-type semiconductor region of the second semiconductor layer is not in contact with the gate insulating film, and an n-type semiconductor region exists between the second p-type semiconductor region of the second semiconductor layer and the gate insulating film;
[0035] The gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.
[0036] Preferably, the work function of the metal material is greater than the work function of the corresponding material of the second semiconductor layer.
[0037] Preferably, the p-type conductive electrode material is boron-doped p-type conductive polysilicon.
[0038] Preferably, the width of the n-type semiconductor region between the second p-type semiconductor region of the second semiconductor layer connected to the emitter and the gate insulating film is in a range of 3 nm to 400 nm.
[0039] Furthermore, the width of the n-type semiconductor region between the second p-type semiconductor region of the second semiconductor layer connected to the emitter and the gate insulating film is in the range of 3 nm to 200 nm.
[0040] Preferably, the insulated gate bipolar transistor is a planar gate IGBT, a trench gate IGBT, a shielded gate IGBT or a super junction IGBT.
[0041] The present invention further provides a semiconductor element, wherein the semiconductor element is a trench MOS type pn junction diode, and the semiconductor element comprises:
[0042] A first semiconductor layer including a first n-type semiconductor region;
[0043] a second semiconductor layer, which is stacked between the first semiconductor layers and includes a second n-type semiconductor region and a p-type semiconductor region; the second semiconductor layer has a groove, and the groove opens from a side of the second semiconductor layer opposite to the first semiconductor layer;
[0044] a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer and forming an ohmic contact therewith;
[0045] an anode electrode formed on a surface of the second semiconductor layer opposite to the first semiconductor layer and forming an ohmic contact therewith;
[0046] a trench MOS gate, which is buried in the trench and wrapped by a gate insulating film, wherein the trench MOS gate and the second semiconductor layer are separated by the gate insulating film, and the trench MOS gate is in contact with the anode electrode;
[0047] Features:
[0048] The anode electrode is connected to the second n-type semiconductor region of the second semiconductor layer and to the p-type semiconductor region of the second semiconductor layer;
[0049] The p-type semiconductor region of the second semiconductor layer connected to the anode electrode is not in contact with the gate insulating film, and the second n-type semiconductor region exists between the p-type semiconductor region of the second semiconductor layer connected to the anode electrode and the gate insulating film;
[0050] The trench MOS gate at least includes a metal material having a Schottky barrier with the second n-type semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film;
[0051] The width of the second n-type semiconductor region of the second semiconductor layer connected to the anode electrode is in a range of 3 nm to 400 nm.
[0052] Preferably, the work function of the metal material is greater than the work function of the corresponding material of the second semiconductor layer.
[0053] Preferably, the p-type conductive electrode material is boron-doped p-type conductive polysilicon.
[0054] Preferably, the width of the second n-type semiconductor region of the second semiconductor layer connected to the anode electrode is in a range of 3 nm to 200 nm.
[0055] The present invention further provides a semiconductor element, wherein the semiconductor element is a pn junction field effect transistor, and the semiconductor element comprises:
[0056] A first semiconductor layer including a first n-type semiconductor region;
[0057] A second semiconductor layer, stacked on the first semiconductor layer, comprising a first n-type semiconductor region, a p-type semiconductor region and a high-resistance semiconductor region;
[0058] Electrodes, including a drain electrode, a source electrode and a gate electrode;
[0059] a gate insulating film disposed between the gate electrode and the second semiconductor layer;
[0060] Features:
[0061] The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer;
[0062] The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, and is connected to both the second n-type semiconductor region of the second semiconductor layer and the p-type semiconductor region of the second semiconductor layer;
[0063] The p-type semiconductor region of the second semiconductor layer connected to the source electrode is not in contact with the gate insulating film, and the high-resistance semiconductor region exists between the p-type semiconductor region of the second semiconductor layer connected to the source electrode and the gate insulating film;
[0064] The gate electrode at least includes a metal material having a Schottky barrier with the high-resistance semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes an electrode material with p-type conductivity, and the electrode material with p-type conductivity is in contact with the gate insulating film.
[0065] Preferably, the work function of the metal material is greater than the work function of the corresponding material of the second semiconductor layer.
[0066] Preferably, the p-type conductive electrode material is p-type conductive polysilicon.
[0067] Preferably, the semiconductor element is a planar gate MOSFET, a trench gate MOSFET, a shielded gate MOSFET or a super junction MOSFET.
[0068] Preferably, the material of the semiconductor layer is gallium oxide, and the high-resistance semiconductor region is nitrogen (N)-doped gallium oxide.
[0069] The present invention has the following beneficial effects:
[0070] The semiconductor element of the present invention introduces a metal material that can generate a Schottky barrier between the gate electrode and the semiconductor layer or a non-metallic conductive material that can deplete the carriers in the semiconductor layer. Taking an n-channel normally-off MOSFET as an example, on the basis of the original pn junction formed by the p-type semiconductor region and the n-type semiconductor region to deplete the electron carriers in the n-type semiconductor region from one side, a Schottky gate or a p-type gate is introduced to deplete the electron carriers in the n-type semiconductor region from the other side, thereby achieving the effect of double-side depletion. From the perspective of electrical performance, the on-state current capacity is maintained and the off-state leakage is further reduced, and it is also beneficial to the regulation of the turn-on voltage. From the perspective of process technology, the key width dimension requirements can be relaxed, the requirements for photolithography & etching technology and equipment can be reduced, the process window can be expanded, and the mass production yield can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0071] In order to more clearly illustrate the technical solution of the present invention, the following will briefly introduce the drawings required for use in the embodiments or prior art descriptions. Obviously, some of the drawings in the following description are only illustrations of some embodiments of the present invention, and the protection scope required by the present invention is not limited to the embodiments. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work.
[0072] Attached Figure 1 FIG. 1 is a vertical cross-sectional view of an embodiment of a conventional pn junction trench gate MOSFET.
[0073] Attached Figure 2 It is a vertical cross-sectional view of an embodiment of a trench gate MOSFET disclosed in application number 202310324836.6.
[0074] Attached Figure 3a FIG. 1 is a vertical cross-sectional view of a first example of a trench gate MOSFET according to an embodiment of the present invention.
[0075] Attached Figure 3b FIG. 1 is a vertical cross-sectional view of a second example of a trench gate MOSFET according to an embodiment of the present invention.
[0076] Attached Figure 4a It is a vertical cross-sectional view of a first example of a shielded gate MOSFET according to an embodiment of the present invention.
[0077] Attached Figure 4b It is a vertical cross-sectional view of a second example of a shielded gate MOSFET according to an embodiment of the present invention.
[0078] Attached Figure 4c 1 is a vertical cross-sectional view of a third example of a shielded gate MOSFET according to an embodiment of the present invention.
[0079] Attached Figure 4d 1 is a vertical cross-sectional view of a fourth example of a shielded gate MOSFET according to an embodiment of the present invention.
[0080] Attached Figure 4e It is a vertical cross-sectional view of a fifth example of a shielded gate MOSFET according to an embodiment of the present invention.
[0081] Attached Figure 4f 1 is a vertical cross-sectional view of a sixth example of a shielded gate MOSFET according to an embodiment of the present invention.
[0082] Attached Figure 5a It is a vertical cross-sectional view of a first example of a super junction MOSFET according to an embodiment of the present invention.
[0083] Attached Figure 5b It is a vertical cross-sectional view of a second example of a super junction MOSFET according to an embodiment of the present invention.
[0084] Attached Figure 6a It is a vertical cross-sectional view of a first example of an insulated gate bipolar transistor according to an embodiment of the present invention.
[0085] Attached Figure 6b It is a vertical cross-sectional view of a second example of an insulated gate bipolar transistor according to an embodiment of the present invention.
[0086] Attached Figure 7a It is a vertical cross-sectional view of a first example of a trench MOS type pn junction diode according to an embodiment of the present invention.
[0087] Attached Figure 7b It is a vertical cross-sectional view of a second example of a trench MOS type pn junction diode according to an embodiment of the present invention.
[0088] The technical features corresponding to the marks in the accompanying drawings are:
[0089] 11 Drain electrode
[0090] 12 Source electrode
[0091] 12c shielding source electrode 12c
[0092] 13 Gate electrode
[0093] 13a n-type gate electrode
[0094] 13b p-type gate electrode
[0095] 13c Schottky gate electrode
[0096] 14 Collector
[0097] 15 Emitter
[0098] 21Semiconductor District
[0099] 21a n+ type semiconductor region
[0100] 21b n-type semiconductor region
[0101] 21c n+ type semiconductor region
[0102] 31a p+ type semiconductor region
[0103] 31b p-type semiconductor region
[0104] 31c super junction p-type column region
[0105] 41 High resistance semiconductor region
[0106] 51a Gate insulating film
[0107] 51b Non-gate insulating film
[0108] 61 cathode
[0109] 62 Anode
[0110] 63 Trench MOS Gate DETAILED DESCRIPTION
[0111] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.
[0112] Attached Figure 1FIG. 1 is a vertical cross-sectional view of an embodiment of a conventional pn junction trench gate MOSFET. Figure 1 The pn junction trench gate MOSFET shown has: a drain electrode 11, an n+ type semiconductor region 21a, an n- type semiconductor region 21b, a p- type semiconductor region 31b and an n+ type semiconductor region 21c located thereon, and a trench embedded in the n- type semiconductor region 21b from the upper surface of the semiconductor layer from top to bottom, a gate electrode 13 located in the trench and covered by a gate insulating film 51a, and a source electrode 12 located on the upper surface of the semiconductor layer.
[0113] Attached Figure 1 In the MOSFET shown in the figure, the p-type semiconductor region 31b connected to the source electrode 12 is in contact with the gate insulating film 51a. Due to the presence of the pn junction in the body, when only a forward voltage is applied between the drain electrode 11 and the source electrode 12, the pn junction in the pn junction type MOSFET body is reverse biased to widen the depletion region, so that a complete electronic conduction channel is not formed between the drain electrode 11 and the source electrode 12, and no current flows between the drain and the source. Based on this principle, the attached Figure 1 The pn junction MOSFET shown is a normally-off device. When a forward voltage is applied between the drain electrode 11 and the source electrode 12, and a voltage V is applied between the gate electrode 13 and the source electrode 12, GS >0, an electron conduction channel will gradually form between the drain electrode 11 and the source electrode 12. When the voltage V applied between the gate electrode 13 and the source electrode 12 GS >V GS(th) (gate-source voltage when the channel is formed) will form an n-type thin layer (inversion layer) where only electron carriers gather in the area of the p-type semiconductor region 31b close to the gate insulating film 51a. This n-type thin layer connects the electronic conduction channel between the drain electrode 11 and the source electrode 12, and current will flow between the drain and the source, and the device will be turned on.
[0114] Attached Figure 2 2 is a vertical cross-sectional view of an embodiment of a trench gate MOSFET applied for by the present applicant in patent application number 202310324836.6. Figure 2 The MOSFET shown is Figure 1 The difference of the MOSFET shown is that the p-type semiconductor region 31b connected to the source electrode 12 is not in contact with the gate insulating film 51a, and there is a semiconductor region 21 between the p-type semiconductor region 31b and the gate insulating film 51a (the semiconductor region 21 can be an n-type semiconductor region 21b or a high-resistance semiconductor region 41). In this embodiment, the semiconductor region 21 is an n-type semiconductor region 21b, and the width range of the semiconductor region 21 is between 3nm and 300nm, preferably between 3nm and 100nm.
[0115] For the attached Figure 2 In the MOSFET shown in FIG. 1 , in the equilibrium state, the pn junction formed by the p-type semiconductor region 31 b and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21, so there is no complete electron conduction channel between the drain electrode 11 and the source electrode 12. Figure 2 The MOSFET can be made into a normally-off device; when only a positive voltage is applied between the drain electrode 11 and the source electrode 12, the pn junction formed by the p-type semiconductor region 31b and the semiconductor region 21 is reverse biased to widen the depletion region, and the depletion effect on the electron carriers in the semiconductor region 21 is further strengthened. In this way, there is no conductive channel between the drain electrode 11 and the source electrode 12, that is, no current flows, and the device is turned off at this time; when the device is in the off state, the voltage V applied between the gate electrode 13 and the source electrode 12 GS >V GS(th) (gate-source voltage when channel is formed), an n-type thin layer where only electron carriers gather will be formed in the area of the semiconductor region 21 close to the gate insulating film 51a. This n-type thin layer connects the electronic conductive channel between the drain electrode 11 and the source electrode 12, and current will flow between the drain and the source, and the device will be turned on.
[0116] Attached Figure 2 The MOSFET shown is relative to the Figure 1 The difference between the MOSFETs shown is that the Figure 1 When the MOSFET shown is in the on state, the electron conduction channel between the drain electrode 11 and the source electrode 12 must pass through both the n-type semiconductor region and the p-type semiconductor region. Among them, the width of the electron conduction channel passing through the p-type semiconductor region is the narrowest, which is the bottleneck affecting the on-state current capacity. Figure 2 When the MOSFET shown is in the on state, the electron conduction channel between the drain electrode 11 and the source electrode 12 only passes through the n-type semiconductor region and no longer passes through the p-type semiconductor region. Through this change in detail, the bottleneck of the width of the electron conduction channel between the drain and the source is eliminated, and the width of the electron conduction channel between the drain and the source is widened, thereby improving the on-state current conduction capacity of the device, which helps to further reduce the device loss.
[0117] However, attached Figure 2 For the MOSFET shown in the figure, if it is to satisfy the normally-off function, the width of the semiconductor region 21 is very demanding, and the width of the semiconductor region 21 needs to be as small as possible. Taking silicon-based devices as an example, preferably, the width of the semiconductor region 21 needs to be ≤100nm. This places very high demands on the precision of wafer manufacturing equipment, especially lithography equipment, resulting in a narrow process window and a small fault tolerance, which can easily cause the width of the semiconductor region 21 to exceed the limit and cause large off-state leakage of the device.
[0118] Attached Figure 3aThis is a vertical cross-sectional view of a first example of a trench gate MOSFET according to an embodiment of the present invention, which includes a first semiconductor layer, a second semiconductor layer, a drain electrode 11 , a source electrode 12 , a gate electrode 13 , and a gate insulating film 51 a . The first semiconductor layer includes: an n+ type semiconductor region 21a stacked on the drain electrode 11; the second semiconductor layer includes an n- type semiconductor region 21b (first semiconductor region) stacked on the n+ type semiconductor region 21a, a p- type semiconductor region 31b (second semiconductor region) connected to the source electrode 12, and an n+ type semiconductor region 21c, and a semiconductor region 21 (third semiconductor region) is provided between the p- type semiconductor region 31b and the gate insulating film 51a. The semiconductor region 21 can be an n- type semiconductor region or a high resistance semiconductor region. In this embodiment, the semiconductor region 21 is an n- type semiconductor region, and the width of the semiconductor region 21 is in the range of 3nm to 300nm, preferably in the range of 3nm to 100nm; the gate electrode 13 is a trench gate electrode, including a Schottky gate electrode 13c and an n-type gate electrode 13a, the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.
[0119] Attached Figure 3a The MOSFET shown is Figure 2 The difference between the MOSFETs shown is that the Figure 3a In the MOSFET shown in the figure, a Schottky gate electrode 13c with a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced. The MIS (metal insulator semiconductor) junction composed of the Schottky gate electrode 13c, the gate insulating film 51a and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the p-type semiconductor region 31b. The pn junction composed of the p-type semiconductor region 31b and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21. Under the combined effect of these two depletion effects, the electron carriers in the semiconductor region 21 are completely depleted. From the process technology, to make a normally-off MOSFET and achieve the same normally-off effect, the attached Figure 3a The width of the semiconductor region 21 in the MOSFET shown can be compared to Figure 2 The design is relatively wider, which can reduce the requirements for lithography & etching technology and equipment, expand the process window, and improve the yield of mass production.
[0120] Attached Figure 3b FIG. 2 is a vertical cross-sectional view of a second example of a trench gate MOSFET according to an embodiment of the present invention. Figure 3b The MOSFET shown is Figure 3a The difference between the MOSFET structures shown is that the Figure 3bThe gate electrode 13 of the MOSFET shown includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon. In the equilibrium state, the p-type gate electrode 13b will also deplete the electron carriers in the semiconductor region 21, and then the pn junction formed by the p-type semiconductor region 31b and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21. Under the combined effect of these two depletion effects, the electron carriers in the semiconductor region 21 are completely depleted. From the process technology, to make a normally-off MOSFET and achieve the same normally-off effect, the attached Figure 3b The width of the semiconductor region 21 in the MOSFET shown can be compared to Figure 2 The design is relatively wider, which can reduce the requirements for lithography & etching technology and equipment, expand the process window, and improve the yield of mass production.
[0121] Attached Figure 4a FIG. 1 is a vertical cross-sectional view of a first example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 4a The MOSFET shown is a shielded gate MOSFET of a top-bottom gate structure, comprising: a first semiconductor layer, a second semiconductor layer, a drain electrode 11, a source electrode 12, a shielded gate electrode, and a gate insulating film 51a. The first semiconductor layer comprises: an n+ type semiconductor region 21a stacked on the drain electrode 11; the second semiconductor layer comprises an n- type semiconductor region 21b stacked on the n+ type semiconductor region 21a, a p- type semiconductor region 31b connected to the source electrode 12, and an n+ type semiconductor region 21c, wherein a semiconductor region 21 is provided between the p- type semiconductor region 31b and the gate insulating film 51a (the semiconductor region 21 may be an n- type semiconductor region 21b or a high resistance semiconductor region 41). In this embodiment, the semiconductor Region 21 is an n-type semiconductor region 21b, and the width range of the semiconductor region 21 is between 3nm and 300nm, preferably between 3nm and 100nm; the shielding gate electrode includes a gate electrode 13 and a shielding source electrode 12c, and the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, and the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the n-type gate electrode 13a can be phosphorus-doped n-type conductive polysilicon, and the Schottky gate electrode 13c is composed of a metal material.
[0122] Attached Figure 4b FIG. 2 is a vertical cross-sectional view of a second example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 4b The MOSFET shown is a shielded gate MOSFET with an upper and lower gate structure. Figure 4a The difference between the MOSFETs shown is that the Figure 4bThe gate electrode 13 of the MOSFET shown includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b , and the p-type gate electrode 13 b may be phosphorus-doped p-type polysilicon.
[0123] Attached Figure 4c FIG. 2 is a vertical cross-sectional view of a third example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 4c The MOSFET shown is a shielded gate MOSFET with left and right split gate structures. Figure 4a On the basis of the shielded gate MOSFET with the upper and lower gate structure shown, the structural design of the shielded gate region is adjusted, and the gate electrode 13 is distributed on the left and right sides of the shielding source electrode 12c.
[0124] Attached Figure 4d FIG. 4 is a vertical cross-sectional view of a fourth example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 4d The MOSFET shown is a shielded gate MOSFET with left and right split gate structures. Figure 4b On the basis of the shielded gate MOSFET with the upper and lower gate structure shown, the structural design of the shielded gate region is adjusted, and the gate electrode 13 is distributed on the left and right sides of the shielding source electrode 12c.
[0125] Attached Figure 4e FIG. 2 is a vertical cross-sectional view of a fifth example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 4e The MOSFET shown is another shielded gate MOSFET with left and right split gate structure. Figure 4a On the basis of the shielded gate MOSFET with the upper and lower gate structure shown, the structural design of the shielded gate region is adjusted, and the gate electrode 13 is distributed on the left and right sides of the shielding source electrode 12c.
[0126] Attached Figure 4f FIG. 2 is a vertical cross-sectional view of a sixth example of a shielded gate MOSFET according to an embodiment of the present invention. Figure 4f The MOSFET shown is another shielded gate MOSFET with left and right split gate structure. Figure 4b On the basis of the shielded gate MOSFET with the upper and lower gate structure shown, the structural design of the shielded gate region is adjusted, and the gate electrode 13 is distributed on the left and right sides of the shielding source electrode 12c.
[0127] Attached Figures 4a to 4fIn the shielded gate MOSFET shown, whether the gate electrode 13 is a Schottky gate electrode 13c or a p-type gate electrode 13b, the gate electrode 13 and the p-type semiconductor region 31b can achieve a better normally-off effect and smaller off-state leakage by virtue of the common depletion effect of the gate electrode 13 and the p-type semiconductor region 31b on the electron carriers in the semiconductor region 21; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.
[0128] Attached Figures 4a to 4f For the shielded gate MOSFET shown, the higher the work function of the metal material used for the Schottky gate electrode 13c, the wider the width of the semiconductor region 21 can be while maintaining the normally-off function. For example, metal materials with high work functions such as Pt, Ni, Au, Co, Cu, and Fe can be used.
[0129] Attached Figure 5a FIG. 1 is a vertical cross-sectional view of a first example of a super junction MOSFET according to an embodiment of the present invention. Figure 5a The super junction MOSFET shown includes a first semiconductor layer, a second semiconductor layer, a drain electrode 11 , a source electrode 12 , a gate electrode 13 , and a gate insulating film 51 a . The first semiconductor layer includes: an n+ type semiconductor region 21a stacked on the drain electrode 11; the second semiconductor layer includes an n- type semiconductor region 21b stacked on the n+ type semiconductor region 21a, a p- type semiconductor region 31b connected to the source electrode 12 and an n+ type semiconductor region 21c, and a super junction p-type column region 31c connected to the p-type semiconductor region 31b, wherein a semiconductor region 21 is provided between the p-type semiconductor region 31b and the gate insulating film 51a (the semiconductor region 21 may be an n-type semiconductor region 21b or a high resistance semiconductor region 41), in this embodiment, the semiconductor region 21 is an n-type semiconductor region 21b, and the width of the semiconductor region 21 is in the range of 3nm to 300nm, preferably in the range of 3nm to 100nm; the gate electrode 13 shown includes a Schottky gate electrode 13c, the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.
[0130] Attached Figure 5b FIG. 2 is a vertical cross-sectional view of a second example of a super junction MOSFET according to an embodiment of the present invention. Figure 5b The superjunction MOSFET shown is Figure 5a The difference between the superjunction MOSFET structure shown is that the attached Figure 5b The illustrated super junction MOSFET includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b , and the p-type gate electrode 13 b may be phosphorus-doped p-type polysilicon.
[0131] Attachment Figure 5aand attached Figure 5b In the super junction MOSFET shown, whether the gate electrode 13 is a Schottky gate electrode 13c or a p-type gate electrode 13b, the gate electrode 13 and the p-type semiconductor region 31b can achieve a better normally-off effect and smaller off-state leakage by virtue of the common depletion effect of the gate electrode 13 and the p-type semiconductor region 31b on the electron carriers in the semiconductor region 21; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.
[0132] Attached Figure 6a FIG. 1 is a vertical cross-sectional view of a first example of an insulated gate bipolar transistor according to an embodiment of the present invention. Figure 6a The insulated gate bipolar transistor shown includes a first semiconductor layer, a second semiconductor layer, a collector electrode 14 , an emitter electrode 15 , a gate electrode 13 , and a gate insulating film 51 a . The first semiconductor layer includes: a p+ type semiconductor region 31a connected to the collector electrode 14; the second semiconductor layer includes an n- type semiconductor region 21b stacked on the p+ type semiconductor region 31a, a p- type semiconductor region 31b connected to the source electrode 12, and an n+ type semiconductor region 21c, wherein a semiconductor region 21 is provided between the p- type semiconductor region 31b and the gate insulating film 51a (the semiconductor region 21 may be an n- type semiconductor region 21b or a high resistance semiconductor region 41), in this embodiment, the semiconductor region 21 is an n- type semiconductor region 21b, and the width of the semiconductor region 21 is in the range of 3nm to 300nm, preferably in the range of 3nm to 100nm; the gate electrode 13 shown includes a Schottky gate electrode 13c, the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.
[0133] Attached Figure 6b FIG. 2 is a vertical cross-sectional view of a second example of an insulated gate bipolar transistor according to an embodiment of the present invention. Figure 6b The insulated gate bipolar transistor shown is Figure 6a The difference between the insulated gate bipolar transistor shown is that the Figure 6b The gate electrode 13 of the insulated gate bipolar transistor shown includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b , and the p-type gate electrode 13 b may be phosphorus-doped p-type polysilicon.
[0134] Attachment Figure 6a and attached Figure 6bIn the insulated gate bipolar transistor shown, whether the gate electrode 13 is a Schottky gate electrode 13c or a p-type gate electrode 13b, the gate electrode 13 and the p-type semiconductor region 31b can achieve a better normally-off effect and smaller off-state leakage by virtue of the common depletion effect of the gate electrode 13 and the p-type semiconductor region 31b on the electron carriers in the semiconductor region 21; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.
[0135] Attached Figure 7a FIG. 1 is a vertical cross-sectional view of a first example of a trench MOS type pn junction diode according to an embodiment of the present invention. Figure 7a The trench MOS type pn junction diode shown in the figure has: a first semiconductor layer, which includes an n+ type semiconductor region 21a; a second semiconductor layer, which is stacked on the first semiconductor layer, including an n-type semiconductor region 21b, a p+ type semiconductor region 31a and a semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor region 21b or a high resistance semiconductor region 41). In this embodiment, the semiconductor region 21 is an n-type semiconductor region 21b, and the width of the semiconductor region 21 is in the range of 3nm to 300nm, and in this embodiment, it is preferably in the range of 3nm to 100nm. The second semiconductor layer has a groove, and the groove extends from the first semiconductor layer to the second semiconductor layer. The 2nd semiconductor layer is open on the side opposite to the 1st semiconductor layer; the cathode electrode 61 is formed on the surface of the 1st semiconductor layer on the side opposite to the 2nd semiconductor layer and forms an ohmic contact therewith; the anode electrode 62 is formed on the surface of the 2nd semiconductor layer on the side opposite to the 1st semiconductor layer and forms an ohmic contact therewith; the trench MOS gate 63 is buried in the trench and wrapped by the gate insulating film 51a, which is in contact with the anode electrode 62, and includes a Schottky gate electrode 13c and an n-type gate electrode 13a, the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.
[0136] Attached Figure 7aIn the trench MOS type pn junction diode shown, when a positive voltage is applied between the anode electrode 62 and the cathode electrode 61, a current will flow between the anode electrode 62 and the cathode electrode 61, and the diode will be forward-conducted. There are two paths for the current: the first current path is along the anode electrode 62—semiconductor region 21—n-type semiconductor region 21b—n+ type semiconductor region 21a—cathode electrode 61; the second current path is along the anode electrode 62—p+ type semiconductor region 31a—n-type semiconductor region 21b—n+ type semiconductor region 21a—cathode electrode 61. In the first current path, the current only passes through the n-type semiconductor region, and there is no pn junction barrier; in the second current path, the current will pass through the pn junction formed by the p+ type semiconductor region 31a and the n-type semiconductor region 21b, and there is a pn junction barrier. When the diode is forward-conducting, since there is no pn junction barrier in the first current path, its blocking effect is relatively small, and the required turn-on voltage is lower than that of the second current path, so the current flows preferentially through the first current path. Compared with the traditional trench MOS pn junction diode, this has a lower turn-on voltage and conduction loss.
[0137] Attached Figure 7a In the trench MOS type pn junction diode shown, when a reverse voltage is applied between the anode electrode 62 and the cathode electrode 61, the Schottky gate electrode 13c is electrically connected to the anode electrode 62 with a negative potential, and the Schottky gate electrode 13c repels and depletes the electron carriers in the semiconductor region 21; the reverse bias widening of the pn junction formed by the p+ type semiconductor region 31a and the semiconductor region 21 will have a depletion effect on the electron carriers in the semiconductor region 21. Under the combined effect of these two types of depletion effects, only a very small leakage current passes between the cathode electrode 61 and the anode electrode 62, and the diode is reversely cut off.
[0138] Attached Figure 7b FIG. 2 is a vertical cross-sectional view of a second example of a trench MOS type pn junction diode according to an embodiment of the present invention. Figure 7b The trench MOS type pn junction diode shown in the figure is Figure 7a The difference between the trench MOS type pn junction diode shown is that the attached Figure 7b The gate electrode 13 of the trench MOS type pn junction diode shown includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13 b , and the p-type gate electrode 13 b may be phosphorus-doped p-type polysilicon.
[0139] Attached Figure 7bIn the trench MOS type pn junction diode shown, when a reverse voltage is applied between the anode electrode 62 and the cathode electrode 61, the p-type gate electrode 13b is electrically connected to the anode electrode 62 with a negative potential, which will cause depletion of electron carriers in the semiconductor region 21; the reverse bias widening of the pn junction formed by the +-type semiconductor region 31a and the semiconductor region 21 will cause depletion of electron carriers in the semiconductor region 21; under the combined effect of these two types of depletion effects, only a very small leakage current passes between the cathode electrode 61 and the anode electrode 62, and the diode is reversely cut off.
[0140] The MOSFETs shown in various embodiments of the present invention are all n-channel MOSFETs based on the participation of electron carriers in conduction. The essence of the technical solution of the present invention is also applicable to p-channel MOSFETs based on the participation of hole carriers in conduction.
[0141] In the present invention, there is no specific limitation on the material of the semiconductor. The material of the semiconductor may be a single element semiconductor such as germanium, silicon, etc.; the material of the semiconductor may be a compound semiconductor such as silicon carbide, gallium nitride, gallium oxide, tin oxide, etc.
[0142] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.
Claims
1. A semiconductor element, wherein the semiconductor element is a pn junction field effect transistor, and the semiconductor element comprises: a first semiconductor layer, wherein the first semiconductor layer is composed of a semiconductor material of a first conductivity type; a second semiconductor layer stacked on one side of the first semiconductor layer, the second semiconductor layer comprising a first semiconductor region and a second semiconductor region, wherein the first semiconductor region is composed of a semiconductor material of a first conductivity type, and the second semiconductor region is composed of a semiconductor material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type; Electrodes, including a drain electrode, a source electrode and a gate electrode; a gate insulating film disposed between the gate electrode and the second semiconductor layer; Features: The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer; The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, and the source electrode is connected to the first semiconductor region of the second semiconductor layer and the second semiconductor region of the second semiconductor layer respectively; The second semiconductor region of the second semiconductor layer connected to the source electrode is not in contact with the gate insulating film, and a third semiconductor region is provided between the second semiconductor region of the second semiconductor layer connected to the source electrode and the gate insulating film, and the third semiconductor region is composed of the semiconductor material of the first conductivity type; The gate electrode at least includes a metal material having a Schottky barrier with the third semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes an electrode material, the electrode material is in contact with the gate insulating film, and the electrode material is composed of an electrode material of the second conductive type.
2. The semiconductor device according to claim 1, characterized in that The first conductivity type is n-type, the second conductivity type is p-type, and the semiconductor element is an n-channel pn junction field effect transistor.
3. The semiconductor device according to claim 1, wherein: The width of the third semiconductor region ranges from 3nm to 400nm.
4. The semiconductor device according to claim 1, wherein: The width of the third semiconductor region ranges from 3nm to 200nm.
5. A semiconductor element, the semiconductor element being an insulated gate bipolar transistor, the semiconductor element comprising: A first semiconductor layer including a first p-type semiconductor region; a second semiconductor layer, stacked on the first semiconductor layer, comprising an n-type semiconductor region and a second p-type semiconductor region; Electrodes, including a collector, an emitter, and a gate electrode; a gate insulating film disposed between the gate electrode and the second semiconductor layer; Features: The collector electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer; The emitter is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, and the emitter is connected to the n-type semiconductor region of the second semiconductor layer and the second p-type semiconductor region of the second semiconductor layer respectively; The second p-type semiconductor region of the second semiconductor layer is not in contact with the gate insulating film, and the n-type semiconductor region is provided between the second p-type semiconductor region of the second semiconductor layer and the gate insulating film; The gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.
6. The semiconductor device according to claim 5, characterized in that The width of the n-type semiconductor region between the second p-type semiconductor region of the second semiconductor layer and the gate insulating film is in a range of 3 nm to 400 nm.
7. The semiconductor device according to claim 5, characterized in that The width of the n-type semiconductor region between the second p-type semiconductor region of the second semiconductor layer and the gate insulating film is in a range of 3 nm to 200 nm.
8. A semiconductor element, the semiconductor element being a trench MOS type pn junction diode, the semiconductor element comprising: A first semiconductor layer including a first n-type semiconductor region; a second semiconductor layer, stacked on the first semiconductor layer, comprising a second n-type semiconductor region and a p-type semiconductor region; The second semiconductor layer has a groove, and the groove opens from a side of the second semiconductor layer opposite to the first semiconductor layer; a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer and forming an ohmic contact therewith; an anode electrode formed on a surface of the second semiconductor layer opposite to the first semiconductor layer and forming an ohmic contact therewith; a trench MOS gate, which is buried in the trench and wrapped by a gate insulating film, wherein the trench MOS gate and the second semiconductor layer are separated by the gate insulating film, and the trench MOS gate is in contact with the anode electrode; Features: the anode electrode being connected to the second n-type semiconductor region of the second semiconductor layer and the p-type semiconductor region of the second semiconductor layer respectively; The p-type semiconductor region of the second semiconductor layer connected to the anode electrode is not in contact with the gate insulating film, and the second n-type semiconductor region is provided between the p-type semiconductor region of the second semiconductor layer connected to the anode electrode and the gate insulating film; The trench MOS gate at least includes a metal material having a Schottky barrier with the second n-type semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film; The width of the second n-type semiconductor region of the second semiconductor layer connected to the anode electrode is in a range of 3 nm to 400 nm.
9. The semiconductor device according to claim 8, characterized in that The width of the second n-type semiconductor region of the second semiconductor layer is in a range of 3 nm to 200 nm.
10. A semiconductor element, the semiconductor element being a pn junction field effect transistor, the semiconductor element comprising: A first semiconductor layer including a first n-type semiconductor region; A second semiconductor layer, stacked on the first semiconductor layer, comprising a second n-type semiconductor region, a p-type semiconductor region and a high-resistance semiconductor region; Electrodes, including a drain electrode, a source electrode and a gate electrode; a gate insulating film disposed between the gate electrode and the second semiconductor layer; Features: The drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer; The source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, and the source electrode is connected to the second n-type semiconductor region of the second semiconductor layer and the p-type semiconductor region of the second semiconductor layer respectively; The p-type semiconductor region of the second semiconductor layer is not in contact with the gate insulating film, and the high-resistance semiconductor region is provided between the p-type semiconductor region of the second semiconductor layer and the gate insulating film; The gate electrode at least includes a metal material having a Schottky barrier with the high-resistance semiconductor region of the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.
11. The semiconductor device according to claim 10, characterized in that The materials of the first semiconductor layer and the second semiconductor layer are gallium oxide respectively, and the high-resistance semiconductor region is nitrogen-doped gallium oxide.
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Semiconductor element
CN118738084A