Transistor model and modeling method

Abstract

The invention belongs to the field of information communication, and particularly relates to a transistor model and a modeling method.The transistor model comprises a voltage-controlled switch and a nonlinear output resistor used for representing a GaN HEMT, an equivalent model is established for the transistor model in the two working states, the action of the voltage-controlled switch is controlled by an input driving level, and the nonlinear output resistor is used for representing the GaN HEMT. Component parameters of the transistor model are extracted according to direct current measurement and S parameter measurement under specific bias, the transistor model in the switching mode is equivalent to a circuit containing a voltage-controlled switch, and model simplification is achieved; a measurement system used for extracting the complete parameter set of the model is simple, the measurement speed is high, a large amount of data directly related to the transistor model design or process can be obtained, and the method can be applied to the design of an efficient radio frequency power amplifier.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic communications, and specifically relates to a transistor model and a modeling method, and in particular to a GaN high electron mobility transistor (HEMT) model and a modeling method suitable for a switching mode. Background Art

[0002] To ensure fast, accurate and successful circuit design, accurate active and passive models of each component are essential. As the operating frequency increases, parasitic effects become increasingly serious. Compared with the modeling of passive components, the modeling of active devices is more critical and more difficult to achieve. Active devices are very complex, and different applications require different degrees of abstraction of physical phenomena. Since there is no universal model that can accurately describe all the performance of active devices, many different active device models have been developed to date, such as small signal (linear) models, large signal (nonlinear) models, noise models and thermal models, and they are used to predict various characteristics of active devices.

[0003] Developing a new device and obtaining an accurate large-signal model of the device is a long and difficult process, which not only troubles manufacturers but also circuit designers, who need accurate component models to successfully analyze and design circuits in a short period of time without lengthy manual adjustments. Since it takes a lot of time to develop accurate and robust nonlinear models, there is little research on this topic. A typical example is GaN HEMT, which has been available for a long time, but it is still difficult to find a good nonlinear model for commercially available devices. Existing nonlinear models are all described by analytical nonlinear functions, resulting in high model complexity, difficulty in development, low robustness, poor versatility in different application environments, and accuracy is usually limited to Class A and Class AB operating modes, and it is impossible to accurately predict its characteristics in Class B and Class C operating modes.

[0004] In addition, in the new trend of modern wireless communication applications, GaN HEMTs mostly work in a more efficient switching mode, in which GaN HEMTs only work in two discrete states: low resistance on and high impedance off. It is obviously unnecessary to use traditional nonlinear functions to describe its complete working state, and this method is not conducive to obtaining data directly related to the design or process of GaN HEMTs. In fact, for GaN HEMTs in switching mode, if the equivalent switch switching speed is fast enough, or the operating frequency is much lower than the maximum oscillation frequency of the device, the transition time between the two discrete states is very short, and it is only necessary to describe the GaN HEMT characteristics in the cutoff region and the saturation region. Therefore, the complexity and development difficulty of this switching model will be significantly reduced compared with the traditional large signal model. Summary of the invention

[0005] In view of at least one of the above disadvantages, an object of the present invention is to provide a GaN HEMT model and modeling method suitable for switching mode, so as to solve the problem of long modeling time and complex model of GaN HEMT in switching mode in the prior art.

[0006] A transistor model includes an intrinsic part, wherein the intrinsic part includes an input resistor R connected in sequence to form a loop. i and input capacitor C gs , feedback capacitor C gd , a voltage-controlled switch, wherein the voltage-controlled switch is connected in parallel with an output capacitor C ds ; The input resistance R i and output capacitor C ds The connection point of is connected to the S pole of the transistor through the first external part; the input capacitor C gs and feedback capacitor C gd The connection point of is connected to the G pole of the transistor through the second external part; the feedback capacitor C gd and output capacitor C ds The connection point is connected to the D pole of the transistor through the third extrinsic part.

[0007] The first extrinsic part includes a source contact resistor R s , source distributed inductance L s .

[0008] The second extrinsic part includes the gate distributed inductance L g , Gate contact resistance R g , gate pad capacitance C pg , the input capacitor C gs With the feedback capacitor C gd The connection of the gate contact resistor R g and gate distributed inductance L g After connecting the G pole of the transistor, the gate contact resistance R g and gate distributed inductance L g The connection is through the gate pad capacitor C pg Ground.

[0009] The third extrinsic part includes the drain contact resistance R d , Drain distributed inductance L d , Drain pad capacitance C pd , the feedback capacitor C gd and the output capacitor C ds The connection of the drain contact resistance R d , Drain distributed inductance L d After connecting the D electrode of the transistor, the drain contact resistance R d , Drain distributed inductance Ld The connection is through the drain pad capacitor C pd Ground.

[0010] definition:

[0011] The transistor model is a GaN HEMT.

[0012] The first external feature part, the second external feature part, and the third external feature part form an external feature part;

[0013] A voltage-controlled switch to represent the nonlinear output resistance of the transistor model;

[0014] Parasitic capacitance, used to represent the input capacitance C of the GaN HEMT gs , output capacitor C ds , feedback capacitor C gd , gate pad capacitance C pg and drain pad capacitance C pd ;

[0015] Parasitic inductance is used to represent the distributed inductance of GaN HEMT at the source, gate and drain, that is, the gate distributed inductance L g , Drain distributed inductance L d , source distributed inductance L s ;

[0016] Contact resistance, which is used to represent the contact resistance of GaN HEMT at the source, gate and drain, that is, the drain contact resistance R d , Gate contact resistance R g , Source contact resistance R s ;

[0017] The intrinsic part includes: an input capacitor, a feedback capacitor and an output capacitor; the remaining components except the components of the intrinsic part are the extrinsic part.

[0018] Parasitic capacitance, parasitic inductance and contact resistance are divided into two categories: intrinsic part and extrinsic part. The parameter value of the intrinsic part is a function of the bias condition, while the parameter value of the extrinsic part is independent of the bias condition.

[0019] A modeling method forms an equivalent circuit based on a transistor model. When the extrinsic elements are known, the S parameter matrix of the GaN HEMT is measured and then transformed into the admittance matrix of the intrinsic element, thereby extracting the parameters of each component of the intrinsic part.

[0020] The inductance parameters in the extrinsic part are extracted using the impedance matrix of the GaN HEMT under the conditions of forward gate bias voltage and zero drain bias voltage.

[0021] The resistance parameters in the extrinsic part are extracted under the conditions of forward gate bias voltage and zero drain bias voltage by using the impedance matrix of the GaN HEMT and the volt-ampere characteristics of the GaN HEMT in two working states.

[0022] Each capacitance parameter in the extrinsic part is extracted using the admittance matrix of the GaN HEMT under the condition that the drain bias voltage is zero and the gate voltage is lower than the pinch-off voltage.

[0023] Compared with the prior art, the technical solution has the following advantages: the present invention can obtain a complete parameter set of the GaN HEMT model by using DC measurement and S parameter measurement, avoiding solving the nonlinear equations used in the traditional method; since the measuring instrument used is simple and the measuring speed is fast, the correction speed of the model parameters under different environments can be effectively improved, and the environmental adaptability of the model can be enhanced; in the process of extracting the model parameter set, a large amount of data directly related to the design or process of the GaN HEMT can also be obtained, providing a powerful tool for the design, analysis and optimization of the switch mode circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of an equivalent model of a GaN HEMT in a switching mode according to the present invention;

[0025] Figure 2 V ds =0 when the gate channel of the transistor;

[0026] Figure 3 is the equivalent circuit of the transistor when the drain bias voltage is zero and the gate voltage is lower than the pinch-off voltage; DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the present invention, and thus to more clearly define the scope of the present invention, the present invention is described in detail with respect to some specific embodiments of the present invention. It should be noted that the following are only some specific implementation methods of the present invention, which are only part of the embodiments of the present invention, wherein the specific and direct description of the relevant structure is only for the convenience of understanding the present invention, and each specific feature does not naturally and directly limit the scope of implementation of the present invention. The conventional selection and replacement made by those skilled in the art under the guidance of the present invention should be regarded as within the scope of the present invention.

[0028] A transistor model includes an intrinsic part, wherein the intrinsic part includes an input resistor R connected in sequence to form a loop. i and input capacitor C gs , feedback capacitor C gd , a voltage-controlled switch, wherein the voltage-controlled switch is connected in parallel with an output capacitor C ds ; The input resistance Ri and output capacitor C ds The connection point of is connected to the S pole of the transistor through the first external part; the input capacitor C gs and feedback capacitor C gd The connection point of is connected to the G pole of the transistor through the second external part; the feedback capacitor C gd and output capacitor C ds The connection point is connected to the D pole of the transistor through the third extrinsic part.

[0029] The first extrinsic part includes a source contact resistor R s , source distributed inductance L s .

[0030] The second extrinsic part includes the gate distributed inductance L g , Gate contact resistance R g , gate pad capacitance C pg , the input capacitor C gs With the feedback capacitor C gd The connection of the gate contact resistor R g and gate distributed inductance L g After connecting the G pole of the transistor, the gate contact resistance R g and gate distributed inductance L g The connection is through the gate pad capacitor C pg Ground.

[0031] The third extrinsic part includes the drain contact resistance R d , Drain distributed inductance L d , Drain pad capacitance C pd , the feedback capacitor C gd and the output capacitor C ds The connection of the drain contact resistance R d , Drain distributed inductance L d After connecting the D electrode of the transistor, the drain contact resistance R d , Drain distributed inductance L d The connection is through the drain pad capacitor C pd Ground.

[0032] definition:

[0033] The transistor model is a GaN HEMT.

[0034] The first external feature part, the second external feature part, and the third external feature part form an external feature part;

[0035] A voltage-controlled switch to represent the nonlinear output resistance of the transistor model;

[0036] Parasitic capacitance, used to represent the input capacitance C of the GaN HEMT gs , output capacitor C ds , feedback capacitor C gd , gate pad capacitance C pg and drain pad capacitance C pd ;

[0037] Parasitic inductance is used to represent the distributed inductance of GaN HEMT at the source, gate and drain, that is, the gate distributed inductance L g , Drain distributed inductance L d , source distributed inductance L s ;

[0038] Contact resistance, which is used to represent the contact resistance of GaN HEMT at the source, gate and drain, that is, the drain contact resistance R d , Gate contact resistance R g , Source contact resistance R s ;

[0039] The intrinsic part includes: an input capacitor, a feedback capacitor and an output capacitor; the remaining components except the components of the intrinsic part are the extrinsic part.

[0040] Parasitic capacitance, parasitic inductance and contact resistance are divided into two categories: intrinsic part and extrinsic part. The parameter value of the intrinsic part is a function of the bias condition, while the parameter value of the extrinsic part is independent of the bias condition.

[0041] A modeling method, based on the above transistor model, the parameter extraction method of the components of the intrinsic part is:

[0042] Step 1: When the parameter values ​​of the components of the extrinsic part are known, the S parameter matrix of the transistor model is measured;

[0043] Step 2: transforming the S parameter matrix in step 1 into an admittance matrix of components of the intrinsic part in the transistor model;

[0044] Step 3: Extract reference values ​​of components of the intrinsic part of the transistor model based on the admittance matrix described in step 2.

[0045] The method for transforming the S parameter matrix of GaN HEMT into the admittance matrix of intrinsic elements in step 2 is as follows (refer to the attached Figure 1 , assuming that the parameters of each component of the extrinsic part are known):

[0046] A1. Convert the measured S parameter matrix of the transistor model into an impedance parameter matrix and subtract L g and L d ;

[0047] A2. Convert the impedance parameter matrix in A1 to the admittance parameter matrix and subtract C gp and C gd ;

[0048] A3, convert the admittance parameter matrix in A2 into an impedance parameter matrix, and subtract R d , R g , R s and L s ;

[0049] A4. Convert the impedance parameter matrix in A3 into an admittance parameter matrix, which is the admittance matrix in step 2.

[0050] Parameters of the intrinsic components: The voltage-controlled switch represents the nonlinear output resistance R of the transistor switch ;

[0051] The components of the intrinsic part and the components of the extrinsic part are used to represent the parasitic parameters that affect the performance of the transistor model in the switching mode;

[0052] When the transistor model input drive level V in Exceeding a certain threshold V ON When the voltage-controlled switch is closed, the nonlinear output resistance R switch Equal to the on-resistance R on ; When the input drive level of the transistor model is V in Less than or equal to a specific threshold V OFF When the voltage-controlled switch is disconnected, the nonlinear output resistance R switch Equal to the cut-off resistance R off ;Right now,

[0053]

[0054] The input capacitance C of the intrinsic part gs , feedback capacitor C gd , output capacitor C ds Its operating frequency f varies with the voltage it is subjected to:

[0055]

[0056] Among them, R ds =R off Specific reactance k times larger, R ds =R on Specific reactance is 1 / k times smaller, so

[0057] When the transistor is in the off state (the voltage-controlled switch is off), the channel resistance can be equivalent to R off Cds Determine the output impedance and change the channel resistance to the inherent resistance effect in the channel;

[0058] When the transistor is in the on state (the voltage-controlled switch is closed), C ds Shunted by a low resistance path, R on Determine the output impedance;

[0059] Therefore, it is sufficient to obtain good accuracy by measuring the intrinsic element parameters when the transistor is in the off state and at the nominal drain supply voltage;

[0060] That is, the parameter values ​​of the components in each intrinsic part are extracted according to the S parameter matrix. For details, refer to the attached Figure 1 , each intrinsic part is in a Π topological structure, and its electrical characteristics are expressed by the admittance parameter:

[0061]

[0062] y 12 =-jwC gd (4)

[0063]

[0064] y 22 =g d +jw(C gs +C gd ) (6)

[0065] in, g m is the transconductance, g d is the gate-drain conductance, τ is the time constant, R i is the input resistance;

[0066] For a typical low noise circuit, The term is less than 0.01 at low frequencies (f<5GHz), and D is approximately 1. In addition, since the switching time is very short, wτ<<1, then:

[0067]

[0068] y 12 =-jwC gd (8)

[0069] y 21 =g m -jw(C gd +g m (R i C gs +τ)) (9)

[0070] y22 =g d +j w (C gs +C gd ) (10)

[0071] Expressions (6) to (9) show that: C gd Derived from y 12 , C gs and R i Derived from y 11 , g m Derived from y 21 , g d and C ds Derived from y 22 .

[0072] The method for extracting the various inductance parameters of the extrinsic part is: extracting them using the impedance matrix of the transistor model under the conditions of forward gate bias voltage and zero drain bias voltage; specifically:

[0073] L of the external part g , L d , L s The extraction method is as follows: extract the parasitic inductance parameters by suppressing the capacitance effect of the gate, and extract the impedance parameters of the transistor model according to the change of frequency under the conditions of positive gate bias voltage and zero drain bias voltage;

[0074] refer to Figure 2 , V ds = 0V, the gate channel of the transistor, at this time for any gate bias condition, the impedance parameter z ij for:

[0075] z 11 =R c / 3+z dy (11)

[0076] z 12 =z 21 =R c / 2 (12)

[0077] z 22 =R c (13)

[0078]

[0079] Among them, R c is the channel resistance under the gate, z dy is the equivalent impedance of the Schottky barrier, n is the ideal factor, k is the Boltzmann constant, T is the temperature, C g is the gate capacitance, I gis the DC gate current;

[0080] Although as the gate current increases, R dy Reduce C y Increase, but with R dy Relative to V gs The exponential change is dominant, and when the gate current density is close to 5×10 7 ~10 8 A / m 2 Time y R dy tends to zero, then:

[0081]

[0082] Therefore, the gate capacitance effect disappears, z 11 becomes a real number:

[0083]

[0084] In addition, due to the components of the external part C pg and C pd The influence of R s , R g , R d and L g , L s , L d The impedance parameters of the components of the extrinsic part are obtained by adding the impedance parameters of the components of the intrinsic part:

[0085]

[0086] z 12 =z 21 =R s +R c / 2+jwL s (18)

[0087] z 22 =R s +R d +R c +jw(L s +L d ) (19)

[0088] Expressions (16) to (18) show that the imaginary part of the impedance parameter of the components of the extrinsic part changes linearly with frequency. During the test, the S parameters of the transistor model are first measured using a network analyzer, and then the measured S parameters are converted into the impedance parameters of the components of the extrinsic part, and then the imaginary part of the impedance parameter of the components of the extrinsic part is plotted with respect to the frequency. Then: L s Derived from z 12The imaginary part, L g Derived from z 11 The imaginary part, L d Derived from z 22 The imaginary part of .

[0089] The method for extracting the various resistance parameters of the extrinsic part is: under the conditions of forward gate bias voltage and zero drain bias voltage, using the impedance matrix of the transistor model and the volt-ampere characteristics of the transistor model in two working states to extract, specifically:

[0090] R of the external part d , R g , R s The extraction method is: extract the contact resistance parameters according to the real part of the impedance parameters of the components of the transistor model in the on and off states and the extrinsic part;

[0091] The derivatives of the volt-ampere characteristic curve of the transistor model under test in the on and off states are R ON and R OFF ,

[0092] Then R OFF =R d +R s +R off , R ON =R d +R s +R on ;

[0093] According to formula (16), z 11 The real part of 1 / I g If the linear change is g +R s +R c / 3; According to equations (17) to (18), z 12 and z 22 The real part of R g , R s , R d and R c There are two relational expressions between them, so the contact resistance parameters can be extracted by combining the above equations.

[0094] The method for extracting the capacitance parameters of the extrinsic part is: extracting using the admittance matrix of the transistor model under the condition that the drain bias voltage is zero and the gate voltage is lower than the pinch-off voltage; specifically,

[0095] C of the external part pg , C pdThe extraction method is: extracting parameter values ​​by suppressing channel conductivity, extracting according to the change of the admittance parameter of the transistor model with frequency under the condition that the drain bias voltage is zero and the gate voltage is lower than the pinch-off voltage;

[0096] Figure 3 is the equivalent circuit of a transistor at zero drain bias and a gate voltage below the pinch-off voltage, where C b represents the fringe capacitance generated by the extension of the depletion layer on both sides of the gate. For frequencies up to several thousand MHz, the resistance and inductance of the extrinsic part do not affect the imaginary part of the admittance parameter. The admittance parameter of the extrinsic element can be written as:

[0097] Im(Y 11 )=jw(C pg +2C b ) (20)

[0098] Im(Y 12 )=Im(Y 21 )=-jwC b (twenty one)

[0099] Im(Y 22 )=jw(C pd +C b ) (twenty one)

[0100] Expressions (19) to (21) show that the imaginary part of the admittance parameter of the extrinsic element varies linearly with frequency. During the test, the S parameters of the transistor model are first measured using a network analyzer, and then the measured S parameters are converted into the admittance parameters of the extrinsic element. Then, the imaginary part of the admittance parameter of the extrinsic element is plotted with respect to the frequency. Then: C b Derived from Y 12 The imaginary part, C pg Derived from Y 11 The imaginary part, C pd Derived from Y 22 The imaginary part of .

[0101] The GaN HEMT model and modeling method applicable to the switch mode described in the present invention is a method of simulating the GaN HEMT as a circuit containing a voltage-controlled switch, and performing modeling for two quasi-static states of switch closing and switch opening.

[0102] All parameters in the transistor model can be directly determined without solving nonlinear equations, which can effectively improve modeling efficiency.

[0103] In practical applications, since the extraction of parameters in the model can be completed through DC measurement and S parameter measurement, a large amount of data directly related to the design or process of GaN HEMT can be obtained while establishing the model; since the parameter extraction method provided by the present invention is simple and fast, the model can be corrected in time according to the measurement results of the parasitic parameters in the current environment under different usage environments, thereby improving the environmental adaptability of the model.

[0104] The present invention has high industrial utilization value because it overcomes various shortcomings in the prior art.

[0105] The above implementation modes are only used to illustrate the present invention and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A transistor model, characterized in that: The intrinsic part includes an input resistor R connected in sequence to form a loop. i and input capacitor C gs , feedback capacitor C gd , a voltage-controlled switch, wherein the voltage-controlled switch is connected in parallel with an output capacitor C ds ; The input resistance R i and output capacitor C ds The connection point is connected to the S pole of the transistor through the first extrinsic part; The input capacitance C gs and feedback capacitor C gd The connection point is connected to the G pole of the transistor through the second extrinsic part; The feedback capacitor C gd and output capacitor C ds The connection point is connected to the D pole of the transistor through the third extrinsic part.

2. The transistor model according to claim 1, characterized in that The first extrinsic part includes a source contact resistor R s , source distributed inductance L s .

3. The transistor model according to claim 1, characterized in that: The second extrinsic part includes the gate distributed inductance L g , Gate contact resistance R g , gate pad capacitance C pg , the input capacitor C gs With the feedback capacitor C gd The connection of the gate contact resistor R g and gate distributed inductance L g After connecting the G pole of the transistor, the gate contact resistance R g and gate distributed inductance L g The connection is through the gate pad capacitor C pg Ground.

4. The transistor model according to claim 1, characterized in that The third extrinsic part includes the drain contact resistance R d , Drain distributed inductance L d , Drain pad capacitance C pd , the feedback capacitor C gd and the output capacitor C ds The connection of the drain contact resistance R d , Drain distributed inductance L d After connecting the D electrode of the transistor, the drain contact resistance R d , Drain distributed inductance L d The connection is through the drain pad capacitor C pd Ground.

5. A modeling method, characterized in that: According to the transistor model according to any one of claims 1 to 4, the parameter extraction method of the components of the intrinsic part is: Step 1: When the parameter values ​​of the components of the extrinsic part are known, the S parameter matrix of the transistor model is measured; Step 2: transforming the S parameter matrix in step 1 into an admittance matrix of components of the intrinsic part in the transistor model; Step 3: Extract reference values ​​of components of the intrinsic part of the transistor model based on the admittance matrix described in step 2.

6. The modeling method according to claim 5, characterized in that: The method for step 2 is: A1. Convert the measured S parameter matrix of the transistor model into an impedance parameter matrix and subtract L g and L d ; A2. Convert the impedance parameter matrix in A1 to the admittance parameter matrix and subtract C gp and C gd ; A3, convert the admittance parameter matrix in A2 into an impedance parameter matrix, and subtract R d , R g , R s and L s ; A4. Convert the impedance parameter matrix in A3 into an admittance parameter matrix, which is the admittance matrix in step 2.

7. The modeling method according to claim 6, characterized in that: The voltage-controlled switch represents the nonlinear output resistance R of the transistor switch ; The components of the intrinsic part and the components of the extrinsic part are used to represent the parasitic parameters that affect the performance of the transistor model in the switching mode; When the transistor model input drive level V in Exceeding a certain threshold V ON When the voltage-controlled switch is closed, the nonlinear output resistance R switch Equal to the on-resistance R on ; When the input drive level of the transistor model is V in Less than or equal to a specific threshold V OFF When the voltage-controlled switch is disconnected, the nonlinear output resistance R switch Equal to the cut-off resistance R off ;Right now, The input capacitance C of the intrinsic part gs , feedback capacitor C gd , output capacitor C ds Its operating frequency f varies with the voltage it is subjected to: Among them, R ds =R off Specific reactance k times larger, R ds =R on Specific reactance is 1 / k times smaller, so When the transistor is in the off state (the voltage-controlled switch is off), the channel resistance can be equivalent to R off , C ds Determine the output impedance; When the transistor is in the on state (the voltage-controlled switch is closed), C ds Shunted by a low resistance path, R on Determine the output impedance; That is, the parameter values ​​of the components in each intrinsic part are extracted according to the S parameter matrix, and each intrinsic part is presented in a Π topological structure, and its electrical characteristics are expressed by the admittance parameter as follows: the 12 =-jwC gd (4) y 22 =g d +jw(C gs +C gd ) (6) in, g m is the transconductance, g d is the gate-drain conductance, τ is the time constant, R i is the input resistance; The term is less than 0.01 at low frequencies (f<5GHz), and D is approximately 1. In addition, since the switching time is very short, wτ<<1, then: the 12 =-jwC gd (8) y 21 =g m -jw(C gd +g m (R i C gs +τ)) (9) y 22 =g d +jw(C gs +C gd ) (10) Expressions (6) to (9) show that: C gd Derived from y 12 , C gs and R i Derived from y 11 , g m Derived from y 21 , g d and C ds Derived from y 22 .

8. The modeling method according to claim 5, characterized in that: The method for extracting various inductance parameters of the extrinsic part is: under the conditions of forward gate bias voltage and zero drain bias voltage, the impedance matrix of the transistor model is used for extraction.

9. The modeling method according to claim 8, characterized in that: L of the external part g , L d , L s The extraction method is as follows: extract the parasitic inductance parameters by suppressing the capacitance effect of the gate, and extract the impedance parameters of the transistor model according to the change of frequency under the conditions of positive gate bias voltage and zero drain bias voltage; V ds = 0V, the gate channel of the transistor, at this time for any gate bias condition, the impedance parameter z ij for: z 11 =R c / 3+z dy (11) z 12 =z 21 =R c / 2 (12) z 22 =R c (13) Among them, R c is the channel resistance under the gate, z dy is the equivalent impedance of the Schottky barrier, n is the ideal factor, k is the Boltzmann constant, T is the temperature, C g is the gate capacitance, I g is the DC gate current; Although as the gate current increases, R dy Reduce C y Increase, but with R dy Relative to V gs The exponential change is dominant, and when the gate current density is close to 5×10 7 ~10 8 A / m 2 Time y R dy tends to zero, then: Therefore, the gate capacitance effect disappears, z 11 becomes a real number: In addition, due to the components of the external part C pg and C pd The influence of R s , R g , R d and L g , L s , L d The impedance parameters of the components of the extrinsic part are obtained by adding the impedance parameters of the components of the intrinsic part: With 12 =from 21 =R s +R c / 2+jwL s (18) z 22 =R s +R d +R c +jw(L s +L d ) (19) Expressions (16) to (18) show that the imaginary part of the impedance parameter of the components of the extrinsic part changes linearly with frequency. During the test, the S parameters of the transistor model are first measured using a network analyzer, and then the measured S parameters are converted into the impedance parameters of the components of the extrinsic part, and then the imaginary part of the impedance parameter of the components of the extrinsic part is plotted with respect to the frequency. Then: L s Derived from z 12 The imaginary part, L g Derived from z 11 The imaginary part, L d Derived from z 22 The imaginary part of .

10. The modeling method according to claim 5, characterized in that: The method for extracting various resistance parameters of the extrinsic part is: under the conditions of forward gate bias voltage and zero drain bias voltage, using the impedance matrix of the transistor model and the volt-ampere characteristics of the transistor model in two working states to extract.

11. The modeling method according to claim 10, characterized in that: R of the external part d , R g , R s The extraction method is: extract the contact resistance parameters according to the real part of the impedance parameters of the components of the transistor model in the on and off states and the extrinsic part; The derivatives of the volt-ampere characteristic curve of the transistor model under test in the on and off states are R ON and R OFF , Then R OFF = R d + R s + R off , R ON = R d + R s + R on ; According to formula (16), z 11 The real part of 1 / I g If the linear change is g +R s +R c / 3; According to equations (17) to (18), z 12 and z 22 The real part of R g , R s , R d and R c There are two relational expressions between them, so the contact resistance parameters can be extracted by combining the above equations.

12. The modeling method according to claim 5, characterized in that: The method for extracting the capacitance parameters of the extrinsic part is: extracting them using the admittance matrix of the transistor model under the condition that the drain bias voltage is zero and the gate voltage is lower than the pinch-off voltage.

13. The modeling method according to claim 12, characterized in that: C of the external part pg , C pd The extraction method is: extracting parameter values ​​by suppressing channel conductivity, extracting according to the change of the admittance parameter of the transistor model with frequency under the condition that the drain bias voltage is zero and the gate voltage is lower than the pinch-off voltage; The equivalent circuit of the transistor at zero drain bias and a gate voltage below the pinch-off voltage, where C b represents the fringe capacitance generated by the extension of the depletion layer on both sides of the gate. For frequencies up to several thousand MHz, the resistance and inductance of the extrinsic part do not affect the imaginary part of the admittance parameter. The admittance parameter of the extrinsic element can be written as: Im(Y 11 )=jw(C pg +2C b ) (20) Im(Y 12 )=Im(Y 21 )=-jwC b (21) In(Y 22 )=jw(C pd +C b ) (21) Expressions (19) to (21) show that the imaginary part of the admittance parameter of the extrinsic element varies linearly with frequency. During the test, the S parameters of the transistor model are first measured using a network analyzer, and then the measured S parameters are converted into the admittance parameters of the extrinsic element. Then, the imaginary part of the admittance parameter of the extrinsic element is plotted with respect to the frequency. Then: C b Derived from Y 12 The imaginary part, C pg Derived from Y 11 The imaginary part, C pd Derived from Y 22 The imaginary part of .

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