Time measurement circuit and time measurement method

Abstract

The invention discloses a time measuring circuit and a time measuring method. The time measuring circuit comprises an oscillation module which is used for generating an oscillation signal in a first level duration of a signal to be measured; the time delay module is electrically connected with the oscillation module and is used for controlling the period of the oscillation signal; the counting module is electrically connected with the oscillation module and is used for measuring the number of rising edges of the oscillation signal; the frequency measurement module is electrically connected with the oscillation module and is used for measuring the frequency of the oscillation signal; the control module is electrically connected with the time delay module, the frequency measurement module and the counting module and used for controlling the time delay value of the time delay module so that the first level duration time of the signal to be measured can be integer multiples of the oscillation signal period; and the duration of the first level of the signal to be measured is calculated according to the count value of the counting module and the frequency of the oscillation signal. According to the invention, the time measurement precision can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of time measurement, and in particular to a time measurement circuit and a time measurement method. Background Art

[0002] As modern electronic technology places increasingly higher demands on precision, the time measurement of various signals in electronic technology becomes particularly important. For example, in digital circuits, the requirements for time measurement are becoming increasingly higher, and high-precision time measurement technology plays a very important role in the chip and semiconductor industries. Among them, time measurement refers to measuring the pulse width, rising edge time, falling edge time or duty cycle of the signal.

[0003] In the related art, a Vernier (vernier) delay line solution or a tap delay line solution can be used. For FPGA (Field Programmable Gate Array), a phase-locked loop, a cascade chain or a carry chain are often used for measurement. However, the above solutions occupy more FPGA resources and the measurement error is also large. Summary of the invention

[0004] The invention provides a time measurement circuit and a time measurement method, so as to improve the accuracy of time measurement.

[0005] According to one aspect of the present invention, there is provided a time measurement circuit, comprising:

[0006] An oscillation module, wherein a periodic signal to be tested is input into one input end of the oscillation module, and the oscillation module is used to generate an oscillation signal within a first level duration of the signal to be tested, and output a second level within a second level duration of the signal to be tested; wherein the first level and the second level are different in level;

[0007] A delay module, the delay module is electrically connected to the oscillation module and is used to control the period of the oscillation signal;

[0008] A counting module, electrically connected to the oscillation module, and used to measure the number of rising edges of the oscillation signal within the first level duration of the signal to be measured;

[0009] A frequency measuring module, electrically connected to the oscillation module, and used to measure the frequency of the oscillation signal;

[0010] A control module is electrically connected to the delay module, the frequency measuring module and the counting module, and is used to control the delay value of the delay module so that the duration of the first level of the signal to be measured is an integer multiple of the period of the oscillation signal; and calculate the duration of the first level of the signal to be measured according to the count value of the counting module and the frequency of the oscillation signal.

[0011] Optionally, the control module is used to store the initial count value of the counting module; increase the delay value of the delay module, and when the count value of the counting module decreases compared to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period;

[0012] Alternatively, the control module is used to store the initial count value of the counting module; reduce the delay value of the delay module, and when the count value of the counting module increases compared to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period;

[0013] Alternatively, the control module is used to store the initial count value of the counting module; increase the delay value of the delay module so that the count value of the counting module decreases compared to the initial count value; and then reduce the delay value of the delay module, and when the count value of the counting module is equal to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period;

[0014] Alternatively, the control module is used to store the initial count value of the counting module; reduce the delay value of the delay module so that the count value of the counting module increases compared to the initial count value; and then increase the delay value of the delay module. When the count value of the counting module is equal to the initial count value, the delay value is fixed so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period.

[0015] Optionally, the oscillation module includes: a first logic function module, a first inverter, a second inverter, a third inverter, a fourth inverter, a first D flip-flop and a second D flip-flop; the delay module includes a first delay unit and a second delay unit;

[0016] The first input terminal of the first logic function module is connected to the signal to be tested, and the first logic function module is used to output the first level if the level polarities of the second input terminal and the third input terminal are the same when the first level is input to the first input terminal; and output the second level if the level polarities of the second input terminal and the third input terminal are different; wherein the first level and the second level are different in level; and the first logic function module is also used to output the second level when the second level is input to the first input terminal;

[0017] The output end of the first logic function module is electrically connected to the input end of the first delay unit and the input end of the second delay unit; the output end of the first logic function module serves as the output end of the oscillation module;

[0018] The output end of the first delay unit is electrically connected to the clock end of the first D flip-flop, the Q end of the first D flip-flop is electrically connected to the D end of the first D flip-flop through a first inverter, and the Q end of the first D flip-flop is electrically connected to the second input end of the first logic function module;

[0019] The output end of the second delay unit is electrically connected to the clock end of the second D flip-flop through the second inverter; the Q end of the second D flip-flop is electrically connected to the D end of the second D flip-flop through the third inverter, and the Q end of the second D flip-flop is electrically connected to the third input end of the first logic function module;

[0020] The first input terminal of the first logic function module is electrically connected to the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop through the fourth inverter.

[0021] Optionally, the oscillation module includes a second logic function module, and the delay module includes a third delay unit;

[0022] The first input end of the second logic function module is connected to the signal to be tested, the output end of the second logic function module serves as the output end of the oscillation module, the output end of the second logic function module is electrically connected to the input end of the third delay unit, and the output end of the third delay unit is electrically connected to the second input end of the second logic function module; the second logic function module is used to invert the input signal of its second input end and output it from its output end when the first input end thereof inputs a first level; and output the second level from its output end when the first input end thereof inputs a second level; wherein the first level and the second level are different in level.

[0023] Optionally, the time measurement circuit is implemented based on FPGA, and the delay module includes at least one of the following: an input-output delay device IODELAY, a dedicated delay chip, and a delay circuit constructed by a DAC and a comparator.

[0024] Optionally, the logic function module includes a lookup table.

[0025] According to another aspect of the present invention, a time measurement method is provided, which is performed by the above-mentioned time measurement circuit, and is characterized in that the time measurement method includes:

[0026] In the initial stage, within the duration of the first level of each period of the signal to be measured, the number of periods of the oscillation signal is measured to obtain an initial count value;

[0027] In the adjustment stage, the delay value of the delay module is adjusted, and when the count value of the counting module changes compared with the initial count value, the delay value is fixed;

[0028] In the measurement phase, the frequency of the oscillation signal is measured; and the duration of the first level of the signal to be measured is determined according to the frequency of the oscillation signal and the count value of the counting module.

[0029] Optionally, in the initial stage, within the first level duration of each cycle of the signal to be measured, measuring the number of cycles of the oscillation signal to obtain an initial count value includes:

[0030] In N cycles of the signal to be tested, if the count values ​​of the oscillation signal are all equal during the first level duration of each cycle, the count value of the oscillation signal is used as the initial count value; wherein N≥2.

[0031] Optionally, in the adjustment stage, adjusting the delay value of the delay module, when the count value of the counting module changes compared to the initial count value, fixing the delay value includes:

[0032] In a plurality of cycles of the signal to be tested, the delay value of the delay module is increased sequentially, and when the count value of the counting module decreases compared to the initial count value, the delay value is fixed;

[0033] Alternatively, within a plurality of cycles of the signal to be tested, the delay value of the delay module is reduced in sequence, and when the count value of the counting module increases compared to the initial count value, the delay value is fixed;

[0034] Alternatively, within a plurality of cycles of the signal to be tested, the delay value of the delay module is increased so that the count value of the counting module decreases compared to the initial count value; the delay value of the delay module is then decreased, and when the count value of the counting module is equal to the initial count value again, the delay value is fixed;

[0035] Alternatively, within multiple cycles of the signal to be tested, the delay value of the delay module is reduced so that the count value of the counting module increases compared to the initial count value; then the delay value of the delay module is increased, and when the count value of the counting module is equal to the initial count value again, the delay value is fixed.

[0036] Optionally, in the measurement phase, measuring the frequency of the oscillation signal includes:

[0037] Control the oscillation module to output a fixed oscillation signal;

[0038] Measuring the frequency of the oscillation signal; and / or determining the duration of the first level of the signal to be measured according to the frequency of the oscillation signal and the count value of the counting module during the measurement phase includes:

[0039] Determining a period of the oscillation signal according to the frequency of the oscillation signal;

[0040] Determine the number of cycles of the oscillation signal within the duration of the first level of the signal to be tested according to the count value of the counting module;

[0041] The duration of the first level of the signal to be tested is obtained by multiplying the number of periods by the period of the oscillation signal.

[0042] The technical solution of the embodiment of the present invention adopts a time measurement circuit, including: an oscillation module, an input end of the oscillation module inputs a periodic signal to be measured, the oscillation module is used to generate an oscillation signal within the first level duration of the signal to be measured, and output a second level within the second level duration of the signal to be measured; wherein the first level and the second level are different in height; a delay module, the delay module is electrically connected to the oscillation module, and is used to control the period of the oscillation signal; a counting module, which is electrically connected to the oscillation module, and is used to measure the number of rising edges of the oscillation signal within the first level duration of the signal to be measured; a frequency measurement module, which is electrically connected to the oscillation module, and is used to measure the frequency of the oscillation signal; a control module, which is electrically connected to the delay module, the frequency measurement module and the counting module, and is used to control the delay value of the delay module, so that the first level duration of the signal to be measured is an integer multiple of the period of the oscillation signal; and the duration of the first level of the signal to be measured is calculated according to the count value of the counting module and the frequency of the oscillation signal. Using input and output delay devices as delay modules, compared with the solutions implemented by the phase-locked loop, cascade chain and carry chain used in the prior art, reduces the impact of nonlinear errors on measurement accuracy, avoids the uneven delay distribution of the delay chain, and avoids the situation where temperature and voltage changes affect the measurement results. The present application has high accuracy, resolution and environmental interference resistance. The period of the oscillation signal is adjusted by adjusting the delay value of the delay module. When the first level of the signal to be measured is an integer multiple of the period of the oscillation signal, the period of the oscillation signal and the number of periods of the oscillation signal corresponding to the first level can be obtained through the frequency measurement module and the counting module, and then the duration of the first level of the signal to be measured can be calculated.

[0043] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of the circuit structure of a time measurement circuit provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of the principle of a time measurement method provided by an embodiment of the present invention;

[0047] Figure 3 for Figure 1 Timing diagram of the oscillator module;

[0048] Figure 4 A schematic diagram of the circuit structure of another time measurement circuit provided by an embodiment of the present invention;

[0049] Figure 5 A schematic diagram of the circuit structure of another time measurement circuit provided by an embodiment of the present invention;

[0050] Figure 6 A logic circuit diagram of a first logic function module provided by an embodiment of the present invention;

[0051] Figure 7 A logic circuit diagram of a second logic function module provided by an embodiment of the present invention;

[0052] Figure 8 A flow chart of a time measurement method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] Figure 1 A schematic diagram of a circuit structure of a time measurement circuit provided by an embodiment of the present invention, Figure 2 A schematic diagram of a time measurement method provided by an embodiment of the present invention, referring to Figure 1 and Figure 2 The time measurement circuit includes: an oscillation module 11, a delay module 12, a counting module 13, a frequency measurement module 14 and a control module 70. The time measurement circuit can be implemented by one or a combination of FPGA, ASIC (Application Specific Integrated Circuit), small-scale digital circuit and analog circuit.

[0056] An input end of the oscillation module 11 inputs a periodic signal to be tested TMU_DIN, and the oscillation module 11 is used to generate an oscillation signal within the duration of a first level of the signal to be tested TMU_DIN, and output a second level within the duration of a second level of the signal to be tested TMU_DIN; wherein the first level and the second level are different in height; the delay module 12 is electrically connected to the oscillation module 11, and is used to control the period of the oscillation signal; wherein, when the time measurement circuit is implemented by FPGA, the delay module 12 includes an input and output delay device IODELAY; of course, the delay module 12 can also be implemented by an independent delay line circuit or a delay chip, etc., or by using an analog The control module 70 is electrically connected to the delay module 12, the frequency measuring module 14 and the counting module 13, and is used to control the delay value of the delay module 12 so that the first level duration of the signal to be measured TMU_DIN within one cycle is an integer multiple of the oscillation signal cycle; and the duration of the first level of the signal to be measured is calculated according to the count value of the counting module 13 and the frequency of the oscillation signal.

[0057] Specifically, Figure 2As shown, the signal to be measured TMU_DIN is also a signal whose time needs to be measured. More specifically, the signal to be measured TMU_DIN is a clock signal, which has periodicity and can also be understood as a periodic signal. In one cycle, it has two polarity levels, namely, a first level and a second level. The first level can be a high level, and the second level can be a low level; of course, the first level can also be a low level and the second level can be a high level. This embodiment takes the first level as a high level and the second level as a low level as an example. The time measurement of the signal to be measured TMU_DIN is to measure the duration of the high level in one cycle of the signal to be measured TMU_DIN.

[0058] The oscillation module 11 can generate an oscillation signal DO within the duration of the first level of the signal to be tested TMU_DIN. That is to say, when the signal to be tested TMU_DIN jumps to the first level, the oscillation module 11 starts to generate the oscillation signal DO; and when the signal to be tested TMU_DIN jumps to the second level, the oscillation module 11 outputs the second level. That is to say, the oscillation signal DO reflects the duration of the first level in the signal to be tested TMU_DIN, so the time of the signal to be tested TMU_DIN can be obtained by only obtaining the information of the oscillation signal DO.

[0059] There are various specific implementations of the oscillation module 11 , which will be exemplarily introduced in the following.

[0060] The frequency of the oscillation signal DO output by the oscillation module 11 is adjustable. The specific adjustment method is to control the delay value of the delay module 12 through the control module 70. When the delay value is different, the frequency of the oscillation signal DO is also different, and the frequency and the period are reciprocal to each other, so the period of the oscillation signal DO can be adjusted by adjusting the delay of the delay module 12. In addition, when the time measurement circuit is implemented using FPGA, the delay module 12 in this embodiment is implemented using the input and output delay device IODELAY inside the FPGA, and more preferably, it can be implemented using the input delay device IDELAY (the so-called input and output delay device IODELAY in this application includes one or more combinations of input delay device IDELAY, output delay device ODELAY, and input and output delay device IODELAY), and the input and output delay device IODELAY has higher accuracy and higher resolution than the delay implemented using the logic function module. After adjusting the delay of the input-output delay device IODELAY, that is, when the delay of IODELAY needs to be fixed for time measurement, the oscillation module can be controlled to output the oscillation signal all the time, and the frequency measurement module can be used to measure the frequency of the oscillation signal in real time to obtain the real-time period of the oscillation circuit, thereby reducing the impact of the environment on the delay accuracy and eliminating the measurement errors caused by temperature and voltage changes.

[0061] In this embodiment, the control module 70 adjusts the period of the oscillation signal DO. When the duration of the first level of the signal to be measured TMU_DIN is an integer multiple of the period of the oscillation signal DO, the oscillation signal can be counted by the counting module, and the frequency of the oscillation signal can be measured by the frequency measuring module after the counting is completed. Finally, the control module can determine the duration of the first level of the signal to be measured TMU_DIN according to the count value and period of the oscillation signal. Exemplarily, the control module 70 can adopt an MCU (Microcontroller Unit) or a CPU (Central Processing Unit) and the like.

[0062] Through the above analysis, it can be known that the period of the oscillation signal is adjusted by adjusting the delay value of the delay module. When the first level of the signal to be tested is an integer multiple of the period of the oscillation signal, the period of the oscillation signal and the number of periods of the oscillation signal corresponding to the first level can be obtained through the frequency measurement module and the counting module, and then the time of the first level of the signal to be tested can be calculated. In addition, the oscillation signal will have a period only during the duration of the first level of the signal to be tested. The oscillation signal has a strong correlation with the signal to be tested, and has a stronger anti-interference ability, which makes the test more accurate. In addition, the oscillation signal generated by the oscillation module has a strong correlation with the signal to be tested. The delay from the jump of the signal to be tested to the high level to the first rising edge of the oscillation signal is the inherent delay generated by the relevant unit in the oscillation module (which will be explained later), and the delay is a fixed value each time the signal to be tested is measured. When the signal to be tested jumps to a low level, the oscillation signal also jumps to a low level, and by continuously adjusting the delay value of the delay module, it can be made that when the signal to be tested jumps to a low level, the oscillation signal just has a rising edge pulse (see Figure 2 ), at this time, the delay of the rising edge pulse relative to the signal to be measured is also an inherent delay, which is equal to the fixed delay mentioned above. At this time, the high level length of the signal to be measured is an integer multiple of the oscillation signal period, and the two inherent delays cancel each other out.

[0063] The technical solution of this embodiment adopts a time measurement circuit, including: an oscillation module, an input end of which inputs a periodic signal to be measured, the oscillation module is used to generate an oscillation signal within the duration of a first level of the signal to be measured, and output a second level within the duration of a second level of the signal to be measured; wherein the first level and the second level are different in height; a delay module, the delay module is electrically connected to the oscillation module, and is used to control the period of the oscillation signal; wherein the delay module includes an input and output delay device; a counting module, which is electrically connected to the oscillation module, and is used to measure the number of rising edges of the oscillation signal within the duration of the first level of the signal to be measured; a frequency measuring module, which is electrically connected to the oscillation module, and is used to measure the frequency of the oscillation signal; a control module, which is electrically connected to the delay module, the frequency measuring module and the counting module, and is used to control the delay value of the delay module, so that the duration of the first level of the signal to be measured is an integer multiple of the period of the oscillation signal; and the duration of the first level of the signal to be measured is calculated according to the count value of the counting module and the frequency of the oscillation signal. The period of the oscillation signal is adjusted by adjusting the delay value of the delay module. When the first level of the signal to be measured is an integer multiple of the period of the oscillation signal, the period of the oscillation signal and the number of periods of the oscillation signal corresponding to the first level can be obtained through the frequency measurement module and the counting module. Then, the duration of the first level of the signal to be measured can be calculated. By real-time frequency measurement, the influence of environmental factors is reduced, and the measurement errors caused by temperature and voltage changes are reduced.

[0064] Optionally, the time measurement circuit is implemented by FPGA, and uses input and output delay devices as delay modules, which has higher accuracy, resolution and anti-environmental interference capabilities.

[0065] It should be noted that the time measurement circuits in this embodiment are all composed of modules inside the FPGA, which has the advantages of simple circuit structure and less occupation of FPGA resources.

[0066] Optionally, in some embodiments, the control module is used to store the initial count value of the counting module 13; increase the delay value of the delay module 12, and when the count value of the counting module 13 decreases compared to the initial count value, fix the delay value so that the first level duration of the signal to be tested TMU_DIN is an integer multiple of the period of the oscillation signal.

[0067] Specifically, the time measurement circuit measures the signal to be measured TMU_DIN within multiple cycles of the signal to be measured TMU_DIN. More specifically, the time measurement process can be divided into an initial stage, an adjustment stage, and a measurement stage. Each stage includes at least one cycle of the signal to be measured TMU_DIN, and the initial stage, the adjustment stage, and the measurement stage are performed in sequence.

[0068] In the initial stage, it is used to determine the initial count value of the oscillation signal. For example, in the first cycle of the signal to be measured TMU_DIN, the counting module 13 counts the rising edges of the oscillation signal DO, and the obtained count value is also the initial count value. Of course, in order to improve the measurement accuracy, the counting module 13 can be controlled by the control module 70, and the rising edges of the oscillation signal DO are counted by the counting module 13 in multiple consecutive cycles. If the count values ​​are all equal, the count value is used as the initial count value.

[0069] In the initial stage, in the oscillation signal corresponding to each cycle of the test signal TMU_DIN, the last cycle of the oscillation signal may not be complete, that is, the first level time of the test signal TMU_DIN in the initial state may not be an integer multiple of the cycle of the oscillation signal. Therefore, the oscillation signal obtained in the initial stage cannot be directly used to measure the time of the test signal TMU_DIN.

[0070] In the adjustment stage, it is used to adjust the period of the oscillation signal so that the time of the first level of the signal to be tested is an integer multiple of the period of the oscillation signal. The control module controls the delay value of the delay module 12. In this embodiment, the delay value of the delay module 12 is increased. For example, the delay value can be increased step by step, where step by step means increasing the step size of the delay module 12 each time, that is, in each period of the signal to be tested, the delay value of the delay module 12 increases by one compared to the previous period. When the delay value of the delay module 12 increases, the period of the oscillation signal becomes larger. Figure 2 As shown, the initial count value of the counting module 13 is, for example, 7. As the period of the oscillation signal gradually increases, when the count value of the counting module 13 is just reduced compared to the initial count value ( Figure 2 The 7th rising edge just disappears in the measurement), indicating that the period of the measured signal TMU_DIN is an integer multiple of the period of the oscillation signal DO. It can be understood that, in actual measurement, if the count value corresponding to the previous delay value is equal to the initial count value, and the count value corresponding to the current delay value is a decrease from the initial count value, the current delay value is fixed. In addition, a plurality of registers may be provided in the control module to store the above-mentioned initial count value, the value of the fixed delay value, etc. It should be noted that the count value corresponding to the current delay value may be minus one or minus n compared to the initial count value, where n>1 and n is an integer. In some embodiments, since the step size of the delay module is a digital quantity rather than a continuous analog quantity, when the step size is increased, the count value corresponding to the delay value decreases compared to the initial count value. At this time, the first level of the signal to be measured may not be exactly an integer multiple of the period of the oscillation signal corresponding to the delay value, but at this time, the first level of the signal to be measured is large enough compared to the period of the oscillation signal, and the relative error of the measurement result is already very small. Therefore, the error can be ignored at this time, that is, it can be considered that the first level of the signal to be measured is an integer multiple of the period of the oscillation signal corresponding to the delay value.

[0071] In the measurement phase, it is used to measure the frequency of the oscillation signal, which can also be understood as measuring the period of the oscillation signal. After the delay value of the delay module 12 is fixed in the adjustment phase. A signal of a constant first level can be input to the input end of the oscillation module 11 that inputs the signal to be measured TMU_DIN, and the oscillation module 11 continuously outputs the oscillation signal. The frequency measurement module 14 measures the frequency of the oscillation signal. For example, the 100MHz clock inside the FPGA can be used to time 1s, and the oscillation signal is counted within 1s. The count value obtained is the frequency of the oscillation signal, and the inverse is the period. After obtaining the period of the oscillation signal, the control module can obtain the time of the first level of the signal to be measured according to the count value of the counting module in the adjustment phase and the period of the oscillation signal. That is, the count value of the counting module is multiplied by the period of the oscillation signal to obtain the time of the first level of the signal to be measured.

[0072] Optionally, in some other embodiments, the control module is used to store the initial count value of the counting module; reduce the delay value of the delay module, and when the count value of the counting module increases compared to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period.

[0073] Specifically, the time test process in this embodiment is the same as that in the above embodiment, including an initial stage, an adjustment stage and a measurement stage. Different from the above embodiment, in this embodiment, the adjustment stage does not increase the delay value of the delay module step by step, but reduces the delay value of the delay module step by step, so that the period of the oscillation signal is reduced step by step. When the count value of the counting module 13 increases compared with the previous count value, the delay value is fixed.

[0074] Optionally, in some other embodiments, the control module is used to store the initial count value of the counting module; first increase the delay value of the delay module to reduce the count value of the counting module compared to the initial count value; then reduce the delay value of the delay module, and when the count value of the counting module is equal to the initial count value, fix the delay value so that the first level duration is an integer multiple of the oscillation signal period.

[0075] Specifically, different from the above implementation, in this embodiment, the delay value first increases and then decreases, and through two adjustments in different directions, it is ensured that the counting change of the counting module is due to the influence of different delay values ​​rather than the influence of other interferences, thereby ensuring measurement accuracy.

[0076] Optionally, in some other embodiments, the control module is used to store the initial count value of the counting module; first reduce the delay value of the delay module to increase the count value of the counting module compared to the initial count value; then increase the delay value of the delay module, and when the count value of the counting module is equal to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period.

[0077] Specifically, different from the above implementation, in this embodiment, the delay value is first reduced and then increased, and through two adjustments in different directions, it is ensured that the counting change of the counting module is due to the influence of different delay values ​​rather than the influence of other interferences, thereby ensuring measurement accuracy.

[0078] Optionally, refer to Figure 1 The oscillation module 11 includes: a first logic function module (logic function 1), a first inverter 111, a second inverter 112, a third inverter 113, a fourth inverter 114, a first D flip-flop DQ1 and a second D flip-flop DQ2; the delay module 12 includes a first delay unit IDL1 and a second delay unit IDL2; the first input end of the first logic function module (logic function 1) inputs the signal to be tested TMU_DIN. The first logic function module is used to output the first level when the first level is input to the first input terminal, if the level polarities of the second input terminal and the third input terminal are the same, and output the second level if the level polarities of the second input terminal and the third input terminal are different; wherein the first level and the second level are different in level; the first logic function module (logic function 1) is also used to output the second level when the second level is input to the first input terminal; the output terminal of the first logic function module (logic function 1) is electrically connected to the input terminal of the first delay unit IDL1 and the input terminal of the second delay unit IDL2; the output terminal of the first logic function module (logic function 1) serves as the output terminal of the oscillation module; the output terminal of the first delay unit IDL1 is electrically connected to the clock terminal CLK of the first D flip-flop DQ1 The Q end of the first D flip-flop DQ1 is electrically connected to the D end of the first D flip-flop DQ1 through the first inverter 111, and the Q end of the first D flip-flop DQ1 is electrically connected to the second input end of the first logic function module; the output end of the second delay unit IDL2 is electrically connected to the clock end CLK of the second D flip-flop DQ2 through the second inverter 112, the Q end of the second flip-flop DQ2 is electrically connected to the D end of the second D flip-flop DQ2 through the third inverter 113, and the Q end of the second D flip-flop DQ2 is electrically connected to the third input end of the first logic function module; the first input end of the first logic function module (logic function 1) is electrically connected to the reset end CLR of the first D flip-flop DQ1 and the reset end CLR of the second D flip-flop DQ2 through the fourth inverter 114. In some other embodiments, the first logic function module can also be replaced by a digital gate circuit (such as Figure 6The logic function module shown includes an XOR gate and an AND gate), or in the FPGA it can also be a first lookup table LUT3.

[0079] Specifically, Figure 3 for Figure 1 The timing diagram of the oscillation module in FIG. 1 is shown in FIG. 1 , wherein the output of the first delay unit IDL1 is the first delayed output signal D1, the output of the second delay unit IDL2 is the second delayed output signal D2, the output of the first D flip-flop DQ1 is the first trigger output signal DQ11, and the output of the second D flip-flop DQ2 is the second trigger output signal DQ21. Figure 3 The oscillation principle of the oscillation module 11 in this embodiment is: in the initial state, the test signal TMU_DIN, the oscillation signal D0, the first delayed output signal D1, the second delayed output signal D2, the first trigger output signal DQ11 and the second trigger output signal DQ21 are all low level.

[0080] When the signal to be tested TMU_DIN jumps to a high level, after the inherent delay of the first logic function module (logic function 1), the oscillation signal D0 output by the first logic function module (logic function 1) jumps to a high level (at this time, the first level is a high level). Wherein, T0 is the inherent delay of the first logic function module (logic function 1), that is, the inherent delay generated by the relevant units in the oscillation module mentioned above.

[0081] The delays of the first delay unit IDL1 and the second delay unit IDL2 can be the same or different. After the oscillation signal D0 is delayed by the first delay unit IDL1, the first delayed output signal D1 is at a high level. After the oscillation signal D0 is delayed by the second delay unit IDL2, the second delayed output signal D2 is at a high level. Wherein, T1 is the delay of the first delay unit IDL1.

[0082] Since the output of the first D flip-flop DQ1 is low level in the initial state, the D terminal is high level after passing through the first inverter 111. When the first delayed output signal D1 jumps to high level, the clock terminal CLK of the first D flip-flop DQ1 forms a rising edge. Therefore, after the inherent delay time T2 of the first D flip-flop DQ1, the first trigger output signal DQ11 of the first D flip-flop DQ1 jumps to high level. In this stage, since the second delayed output signal D2 is input to the clock terminal of the second D flip-flop DQ2 after passing through the second inverter 112, the clock terminal of the second D flip-flop DQ2 inputs a low level. The output of the second D flip-flop DQ2 remains at a low level.

[0083] At this time, the first trigger output signal DQ11 is at a high level, and the second trigger output signal DQ21 is at a low level. Since the signal to be tested TMU_DIN is at a high level, after the total delay T3 of the routing delay between the output of the first D flip-flop DQ1 and the input of the first logic function module (logic function 1) and the inherent delay of the first logic function module (logic function 1), the oscillation signal D0 jumps to a low level. Then, after the delay time T4 of the second delay unit IDL2 (the delay of the IDELAY2 primitive module), the second delay output signal D2 jumps to a low level, while the first trigger output signal DQ11 remains at a high level. Then, after the delay time T5 of the second D flip-flop DQ2, the second trigger output signal DQ21 flips to a high level. At this time, the first trigger output signal DQ11 is high, the second trigger output signal DQ21 is high, and the signal to be tested TMU_DIN is high. Therefore, after the total delay T6 of the routing delay between the output of the second D trigger DQ2 and the input of the first logic function module (logic function 1) and the inherent delay of the first logic function module (logic function 1), the oscillation signal D0 jumps to a high level. Thus, a complete cycle of the oscillation signal D0 is completed, and the subsequent generation principle of the oscillation signal D0 is the same as described above, which will not be repeated here. Among them, T1 can also be understood as the delay of the primitive module of the first delay unit, and T4 can also be understood as the delay of the primitive module of the second delay unit.

[0084] It should be noted that a period of the oscillation signal D0 is T=T1+T2+T3+T4+T5+T6, where T2, T3, T5, and T6 are all delays of the FPGA internal devices themselves or routing delays. After the FPGA compilation is completed, these delay values ​​are fixed. Only T1 and T4 can be dynamically configured. By dynamically configuring the values ​​of T1 and T4, the period of the oscillation signal D0 can be changed and adjusted.

[0085] In addition, in this embodiment, the test signal TMU_DIN is directly electrically connected to the reset terminals of the first D flip-flop DQ1 and the second D flip-flop DQ2 after passing through the fourth inverter 114. When the test signal TMU_DIN jumps to a low level, the first D flip-flop DQ1 and the second D flip-flop DQ2 jump to a low level after a very small delay.

[0086] like Figure 3 Te shown is the delay between the falling edge of the signal to be tested TMU_DIN and the output of the oscillation signal D0. This delay is the physical delay of the first logic function module (logic function 1) itself, and is equal to the inherent delay T0 of the first logic function module (logic function 1).

[0087] like Figure 3The Tf shown is the delay of the first delay unit IDL1 (that is, the physical delay configured by the IDELAY1 primitive module). After this delay, the first delayed output signal D1 is always 0.

[0088] Similarly, the second delayed output signal D2 is also 0 after the delay of the second delay unit IDL2 (that is, the physical delay of IDELAY2).

[0089] The signal to be tested TMU_DIN is inverted and input to the reset terminal of the trigger, that is, input to the reset terminal CLR of the first D trigger DQ1 and the reset terminal CLR of the second D trigger DQ2. Therefore, when the signal to be tested TMU_DIN is 0, the first trigger output signal DQ11 and the second trigger output signal DQ21 are both always 0.

[0090] At this time, D0, D1, D2, DQ11, and DQ21 are all 0 until the next time the signal to be tested TMU_DIN is pulled high, and then D0, D1, D2, DQ11, and DQ21 will restart the above process. Figure 4 As shown, Figure 4 A circuit structure diagram of another time measurement circuit provided by an embodiment of the present invention. The oscillation module 11 includes a second logic function module (logic function 2), and the delay module 12 includes a third delay unit IDL3; the first end of the second logic function module (logic function 2) is connected to the signal to be measured TMU_DIN, the output end of the second logic function module (logic function 2) is used as the output end of the oscillation module 11, the output end of the second logic function module (logic function 2) is electrically connected to the input end of the third delay unit IDL3, and the output end of the third delay unit IDL3 is electrically connected to the input end of the second logic function module (logic function 2); the second logic function module (logic function 2) is used to invert the input signal of its second input end and output it from its output end when the first level is input to its first input end; when the second level is input to its first input end, the second level is output from its output end; wherein the first level and the second level are different in height.

[0091] Specifically, in the initial state, the first input end of the second logic function module (logic function 2) is at the second level (i.e., low level), so its output end, i.e., the oscillation signal D0 is at a low level, and the output of the third delay unit IDL3, the third delayed output signal IDL3, is also at a low level. When the signal to be measured TMU_DIN jumps to a high level, after the inherent delay of the second logic function module (logic function 2), the oscillation signal D0 jumps to a high level, and after the delay of the third delay unit IDL3, the high level signal makes the second input end of the second logic function module (logic function 2) a high level. Subsequently, after the inherent delay of the second logic function module (logic function 2), the oscillation signal D0 jumps to a low level, and the oscillation is cyclically oscillated so that the oscillation signal D0 has a certain period. Among them, by adjusting the delay value of the third delay unit IDL3, the period of the oscillation signal D0 can be adjusted.

[0092] The second logic function module in the FPGA may also be replaced by a second lookup table LUT2 or a logic gate circuit, for example: Figure 7 The circuit shown includes a NOT gate and an AND gate.

[0093] like Figure 5 As shown, Figure 5 A schematic diagram of the circuit structure of another time measurement circuit provided by an embodiment of the present invention. Figure 4 The difference is that, in this embodiment, the delay module 12 includes a delay circuit constructed by a DAC and a comparator. The input signal of the comparator can be regarded as a linearly rising ramp (with a certain rise time). The DAC is connected to the control module 70. By changing the threshold of the comparator reversal through the DAC, different delays can be obtained. Of course, in other embodiments, the delay module 12 has a delay circuit constructed by a DAC and a comparator. Figure 4 and Figure 5 In addition to the implementation method, other methods can also be used. For example, a special delay chip can be used. The control module inputs a control digital quantity to the delay chip so that its input to output has a controlled delay, and different delays can be obtained from input to output.

[0094] The present invention also provides a time measurement method, which is performed by the time measurement circuit provided by any embodiment of the present invention. Figure 8 , Figure 8 A flow chart of a time measurement method provided by an embodiment of the present invention. The time measurement method includes:

[0095] Step S101, in the initial stage, within the first level duration of each cycle of the signal to be measured, the number of cycles of the oscillation signal is measured to obtain an initial count value;

[0096] Specifically, the initial stage is used to determine the initial count value of the oscillation signal. For example, in the first cycle of the signal to be tested TMU_DIN, the counting module 13 counts the rising edges of the oscillation signal DO, and the obtained count value is also the initial count value.

[0097] In the initial stage, in the oscillation signal corresponding to each cycle of the test signal TMU_DIN, the last cycle of the oscillation signal may not be complete, that is, the first level time of the test signal TMU_DIN in the initial state may not be an integer multiple of the oscillation signal cycle. Therefore, the oscillation signal obtained in the initial stage cannot be directly used to measure the time of the test signal TMU_DIN.

[0098] Step S102, in the adjustment stage, adjusting the delay value of the delay module, when the count value of the counting module changes compared to the initial count value, fixing the delay value;

[0099] Specifically, the adjustment stage is used to adjust the period of the oscillation signal so that the time of the first level of the signal to be tested is an integer multiple of the period of the oscillation signal. The control module 70 controls the delay value of the delay module 12. In this embodiment, the delay value of the delay module 12 is increased. For example, the delay value can be increased step by step, that is, in each period of the signal to be tested, the delay value of the delay module 12 increases by one compared with the previous period. When the delay value of the delay module 12 increases, the period of the oscillation signal becomes larger. Figure 2 As shown, the initial count value of the counting module 13 is, for example, 7. As the period of the oscillation signal gradually increases, when the count value of the counting module 13 is just reduced compared to the initial count value (such as Figure 2 The seventh rising edge just disappears), indicating that the period of the measured signal TMU_DIN is an integer multiple of the period of the oscillation signal DO. It can be understood that, in actual measurement, if the count value corresponding to the previous delay value is equal to the count initial value, and the count value corresponding to the current delay value is not equal to the count initial value, the current delay value is fixed. In addition, a plurality of registers may be provided in the control module to store the above-mentioned count initial value, the value of the fixed delay value, etc.

[0100] Step S103, in the measurement phase, the frequency of the oscillation signal is measured; and the duration of the first level of the signal to be measured is determined according to the frequency of the oscillation signal and the count value of the counting module.

[0101] Specifically, the measurement phase is used to measure the frequency of the oscillation signal, which can also be understood as measuring the period of the oscillation signal. After the delay value of the delay module 12 is fixed in the adjustment phase. A signal of a constant first level can be input to the input end of the oscillation module 11 that inputs the signal to be measured TMU_DIN, and the oscillation module 11 continuously outputs the oscillation signal. The frequency measurement module 14 measures the frequency of the oscillation signal. For example, the 100MHz clock inside the FPGA can be used to time 1s, and the oscillation signal is counted within 1s. The count value obtained is the frequency of the oscillation signal, and the inverse is the period. After obtaining the period of the oscillation signal, the control module can obtain the time of the first level of the signal to be measured according to the count value of the counting module in the adjustment phase and the period of the oscillation signal. That is, the count value of the counting module is multiplied by the period of the oscillation signal to obtain the time of the first level of the signal to be measured.

[0102] The technical solution of this embodiment adopts a time measurement method that uses an input and output delay device as a delay module, which has high accuracy, resolution and environmental interference resistance.

[0103] Optionally, in the initial stage, within the first level duration of each cycle of the signal to be tested, the number of cycles of the oscillation signal is measured to obtain an initial counting value, including: within N cycles of the signal to be tested, if the counting values ​​of the oscillation signal are equal within the first level duration of each cycle, then the counting value of the oscillation signal is used as the initial counting value; wherein, N≥2.

[0104] Specifically, to improve the measurement accuracy, the control module may control the counting module 13 to count the rising edges of the oscillation signal DO in a plurality of consecutive cycles. If the count values ​​are all equal, the count values ​​are used as the initial count values.

[0105] Optionally, in the adjustment stage, the delay value of the delay module is adjusted, and when the count value of the counting module changes compared to the initial count value, the fixed delay value includes:

[0106] In multiple cycles of the signal to be tested, the delay value of the delay module is increased in sequence, and when the count value of the counting module decreases compared to the initial count value, the delay value is fixed;

[0107] Alternatively, within multiple cycles of the signal to be measured, the delay value of the delay module is reduced in sequence, and when the count value of the counting module increases compared to the initial count value, the delay value is fixed;

[0108] Alternatively, within multiple cycles of the signal to be measured, the delay value of the delay module is increased so that the count value of the counting module decreases compared to the initial count value; then the delay value of the delay module is decreased, and when the count value of the counting module is equal to the initial count value again, the delay value is fixed;

[0109] Alternatively, within multiple cycles of the signal to be tested, the delay value of the delay module is reduced to increase the count value of the counting module compared to the initial count value; then the delay value of the delay module is increased, and when the count value of the counting module is equal to the initial count value again, the delay value is fixed.

[0110] Specifically, the method for adjusting the delay value of the delay module in this embodiment can refer to the description of the time measurement circuit part of the present invention, which will not be repeated here.

[0111] Optionally, in the measurement phase, measuring the frequency of the oscillation signal includes:

[0112] Control the oscillation module to output a fixed oscillation signal;

[0113] Specifically, the control module 70 can input a signal of a constant first level to the input end of the oscillation module 11 that inputs the test signal TMU_DIN, and the oscillation module 11 continuously outputs the oscillation signal. Of course, other modules can also control the input end of the oscillation module 11 that inputs the test signal TMU_DIN to input a signal of a constant first level.

[0114] Measure the frequency of the oscillation signal;

[0115] Specifically, the frequency measuring module 14 is used to measure the frequency of the oscillation signal. For example, the 100 MHz clock inside the FPGA can be used to time 1 second, and the oscillation signal can be counted within 1 second. The count value obtained is the frequency of the oscillation signal, and the inverse is the period.

[0116] It should be noted that, in some other implementations, the frequency measuring module may also directly measure the frequency of the oscillation signal when the oscillation module inputs the signal to be measured, without controlling the oscillation module to fixedly output the oscillation signal.

[0117] Optionally, in the measurement phase, determining the duration of the first level of the signal to be measured according to the frequency of the oscillation signal and the count value of the counting module includes:

[0118] Determine the period of the oscillation signal according to the frequency of the oscillation signal;

[0119] Determine the number of cycles of the oscillation signal within the duration of the first level of the signal to be measured according to the count value of the counting module;

[0120] The duration of the first level of the signal to be measured is obtained by multiplying the number of periods by the period of the oscillation signal.

[0121] Specifically, after obtaining the period of the oscillation signal, the control module can obtain the time of the first level of the signal to be measured according to the count value of the counting module in the adjustment phase and the period of the oscillation signal. That is, the time of the first level of the signal to be measured can be obtained by multiplying the count value of the counting module by the period of the oscillation signal.

[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0123] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A time measurement circuit, characterized in that: include: An oscillation module, wherein a periodic signal to be tested is input into one input end of the oscillation module, and the oscillation module is used to generate an oscillation signal within a first level duration of the signal to be tested, and output a second level within a second level duration of the signal to be tested; wherein the first level and the second level are different in level; A delay module, the delay module is electrically connected to the oscillation module and is used to control the period of the oscillation signal; A counting module, electrically connected to the oscillation module, and used to measure the number of rising edges of the oscillation signal within the first level duration of the signal to be measured; A frequency measuring module, electrically connected to the oscillation module, and used to measure the frequency of the oscillation signal; A control module is electrically connected to the delay module, the frequency measuring module and the counting module, and is used to control the delay value of the delay module so that the duration of the first level of the signal to be measured is an integer multiple of the period of the oscillation signal; and calculate the duration of the first level of the signal to be measured according to the count value of the counting module and the frequency of the oscillation signal.

2. The time measurement circuit according to claim 1, characterized in that: The control module is used to store the initial count value of the counting module; increase the delay value of the delay module, and when the count value of the counting module decreases compared to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period; Alternatively, the control module is used to store the initial count value of the counting module; reduce the delay value of the delay module, and when the count value of the counting module increases compared to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period; Alternatively, the control module is used to store the initial count value of the counting module; increase the delay value of the delay module so that the count value of the counting module decreases compared to the initial count value; and then reduce the delay value of the delay module, and when the count value of the counting module is equal to the initial count value, fix the delay value so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period; Alternatively, the control module is used to store the initial count value of the counting module; reduce the delay value of the delay module so that the count value of the counting module increases compared to the initial count value; and then increase the delay value of the delay module. When the count value of the counting module is equal to the initial count value, the delay value is fixed so that the first level duration of the signal to be tested is an integer multiple of the oscillation signal period.

3. The time measurement circuit according to claim 1, characterized in that: The oscillation module includes: a first logic function module, a first inverter, a second inverter, a third inverter, a fourth inverter, a first D flip-flop and a second D flip-flop; the delay module includes a first delay unit and a second delay unit; The first input terminal of the first logic function module is connected to the signal to be tested, and the first logic function module is used to output the first level if the level polarities of the second input terminal and the third input terminal are the same when the first level is input to the first input terminal; and output the second level if the level polarities of the second input terminal and the third input terminal are different; wherein the first level and the second level are different in level; and the first logic function module is also used to output the second level when the second level is input to the first input terminal; The output end of the first logic function module is electrically connected to the input end of the first delay unit and the input end of the second delay unit; the output end of the first logic function module serves as the output end of the oscillation module; The output end of the first delay unit is electrically connected to the clock end of the first D flip-flop, the Q end of the first D flip-flop is electrically connected to the D end of the first D flip-flop through a first inverter, and the Q end of the first D flip-flop is electrically connected to the second input end of the first logic function module; The output end of the second delay unit is electrically connected to the clock end of the second D flip-flop through the second inverter; the Q end of the second D flip-flop is electrically connected to the D end of the second D flip-flop through the third inverter, and the Q end of the second D flip-flop is electrically connected to the third input end of the first logic function module; The first input terminal of the first logic function module is electrically connected to the reset terminal of the first D flip-flop and the reset terminal of the second D flip-flop through the fourth inverter.

4. The time measurement circuit according to claim 1, characterized in that: The oscillation module includes a second logic function module, and the delay module includes a third delay unit; The first input end of the second logic function module is connected to the signal to be tested, the output end of the second logic function module serves as the output end of the oscillation module, the output end of the second logic function module is electrically connected to the input end of the third delay unit, and the output end of the third delay unit is electrically connected to the second input end of the second logic function module; the second logic function module is used to invert the input signal of its second input end and output it from its output end when the first input end thereof inputs a first level; and output the second level from its output end when the first input end thereof inputs a second level; wherein the first level and the second level are different in level.

5. The time measurement circuit according to claim 1, characterized in that: The time measurement circuit is implemented based on FPGA, and the delay module includes at least one of the following: an input-output delay device IODELAY, a dedicated delay chip, and a delay circuit constructed by a DAC and a comparator.

6. The time measurement circuit according to claim 3 or 4, characterized in that: The logic function module includes a lookup table.

7. A time measurement method, executed by the time measurement circuit according to any one of claims 1 to 6, characterized in that: The time measurement method comprises: In the initial stage, within the duration of the first level of each period of the signal to be measured, the number of periods of the oscillation signal is measured to obtain an initial count value; In the adjustment stage, the delay value of the delay module is adjusted, and when the count value of the counting module changes compared with the initial count value, the delay value is fixed; In the measurement phase, the frequency of the oscillation signal is measured; and the duration of the first level of the signal to be measured is determined according to the frequency of the oscillation signal and the count value of the counting module.

8. The time measurement method according to claim 7, characterized in that: In the initial stage, within the first level duration of each cycle of the signal to be measured, measuring the number of cycles of the oscillation signal to obtain the initial count value includes: In N cycles of the signal to be tested, if the count values ​​of the oscillation signal are all equal during the first level duration of each cycle, the count value of the oscillation signal is used as the initial count value; wherein N≥2.

9. The time measurement method according to claim 7, characterized in that: In the adjustment stage, adjusting the delay value of the delay module, and fixing the delay value when the count value of the counting module changes compared to the initial count value, includes: In a plurality of cycles of the signal to be tested, the delay value of the delay module is increased sequentially, and when the count value of the counting module decreases compared to the initial count value, the delay value is fixed; Alternatively, within a plurality of cycles of the signal to be tested, the delay value of the delay module is reduced in sequence, and when the count value of the counting module increases compared to the initial count value, the delay value is fixed; Alternatively, within a plurality of cycles of the signal to be tested, the delay value of the delay module is increased so that the count value of the counting module decreases compared to the initial count value; the delay value of the delay module is then decreased, and when the count value of the counting module is equal to the initial count value again, the delay value is fixed; Alternatively, within multiple cycles of the signal to be tested, the delay value of the delay module is reduced so that the count value of the counting module increases compared to the initial count value; then the delay value of the delay module is increased, and when the count value of the counting module is equal to the initial count value again, the delay value is fixed.

10. The time measurement method according to claim 7, characterized in that: In the measurement phase, measuring the frequency of the oscillation signal includes: Control the oscillation module to output an oscillation signal in a fixed manner; measuring the frequency of the oscillation signal; and / or, In the measurement phase, determining the duration of the first level of the signal to be measured according to the frequency of the oscillation signal and the count value of the counting module includes: Determining a period of the oscillation signal according to the frequency of the oscillation signal; Determine the number of cycles of the oscillation signal within the duration of the first level of the signal to be tested according to the count value of the counting module; The duration of the first level of the signal to be tested is obtained by multiplying the number of periods by the period of the oscillation signal.

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