Assembly line successive approximation type analog-to-digital conversion circuit and method

Abstract

The invention provides a pipeline successive approximation type analog-to-digital conversion circuit and method, and relates to the technical field of analog-to-digital conversion. The assembly line successive approximation type analog-to-digital conversion circuit comprises a two-stage analog-to-digital converter, a residual amplifier, a feedback circuit and a digital coding circuit, the analog input end of the first-stage analog-to-digital converter receives an analog input signal, the residual output end of the first-stage analog-to-digital converter is connected with the input end of the residual amplifier, and the output end of the first-stage analog-to-digital converter is connected with the analog input end of the second-stage analog-to-digital converter; the digital output end of the second-stage analog-to-digital converter is connected with the input end of the feedback circuit; the output end of the feedback circuit is connected with the feedback input end of the analog-to-digital converter; the digital output ends of the analog-to-digital converters are connected with the digital coding circuit, and the digital coding circuit is used for generating target digital signals corresponding to the analog input signals according to digital codes output by the analog-to-digital converters. According to the invention, high-speed, high-precision and low-power-consumption signal conversion can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, and in particular to a pipeline successive approximation analog-to-digital conversion circuit and method. Background Art

[0002] A traditional pipelined analog-to-digital converter (Pipelined ADC) works by cascading multiple sub-stages, and a Flash ADC with a lower quantization bit number is used as a sub-ADC in each sub-stage. When the accuracy is high, too many pipeline sub-stages need to be cascaded, consuming a lot of power.

[0003] The traditional successive approximation analog-to-digital converter (SAR ADC) has the characteristics of simple structure and low power consumption, but it is essentially a serial structure ADC, which requires multiple comparisons in each cycle. When the number of bits is large, the required conversion time is too long. Therefore, the pipelined successive approximation analog-to-digital converter (Pipelined SAR ADC) or two-step successive approximation analog-to-digital converter (Two-Step SAR ADC) that combines the two has become a hot research topic in recent years because it can simultaneously have the advantages of high speed, high precision and low power consumption. Summary of the invention

[0004] The purpose of the present application is to provide a pipelined successive approximation analog-to-digital conversion circuit and method to address the deficiencies in the above-mentioned prior art, so as to achieve high-speed, high-precision, and low-power signal conversion.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a pipelined successive approximation analog-to-digital conversion circuit, the pipelined successive approximation analog-to-digital conversion circuit comprising: a two-stage analog-to-digital converter, a residual amplifier, a feedback circuit, and a digital encoding circuit;

[0007] An analog input terminal of a first-stage analog-to-digital converter in the two-stage analog-to-digital converter receives an analog input signal, a residual output terminal of the first-stage analog-to-digital converter is connected to an input terminal of a residual amplifier, and an output terminal of the residual amplifier is connected to an analog input terminal of a second-stage analog-to-digital converter in the two-stage analog-to-digital converter;

[0008] The digital output terminal of the second-stage analog-to-digital converter is connected to the input terminal of the feedback circuit, and the two output terminals of the feedback circuit are respectively connected to the feedback input terminals of the two-stage analog-to-digital converter;

[0009] The digital output ends of the two-stage analog-to-digital converter are both connected to the digital encoding circuit, and the digital encoding circuit is used to generate a target digital signal corresponding to the analog input signal according to the digital code output by the two-stage analog-to-digital converter.

[0010] Optionally, the first-stage analog-to-digital converter includes: a first analog-to-digital conversion unit and an inverse residual amplifier;

[0011] The analog input terminal of the first analog-to-digital conversion unit serves as the analog input terminal of the first-stage analog-to-digital converter, the input terminal of the inverse residual amplifier serves as the feedback input terminal of the first-stage analog-to-digital converter, the output terminal of the inverse residual amplifier is connected to the feedback input terminal of the first analog-to-digital conversion unit, the residual output terminal of the first analog-to-digital conversion unit serves as the residual output terminal of the first-stage analog-to-digital converter, and the digital output terminal of the first analog-to-digital conversion unit serves as the digital output terminal of the first-stage analog-to-digital converter;

[0012] The second-stage analog-to-digital converter includes: a second analog-to-digital conversion unit.

[0013] Optionally, the first analog-to-digital conversion unit includes: M+1 first capacitors and a first control switch group, a second control switch, a third control switch, a first comparator and a first successive approximation logic circuit, where M is the number of quantization bits of the first-stage analog-to-digital converter;

[0014] One end of the first M first control switch groups is respectively connected to a positive reference signal, a negative reference signal, a preset common mode signal and the analog input signal, one end of the M+1 first control switch group is respectively connected to the preset common mode signal and the analog input signal, and the other end of the M+1 first control switch group is connected to the bottom plate of the M+1 first capacitor;

[0015] The top plates of the M+1 first capacitors are connected as the feedback input terminal of the first analog-to-digital conversion unit, and the capacitor connection point thereof is connected to the preset common mode signal through the second control switch;

[0016] The capacitor connection point is also connected to the third control switch as a residual output terminal of the first analog-to-digital conversion unit;

[0017] The capacitor connection point is also connected to the positive input terminal of the first comparator, the negative input terminal of the first comparator is connected to the preset common mode signal, the output terminal of the first comparator is connected to the input terminal of the first successive approximation logic circuit, and the output terminal of the first successive approximation logic circuit serves as the digital output terminal of the first analog-to-digital conversion unit;

[0018] The output end of the first successive approximation logic circuit is also connected to the control ends of the M+1 first control switch groups.

[0019] Optionally, the inverse residual amplifier includes: B+1 second capacitors and a fourth control switch group, wherein the ratio of the total value of the B+1 second capacitors to the sum of the total value of the M+1 first capacitors and the total value of the B+1 second capacitors is the amplification factor of the inverse residual amplifier, and B is the number of feedback bits of the feedback circuit;

[0020] One end of the first B fourth control switch groups are respectively connected to a positive reference signal, a negative reference signal, a preset common mode signal and an analog input signal, one end of the B+1th fourth control switch group is respectively connected to the preset common mode signal and the analog input signal, and the other end of the B+1th fourth control switch group is connected to the bottom plate of the B+1 second capacitor;

[0021] The control ends of the B+1 fourth control switch groups serve as the input ends of the inverse residual amplifier, and the top plates of the B+1 second capacitors are connected as the output ends of the inverse residual amplifier.

[0022] Optionally, the second analog-to-digital conversion unit includes: L+1 third capacitors and a fifth control switch group, a sixth control switch group, a seventh control switch, a fourth capacitor, a fifth capacitor, a second comparator, a second successive approximation logic circuit and a first selector, where L is the number of quantization bits of the second-stage analog-to-digital converter;

[0023] One end of the first L fifth control switch groups is respectively connected to the positive reference signal, the negative reference signal, the preset common mode signal and the output end of the residual amplifier, one end of the L+1th fifth control switch group is respectively connected to the preset common mode signal and the output end of the residual amplifier, and the other end of the L+1th fifth control switch group is connected to the bottom plate of the L+1 third capacitor;

[0024] One end of the sixth control switch group is connected to the preset common mode signal and the output end of the residual amplifier respectively, and the other end of the sixth control switch group is connected to the bottom plate of the fourth capacitor;

[0025] The top plates of the L+1 third capacitors are connected to the bottom plate of the fifth capacitor, the top plate of the fifth capacitor is connected to the top plate of the fourth capacitor, and the capacitor connection point is connected to the preset common mode signal through the seventh control switch;

[0026] The capacitor connection point is also connected to the positive input terminal of the second comparator, the negative input terminal of the second comparator is connected to the preset common mode signal, the output terminal of the second comparator is connected to the input terminal of the second successive approximation logic circuit, and the output terminal of the second successive approximation logic circuit serves as the digital output terminal of the second-stage analog-to-digital converter;

[0027] The output end of the second successive approximation logic circuit is connected to the first input end of the first selector, and the second input end of the first selector serves as the feedback input end of the second-stage analog-to-digital converter;

[0028] The output end of the first selector is connected to the control ends of the fifth control switch group and the sixth control switch group.

[0029] Optionally, the residual amplifier comprises: an amplifier, two sixth capacitors, two seventh capacitors, a plurality of first phase switches, a plurality of second phase switches, a plurality of second phase first sub-switches and a plurality of second phase second sub-switches;

[0030] The residual output end of the first-stage analog-to-digital converter is respectively connected to the positive input end and the negative input end of the amplifier through two second phase switches, and the positive input end and the negative input end of the amplifier are also respectively connected to a preset common-mode signal through two first phase switches;

[0031] The positive output terminal and the negative output terminal of the amplifier are respectively connected to the top plates of the two sixth capacitors through two second-phase first sub-switches, the positive output terminal and the negative output terminal of the amplifier are respectively connected to the bottom plates of the two sixth capacitors through two second-phase second sub-switches, and the bottom plates of the two sixth capacitors are also respectively connected to the preset common-mode signal through two second-phase first sub-switches;

[0032] The positive input terminal of the amplifier is connected to the top plate of the sixth capacitor at the negative output terminal through a seventh capacitor, and the negative input terminal of the amplifier is connected to the top plate of the sixth capacitor at the positive output terminal through another seventh capacitor;

[0033] The two seventh capacitors are further connected via a first phase switch, and the two seventh capacitors are further connected to the preset common mode signal via two first phase switches respectively;

[0034] The two seventh capacitors are connected as output terminals of the residual amplifier.

[0035] Optionally, the amplifier is a gain-enhanced telescopic cascode amplifier.

[0036] Optionally, the feedback circuit includes: a plurality of D flip-flops, a plurality of gain error feedback modules with increasing orders, and a second selector;

[0037] The input end of the first D flip-flop serves as the input end of the feedback circuit, multiple D flip-flops are connected in series in sequence, the input end of the i-th order gain error feedback module is connected to the output end of the first i D flip-flops, the output ends of the multiple gain error feedback modules are respectively connected to the multiple input ends of the second selector, and the output end of the second selector serves as the output end of the feedback circuit;

[0038] The clock terminals of the plurality of D flip-flops are used to receive a clock signal.

[0039] In a second aspect, an embodiment of the present application further provides an analog-to-digital conversion method, which is applied to the pipelined successive approximation analog-to-digital conversion circuit as described in any one of the first aspects, and the method includes:

[0040] In the working stage of the first-stage analog-to-digital converter, the analog input signal is quantized to generate a first digital code and a first-stage residual signal;

[0041] In the residual amplification stage of the residual amplifier, the first-stage residual signal is amplified to obtain an amplified residual signal;

[0042] In the working stage of the second-stage analog-to-digital converter, the amplified residual signal and the feedback signal of the current cycle are added and quantized to generate a second digital code;

[0043] In the feedback phase of the feedback circuit, the second digital code is processed by a preset feedback function to generate a feedback signal and feed it back to the working phase of the first-stage analog-to-digital converter and the working phase of the second-stage analog-to-digital converter in the next cycle;

[0044] In the coding field of the digital coding circuit, the first digital code and the second digital code are combined to generate a target digital signal corresponding to the analog input signal.

[0045] Optionally, in the working stage of the first-stage analog-to-digital converter, quantizing the analog input signal to generate a first digital code and a first-stage residual signal includes:

[0046] In the first sampling stage, the analog input signal is sampled;

[0047] In the first reset stage, the sampled analog input signal is held;

[0048] In the first quantization stage, the analog input signal is quantized to generate the first digital code and the original residual signal;

[0049] In the first-stage subtraction stage, the original residual signal and the feedback signal are subtracted to generate the first-stage residual signal.

[0050] Optionally, in the working stage of the second-stage analog-to-digital converter, the amplified residual signal and the feedback signal of the current cycle are added, and quantized to generate a second digital code, including:

[0051] In the second sampling stage, the amplified residual signal is sampled;

[0052] In the second stage reset phase, the sampled amplified residual signal is maintained;

[0053] In the second stage of addition, the amplified residual signal and the feedback signal are added to generate a restored input signal;

[0054] In the second-level quantization stage, the restored input signal is quantized to generate the second digital code.

[0055] The beneficial effects of this application are:

[0056] The present application provides a pipeline successive approximation analog-to-digital conversion circuit and method, which provides a feedback circuit to process the digital code output by the second-stage analog-to-digital converter to obtain a feedback digital code, subtract the feedback digital code from the first-stage analog-to-digital converter, and add the feedback digital code back to the second-stage analog-to-digital converter to extract the gain error of the residual amplifier and perform a shaping operation so that the gain error is shaped into a high-pass shape. At the same time, a high-precision residual amplifier is used to further reduce the gain error of the residual amplifier, so that the influence of the quantization leakage error after high-pass shaping on the analog input signal bandwidth is greatly reduced, and high-precision signal conversion is achieved under the premise of ensuring high-speed and low power consumption of analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A structural block diagram of a pipelined successive approximation analog-to-digital conversion circuit provided in an embodiment of the present application;

[0059] Figure 2 A circuit structure diagram of a first-stage analog-to-digital converter provided in an embodiment of the present application;

[0060] Figure 3 A circuit structure diagram of a second-stage analog-to-digital converter provided in an embodiment of the present application;

[0061] Figure 4 A circuit structure diagram of a residual amplifier provided in an embodiment of the present application;

[0062] Figure 5 A circuit diagram of an amplifier provided in an embodiment of the present application;

[0063] Figure 6 A schematic diagram of the structure of a feedback circuit provided in an embodiment of the present application;

[0064] Figure 7 A signal flow chart of a pipelined successive approximation analog-to-digital conversion circuit provided in an embodiment of the present application;

[0065] Figure 8 A schematic diagram of a flow chart of an analog-to-digital conversion method provided in an embodiment of the present application;

[0066] Fig. 9 This is a working timing diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0068] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0069] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0070] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0071] In a traditional pipelined successive approximation analog-to-digital conversion circuit, an inter-stage residual amplifier (RA) is set between two stages of successive approximation analog-to-digital converters to ensure that each sub-stage can sense the full-scale signal, thereby greatly relaxing the accuracy requirements for the sub-stages. However, when there is an error in the amplification factor of the residual amplifier, the quantization noise of the first-stage SAR ADC will leak to the final output, thereby greatly affecting the overall conversion accuracy.

[0072] Specifically, in a conventional pipeline successive approximation analog-to-digital conversion circuit, the output D out It can be expressed as: D out =D out1 +D out2 / G, where D out1 = Vin-Q1, the gain of the inter-stage residual amplifier is G(1-Δ), then D out2 =G(1-Δ)Q1-Q2, through transformation we can get:

[0073] D out =D out1 +D out2 / G=Vin-ΔQ1-Q2 / G

[0074] Among them, Q1 is the first-level quantization error, Q2 is the second-level quantization error. It can be seen that there is a quantization leakage error ΔQ1 at this time, and its value is the product of the gain error Δ and the first-level quantization error Q1.

[0075] Based on the technical problems existing in the above-mentioned prior art, the present application intends to provide a pipelined successive approximation analog-to-digital conversion circuit and method. By setting a feedback circuit, the digital code output by the second-stage analog-to-digital converter is processed to obtain a feedback digital code, the feedback digital code is subtracted from the first-stage analog-to-digital converter, and the feedback digital code is added back to the second-stage analog-to-digital converter to extract the gain error of the residual amplifier and perform a shaping operation so that the gain error is shaped into a high-pass shape. At the same time, a high-precision residual amplifier is used to further reduce the gain error of the residual amplifier, so that the influence of the quantization leakage error after high-pass shaping on the analog input signal bandwidth is greatly reduced, thereby achieving high-precision signal conversion while ensuring high-speed and low power consumption of analog-to-digital conversion.

[0076] The specific implementation of the pipelined successive approximation analog-to-digital conversion circuit and method provided by the present application is described below in conjunction with the embodiments.

[0077] In one possible implementation, the present application provides a pipelined successive approximation analog-to-digital conversion circuit. Specifically, the pipelined successive approximation analog-to-digital conversion circuit may include: a two-stage analog-to-digital converter, a residual amplifier, a feedback circuit, and a digital encoding circuit.

[0078] The analog input end of the first-stage analog-to-digital converter in the two-stage analog-to-digital converter receives an analog input signal, the residual output end of the first-stage analog-to-digital converter is connected to the input end of a residual amplifier, and the output end of the residual amplifier is connected to the analog input end of the second-stage analog-to-digital converter in the two-stage analog-to-digital converter; the digital output end of the second-stage analog-to-digital converter is connected to the input end of a feedback circuit, and the two output ends of the feedback circuit are respectively connected to the feedback input ends of the two-stage analog-to-digital converter; the digital output ends of the two-stage analog-to-digital converters are both connected to a digital encoding circuit, and the digital encoding circuit is used to generate a target digital signal corresponding to the analog input signal according to the digital code output by the two-stage analog-to-digital converter.

[0079] Figure 1 The structural block diagram of the pipeline successive approximation analog-to-digital conversion circuit provided in the embodiment of the present application is as follows: Figure 1 As shown, taking a two-stage analog-to-digital converter as an example, the analog input end of the first-stage analog-to-digital converter 1 receives the analog input signal Vin, the residual output end of the first-stage analog-to-digital converter 1 is connected to the input end of the residual amplifier 2, and is used to output the first-stage residual signal Q1 to the residual amplifier 2, and the digital output end of the first-stage analog-to-digital converter 1 is used to output the first digital code D out1 The residual amplifier 2 amplifies the first-stage residual signal Q1 and outputs the amplified residual signal Vo. The output end of the residual amplifier 2 is connected to the analog input end of the second-stage analog-to-digital converter 3. The digital output end of the second-stage analog-to-digital converter 3 is used to output the second digital code D out2 .

[0080] The digital output end of the second-stage analog-to-digital converter 3 is connected to the input end of the feedback circuit 4, and the output end of the feedback circuit 4 is respectively connected to the feedback input ends of the first-stage analog-to-digital converter 1 and the second-stage analog-to-digital converter 3 to provide feedback digital code D for the first-stage analog-to-digital converter 1 and the second-stage analog-to-digital converter 3. FB .

[0081] The digital encoding circuit 5 is used to encode the first digital code D out1 and the second digital code D out2 Add and get the final quantized output digital code D out .

[0082] The specific working principle of the pipeline successive approximation analog-to-digital converter is as follows: First, the analog input signal Vin is quantized by the first-stage analog-to-digital converter 1 to generate the first-stage quantized first digital code D out1 , combined with the feedback digital code D FB The first-stage residual signal Q1 is generated. The first-stage residual signal Q1 is amplified by G(1-Δ) times by the residual amplifier with error to obtain an amplified error signal Vo. The amplified error signal Vo is combined with the feedback digital code D FB Generate an analog input signal Vin2 for the second-stage analog-to-digital converter.

[0083] Where G is the ideal amplification factor, Δ is the gain error, and the second-stage analog-to-digital converter 3 quantizes the analog input signal Vin2 to generate the second-stage quantized second digital code D out2 .

[0084] Second digit code D out2 It will be output to the feedback circuit 4 at the same time, and the feedback digital code D will be obtained after being processed by the system function H(z) of the feedback circuit. FB , feedback digital code D FB It will be fed back to the first-stage analog-to-digital converter 1 and the second-stage analog-to-digital converter 3 to perform a gain error Δ shaping operation, so that the gain error Δ is shaped into a high-pass shape.

[0085] In a possible implementation, the first-stage analog-to-digital converter includes: a first analog-to-digital conversion unit and an inverse residual amplifier; the analog input end of the first analog-to-digital conversion unit serves as the analog input end of the first-stage analog-to-digital converter, the input end of the inverse residual amplifier serves as the feedback input end of the first-stage analog-to-digital converter, the output end of the inverse residual amplifier is connected to the feedback input end of the first analog-to-digital conversion unit, the residual output end of the first analog-to-digital conversion unit serves as the residual output end of the first-stage analog-to-digital converter, and the digital output end of the first analog-to-digital conversion unit serves as the digital output end of the first-stage analog-to-digital converter; the second-stage analog-to-digital converter includes: a second analog-to-digital conversion unit.

[0086] In this embodiment, the first-stage analog-to-digital converter includes a first analog-to-digital conversion unit and an inverse residual amplifier. Since the original residual signal Q0 generated by the first-stage analog-to-digital conversion unit will be amplified by G times after passing through the residual amplifier, it is necessary to set an inverse residual amplifier in the first-stage analog-to-digital converter. The feedback circuit is based on the second digital code D out2 Generate feedback digital code D FB After that, it is reduced by G times through the inverse residual amplifier, and the feedback digital code D reduced by G times is subtracted from the original residual signal Q0 generated by the first-stage analog-to-digital conversion unit. FB The first residual signal Q1 is obtained, so as to achieve shaping of the gain error of the residual amplifier through the feedback circuit, thereby reducing the influence of the gain error on the first residual signal Q1.

[0087] The second-stage analog-to-digital converter does not need to be amplified by the residual amplifier, so there is no need to set an inverse residual amplifier in the second-stage analog-to-digital converter, that is, the second-stage analog-to-digital converter only needs to be composed of the second analog-to-digital conversion unit.

[0088] In one possible implementation, Figure 2 The circuit structure diagram of the first-stage analog-to-digital converter provided in the embodiment of the present application is as follows: Figure 2As shown, the first analog-to-digital conversion unit includes: M+1 first capacitors 11 and a first control switch group 12, a second control switch 13, a third control switch 14, a first comparator 15 and a first successive approximation logic circuit 16, where M is the quantization bit number of the first-stage analog-to-digital converter.

[0089] One end of the first M first control switch groups 12 is respectively connected to the positive reference signal Vrp, the negative reference signal Vrn, the preset common mode signal Vcm and the analog input signal Vin, one end of the M+1 first control switch group 12 is respectively connected to the preset common mode signal Vcm and the analog input signal Vin, and the other end of the M+1 first control switch group 12 is connected to the bottom plate of the M+1 first capacitor 11; the top plate of the M+1 first capacitor 11 is connected as the feedback input end of the first analog-to-digital conversion unit, and its capacitor connection point is connected to the preset common mode signal Vcm through the second control switch 13. The capacitor connection point is also connected to the third control switch 14 as the residual output terminal of the first analog-to-digital conversion unit; the capacitor connection point is also connected to the positive input terminal of the first comparator 15, the negative input terminal of the first comparator 15 is connected to the preset common-mode signal Vcm, the output terminal of the first comparator 15 is connected to the input terminal of the first successive approximation logic circuit 16, and the output terminal of the first successive approximation logic circuit 16 serves as the digital output terminal of the first analog-to-digital conversion unit; the output terminal of the first successive approximation logic circuit 16 is also connected to the control terminal of M+1 first control switch groups 12.

[0090] In this embodiment, if Figure 2 As shown, M+1 first capacitors form a first-stage SAR DAC, which is used to convert the first digital code Dout1 generated by the first successive approximation logic circuit 16 into an analog signal, and subtract it from the analog input signal Vin to generate an original residual signal Q0 of the first-stage analog-to-digital conversion unit.

[0091] In which, when the first analog-to-digital conversion unit samples the analog input signal Vin, the bottom plates of the M+1 first capacitors are connected to the analog input signal Vin through the first control switch group 12, and the top plates are connected to the preset common mode signal Vcm. At this time, the analog input signal Vin is stored in all the first capacitors in the form of charge.

[0092] Then, in the reset phase of the first analog-to-digital conversion unit, the bottom plates of the M+1 first capacitors are connected to the preset common-mode signal Vcm under the control of the non-overlapping clock signal, and the top plates are disconnected and in a high-impedance state. At this time, the analog input signal Vin is transmitted and maintained to the top plate of the first capacitor.

[0093] Afterwards, in the quantization stage of the first analog-to-digital conversion unit, the first comparator 15 determines the size of the voltage signal on the top plate of the first capacitor, and the first successive approximation logic circuit 16 generates the first data code D of the first level quantization according to the determination result of the first comparator 15 according to the binary search algorithm. out1 , and the first data code D out1 The first digital code D is fed back to the first control switch group 12, and the first digital code D is fed back to the first control switch group 12 by controlling the conduction of the first control switch group 12. out1 The first digital code D out1 The corresponding analog signal quantities are subtracted to generate the first-stage original residual signal Q0 at the top plate of the first capacitor.

[0094] Furthermore, if Figure 2 The inverse residual amplifier includes: B+1 second capacitors 17 and a fourth control switch group 18, wherein the ratio of the total value of the B+1 second capacitors 17 to the sum of the total value of the M+1 first capacitors 11 and the total value of the B+1 second capacitors 17 is the amplification factor of the inverse residual amplifier, and B is the number of feedback bits of the feedback circuit.

[0095] One end of the first B fourth control switch groups 18 is connected to the positive reference signal V rp , negative reference signal V rn , preset common mode signal V cm and the analog input signal V in , one end of the B+1th fourth control switch group 18 is respectively connected to the preset common mode signal V cm and the analog input signal V in , the other end of the B+1 fourth control switch group 18 is connected to the bottom plate of the B+1 second capacitor 17; the control end of the B+1 fourth control switch group 18 serves as the input end of the inverse residual amplifier, and the top plate of the B+1 second capacitor 17 is connected as the output end of the inverse residual amplifier.

[0096] In this embodiment, the feedback circuit may be, for example, an error feedback (EF) circuit or a gain error feedback (GEF) circuit. Assume that the total number of bits of the pipeline successive approximation analog-to-digital conversion circuit is N bits, the first-stage analog-to-digital converter quantizes M bits, and the second-stage analog-to-digital converter quantizes L bits, wherein N=M+L. B bits of the L-bit digital code of the second-stage analog-to-digital converter are used as feedback signals and are fed back to the first-stage analog-to-digital converter and the second-stage analog-to-digital converter after being processed by the feedback circuit. The gain of the residual amplifier between the two-stage analog-to-digital converters is G times, G=2 M .

[0097] B+1 second capacitors 17 form the first-stage EF DAC or GEF DAC, and the total capacitance value of the B+1 second capacitors is 1 / G times the total capacitance value of the B+1 second capacitors and the M+1 first capacitors, thereby realizing inverse residual amplification in the charge domain.

[0098] In the multiplication and subtraction stage of the first analog-to-digital conversion unit, if the feedback circuit function is turned on, according to the feedback digital code D provided by the feedback circuit FB The fourth control switch group 18 is controlled to be turned on, and the bottom plates of the B+1 second capacitors 17 generate the feedback digital code D FB The corresponding analog signal quantity is based on the amplification factor 1 / G of the inverse residual amplifier unit, and the original residual signal Q0 and D FB / G are subtracted to obtain a shaped high-pass first residual signal Q1.

[0099] The first analog-to-digital conversion unit in the first-stage analog-to-digital converter and the capacitor in the inverse residual amplifier adopt bottom plate sampling technology, and the control switch group adopts Vcm-based switch timing. The control switch group includes a switch for controlling the analog input signal and a three-level switch for controlling the reference voltage.

[0100] In one possible implementation, Figure 3 The circuit structure diagram of the second-stage analog-to-digital converter provided in the embodiment of the present application is as follows: Figure 3 As shown, the second analog-to-digital conversion unit includes: L+1 third capacitors 31 and a fifth control switch group 32, a sixth control switch group 33, a seventh control switch 34, a fourth capacitor Cvd, a fifth capacitor Catt, a second comparator 35, a second successive approximation logic circuit 36 ​​and a first selector 37, where L is the number of quantization bits of the second-stage analog-to-digital converter.

[0101] One end of the first L fifth control switch groups 32 is connected to the positive reference signal V rp , negative reference signal V rn , preset common mode signal V cm and the residual amplifier output V o , one end of the L+1th fifth control switch group 32 is respectively connected to the preset common mode signal V cm and the residual amplifier output V o , the other end of the L+1 fifth control switch group 32 is connected to the bottom plate of the L+1 third capacitor 31; one end of the sixth control switch group 33 is respectively connected to the preset common mode signal V cm and the output of the residual amplifier V o The other end of the sixth control switch group 33 is connected to the bottom plate of the fourth capacitor Cvd.

[0102] The top plates of L+1 third capacitors 31 are connected to the bottom plates of the fifth capacitor Catt, and the top plates of the fifth capacitor Catt are connected to the top plates of the fourth capacitor Cvd. The capacitor connection points are connected to the preset common mode signal V through the seventh control switch 34. cm ; The capacitor connection point is also connected to the positive input terminal of the second comparator 35, the negative input terminal of the second comparator 35 is connected to the preset common-mode signal Vcm, the output terminal of the second comparator 35 is connected to the input terminal of the second successive approximation logic circuit 36, and the output terminal of the second successive approximation logic circuit 36 ​​serves as the digital output terminal of the second-stage analog-to-digital converter; the output terminal of the second successive approximation logic circuit 36 ​​is connected to the first input terminal of the first selector 37, and the second input terminal of the first selector 37 serves as the feedback input terminal of the second-stage analog-to-digital converter; the output terminal of the first selector 37 is connected to the control terminals of the fifth control switch group 32 and the sixth control switch group 33.

[0103] In this embodiment, in the stage where the second analog-to-digital conversion unit samples the amplified residual signal, the bottom plates of the L+1 third capacitors and the fourth capacitor Cvd are connected to the amplified residual signal GQ1, and the top plates of the fourth capacitor Cvd and the fifth capacitor Catt are connected to the preset common mode signal V cm At this time, the amplified residual signal GQ1 is stored in all the second capacitors in the form of charges.

[0104] Then, in the reset phase of the second analog-to-digital conversion unit, the bottom plates of the L+1 third capacitors and the fourth capacitor Cvd are connected to the preset common mode signal V under the control of the non-overlapping clock signal. cm , the top plates of the fourth capacitor Cvd and the fifth capacitor Catt are disconnected and are in a high-impedance state. At this time, the amplified residual signal is transmitted and maintained to the top plate of the third capacitor.

[0105] Afterwards, in the addition stage of the second analog-to-digital conversion unit, if the feedback circuit function is turned on, according to the feedback digital code D provided by the feedback circuit FB The fifth control switch group 32 and the sixth control switch group 33 are turned on, and the bottom plates of the L+1 third capacitors and the fourth capacitor Cvd generate the feedback digital code D FB The corresponding analog signal quantity is the amplified residual signal GQ1 and the feedback digital code D FB The corresponding analog signal quantities are added to restore the original input signal Vin2 of the second-stage analog-to-digital converter.

[0106] In the quantization stage of the second analog-to-digital conversion unit, the restored input signal Vin2 is quantized by the second comparator 35 and the second successive approximation logic circuit 36 ​​to obtain a second digital code D out2 .

[0107] In one possible implementation, the residual amplifier in the pipelined successive approximation analog-to-digital conversion circuit of the embodiment of the present application can be a common circuit structure that can realize an amplification function, such as a switched capacitor closed-loop amplifier, an open-loop amplifier, a ring amplifier (Ring AMP), a floating inverting amplifier (FIA), etc.

[0108] In some embodiments, Figure 4 The circuit structure diagram of the residual amplifier provided in the embodiment of the present application is as follows: Figure 4 As shown, the residual amplifier includes: an amplifier 21, two sixth capacitors C LS , two seventh capacitors C F , a plurality of first phase switches Multiple second phase switches A plurality of second phase first sub switches and a plurality of second phase second sub switches

[0109] The residual output of the first-stage analog-to-digital converter is connected through two second-phase switches. The positive input terminal and the negative input terminal of the amplifier 21 are connected respectively, and the positive input terminal and the negative input terminal of the amplifier 21 are also connected through two first phase switches Connect the preset common mode signal V cm .

[0110] The positive output terminal and the negative output terminal of the amplifier 21 are connected through two second phase first sub switches. Connect two sixth capacitors C LS The positive output terminal and the negative output terminal of the amplifier 21 are connected through two second phase second sub switches. Connect two sixth capacitors C LS The bottom plate, two sixth capacitors C LS The bottom plate of the second phase first sub switch Connect the preset common mode signal V cm .

[0111] The positive input terminal of the amplifier 21 is connected to the F The sixth capacitor C connected to the negative output terminal LS The negative input terminal of the amplifier 21 is connected to the top plate of the amplifier 21 through another seventh capacitor C F The sixth capacitor C connected to the positive output terminal LS The top plate.

[0112] Two seventh capacitors C F Also through a first phase switch Connect the two seventh capacitors C F Also through the two first phase switches Connect the preset common mode signal V cm ; Two seventh capacitors C F Connect as the output of the residual amplifier.

[0113] In this embodiment, a correlated level shifting technique (CLS, or correlated level shifting technique) is used to adjust the sixth capacitor C LS Set the second phase first sub switch and the second phase sub-switch

[0114] In the first phase, control the first phase switch The seventh capacitor C F Charging is performed, and in the second phase, the second phase switch is controlled On, in the first sub-phase of the second phase, control the first sub-switch of the second phase The output of the residual amplifier is simultaneously connected to the second-stage analog-to-digital converter and the sixth capacitor C LS Sampling, in the second sub-phase of the second phase, controlling the second sub-switch of the second phase The sixth capacitor C LS The bottom plate of the amplifier 21 is switched to the output end of the amplifier 21 for level shifting. At this time, the output of the amplifier 21 is instantly raised, but due to the sixth capacitor C LS The charge sharing effect between the second-stage analog-to-digital converter and the sixth capacitor C LS Part of the charge is pre-stored on the residual amplifier, so the output of the residual amplifier is closer to the ideal value, which is equivalent to the switching gain of the amplifier becoming higher.

[0115] In some embodiments, the amplifier is a telescopic cascode amplifier.

[0116] The pipelined successive approximation analog-to-digital conversion circuit provided in the above embodiment uses a high-precision closed-loop amplifier in the residual amplifier to further reduce the gain error of the residual amplifier, so that the influence of the quantization leakage error after high-pass shaping on the analog input signal bandwidth is greatly reduced, thereby achieving high-precision analog-to-digital conversion.

[0117] Figure 5 The circuit structure diagram of the amplifier provided in the embodiment of the present application is as follows: Figure 5 As shown, the amplifier of this embodiment adopts a gain-boosting telescopic cascode amplifier, which can achieve a higher open-loop gain without consuming much power. Its specific structure and connection relationship are shown in the figure, and will not be described here.

[0118] In a possible implementation, the feedback circuit includes: a plurality of D flip-flops, a plurality of gain error feedback modules with increasing orders, and a second selector.

[0119] The input end of the first D flip-flop serves as the input end of the feedback circuit, multiple D flip-flops are connected in series in sequence, the input end of the i-th order gain error feedback module is connected to the output end of the first i D flip-flops, the output ends of the multiple gain error feedback modules are respectively connected to the multiple input ends of the second selector, and the output end of the second selector serves as the output end of the feedback circuit; the clock ends of the multiple D flip-flops are used to receive clock signals.

[0120] Wherein, i is the order of the gain error feedback module, and i is a positive integer greater than or equal to 1. This embodiment is described by taking i values ​​of 1 and 2 as examples.

[0121] In this embodiment, Figure 6 A schematic diagram of the structure of the feedback circuit provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, taking the second-order gain error feedback as an example, the feedback circuit includes two D flip-flops, a first-order gain error feedback module, a second-order gain error feedback module and a second selector. The input end of the first D flip-flop is used to receive the second digital code D out2 The output end of the first D flip-flop is connected to the input end of the second D flip-flop, the input end of the first-order gain error feedback module and one input end of the second-order gain error feedback module, the output end of the second D flip-flop is connected to the other input end of the second-order gain error feedback module, and the output end of the first-order gain error feedback module and the output end of the second-order error gain shaping module are respectively connected to the two input ends of the second selector.

[0122] When the first-order feedback is turned on, the system function of the feedback circuit is H(z) = z -1 , when the second-order feedback is turned on, the system function of the feedback circuit is H(z) = 2z -1 -z -2 , and so on, through the second selector to configure the feedback digital code D to be output FB The order of .

[0123] Based on the specific implementation of the above pipeline successive approximation analog-to-digital converter, for example, Figure 7 The signal flow chart of the pipeline successive approximation analog-to-digital conversion circuit provided in the embodiment of the present application is as follows: Figure 7 As shown, the first-stage analog-to-digital converter 1 quantizes the analog input signal Vin to generate a first digital code D out1 and the original residual signal Q0, the quantization output result of the second-stage analog-to-digital converter 3 is the second digital code D out2 , the second digital code D out2 The feedback digital code D is generated by the feedback circuit 4 FB, where D FB =D out2 H(z), then feedback digital code D FB After passing through the inverse residual amplifier, the original residual signal Q0 of the first-stage analog-to-digital converter 1 is subtracted to obtain Q1 = Q0-D FB / G, after the residual amplifier 2 amplifies the subtracted signal, it adds the feedback signal back to the output Vo of the residual amplifier 2 to obtain the actual analog input signal Vin2 of the second-stage analog-to-digital converter 3.

[0124] Take the first-order gain error feedback as an example (H(z)=z -1 ), the second digital code D obtained by quantization of the second-stage analog-to-digital converter 3 out2 It is the result of amplification of Q1 at the previous moment. Therefore, the input signal of residual amplifier 2 is a high-pass signal Q1=Q1·(1-z -1 Since the inter-stage gain of the residual amplifier 2 is G(1-Δ), its output Vo will contain two high-pass signal components GQ1·(1-z -1 ) and GQ1Δ·(1-z -1 ), then D out2 ·z -1 Adding back the output Vo of residual amplifier 2 can convert the high-pass GQ1 (1-z -1 ) is restored to a broadband GQ1, while the component with gain error Δ is still in high-pass shape. After combining the quantization results of the first and second stages, the final output can be expressed as:

[0125]

[0126] It can be seen that the quantization leakage error ΔQ1 is shaped and reduced based on the processing function H(z) of the feedback circuit, thereby greatly reducing the impact of the quantization leakage error ΔQ1 on the output target digital signal and improving the analog-to-digital conversion accuracy from the analog input signal to the target digital signal.

[0127] In one possible implementation, Figure 8 A flow chart of the analog-to-digital conversion method provided in the embodiment of the present application is shown in FIG. Figure 8 As shown, the method may include:

[0128] S101: In a working phase of a first-stage analog-to-digital converter, an analog input signal is quantized to generate a first digital code and a first-stage residual signal.

[0129] S102: In the residual amplification stage of the residual amplifier, amplify the first-stage residual signal to obtain an amplified residual signal.

[0130] S103: In the working phase of the second-stage analog-to-digital converter, the amplified residual signal and the feedback signal of the current cycle are added, and quantized to generate a second digital code.

[0131] S104: In the feedback phase of the feedback circuit, the second digital code is processed using a preset feedback function to generate a feedback signal and feed it back to the working phase of the first-stage analog-to-digital converter and the working phase of the second-stage analog-to-digital converter in the next cycle.

[0132] S105: In the coding field of the digital coding circuit, the first digital code and the second digital code are combined to generate a target digital signal corresponding to the analog input signal.

[0133] In this embodiment, during the working phase of the first-stage analog-to-digital converter, the first-stage analog-to-digital converter quantizes the analog input signal Vin to generate a first-stage quantized first digital code D out1 , and at the same time, the first-stage residual signal Q1 is generated. Then, in the residual amplification stage, the first-stage residual signal Q1 is amplified by the residual amplifier with error G(1-Δ) times to obtain the amplified error signal Vo. Then, in the working stage of the second-stage analog-to-digital converter, the amplified error signal Vo is combined with the feedback digital code D FB Generate an analog input signal Vin2 of the second-stage analog-to-digital converter, and quantize the analog-to-digital input signal Vin2 to generate a second-stage quantized second digital code D out2 , in the feedback stage, the second digital code D out2 After the system function H(z) of the feedback circuit is processed, the feedback digital code D is obtained. FB , feedback digital code D FB It will be fed back to the first-stage analog-to-digital converter 1 and the second-stage analog-to-digital converter 3 to shape the gain error in the first-stage residual signal Q1 in the next cycle, and restore the more accurate analog input signal Vin2 in the second-stage converter, thereby improving the accuracy of the target digital signal Dout.

[0134] In some embodiments, Fig. 9 The working timing diagram provided for the embodiment of the present application is as follows: Fig. 9 As shown, the process of quantizing the analog input signal to generate the first digital code and the first-stage residual signal in the working stage of the first-stage analog-to-digital converter in S101 may include:

[0135] In the first sampling stage, the analog input signal is sampled; in the first reset stage, the sampled analog input signal is maintained; in the first quantization stage, the analog input signal is quantized to generate a first digital code and an original residual signal; in the first subtraction stage, the original residual signal and the feedback signal are subtracted to generate a first residual signal.

[0136] Specifically, in the first sampling stage sample1, the analog input signal Vin is sampled, and the analog input signal Vin is stored in all the first capacitors in the form of charges.

[0137] Then, in the first reset stage reset1, the bottom plate of the first capacitor is connected to the preset common mode signal Vcm under the control of the non-overlapping clock signal, and the top plate is disconnected and in a high-impedance state. At this time, the analog input signal Vin is transmitted and maintained to the top plate of the first capacitor.

[0138] Afterwards, in the first quantization stage, the analog input signal Vin is quantized to generate the first data code D out1 , and the first digital code D out1 The first digital code D out1 The corresponding analog signal quantities are subtracted to generate the first-stage original residual signal Q0 at the top plate of the first capacitor.

[0139] Then, in the first stage of multiplication and subtraction sub, if the feedback circuit function is turned on, according to the feedback digital code D provided by the feedback circuit FB , the upper plate of the first capacitor 17 is used to generate the original residual signal Q0 and D FB / G are subtracted to obtain a shaped high-pass first residual signal Q1.

[0140] In some embodiments, the process of adding the amplified residual signal and the feedback signal of the current cycle and quantizing and generating the second digital code in the above S103 during the working stage of the second-stage analog-to-digital converter may include:

[0141] In the second-stage sampling stage, the amplified residual signal is sampled; in the second-stage resetting stage, the sampled amplified residual signal is maintained; in the second-stage adding stage, the amplified residual signal and the feedback signal are added to generate a restored input signal; in the second-stage quantization stage, the restored input signal is quantized to generate a second digital code.

[0142] In this embodiment, in the second sampling stage sample2, the amplified residual signal GQ1 is sampled, and the amplified residual signal GQ1 is stored in all the second capacitors in the form of charges.

[0143] Then, in the second reset stage reset2, the bottom plates of the third capacitor and the fourth capacitor are connected to the preset common mode signal V under the control of the non-overlapping clock signal. cm , the top plates of the fourth capacitor and the fifth capacitor are disconnected and are in a high-impedance state. At this time, the amplified residual signal is transmitted and maintained to the top plate of the third capacitor.

[0144] Afterwards, in the second stage of addition, if the feedback circuit function is turned on, according to the feedback digital code D provided by the feedback circuit FB , the amplified residual signal GQ1 and the feedback digital code D FB The corresponding analog signal quantities are added to restore the original input signal Vin2 of the second-stage analog-to-digital converter.

[0145] In the second quantization stage, the restored input signal Vin2 is quantized to obtain the second digital code D out2 .

[0146] After the second quantization stage, the second digital code D is fed back to the feedback circuit in the error feedback stage fb. out2 .

[0147] The pipelined successive approximation analog-to-digital conversion circuit and method provided in the above-mentioned embodiment, by setting a feedback circuit, processes the digital code output by the second-stage analog-to-digital converter to obtain a feedback digital code, subtracts the feedback digital code from the first-stage analog-to-digital converter, and adds the feedback digital code back to the second-stage analog-to-digital converter to extract the gain error of the residual amplifier and perform a shaping operation so that the gain error is shaped into a high-pass shape. At the same time, a high-precision residual amplifier is used to further reduce the gain error of the residual amplifier, so that the influence of the quantization leakage error after high-pass shaping on the analog input signal bandwidth is greatly reduced, and high-precision signal conversion is achieved under the premise of ensuring high-speed and low power consumption of analog-to-digital conversion.

[0148] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A pipeline successive approximation analog-to-digital conversion circuit, characterized in that: The pipeline successive approximation analog-to-digital conversion circuit comprises: a two-stage analog-to-digital converter, a residual amplifier, a feedback circuit and a digital encoding circuit; An analog input terminal of a first-stage analog-to-digital converter in the two-stage analog-to-digital converter receives an analog input signal, a residual output terminal of the first-stage analog-to-digital converter is connected to an input terminal of a residual amplifier, and an output terminal of the residual amplifier is connected to an analog input terminal of a second-stage analog-to-digital converter in the two-stage analog-to-digital converter; The digital output terminal of the second-stage analog-to-digital converter is connected to the input terminal of the feedback circuit, and the two output terminals of the feedback circuit are respectively connected to the feedback input terminals of the two-stage analog-to-digital converter; The digital output ends of the two-stage analog-to-digital converter are both connected to the digital encoding circuit, and the digital encoding circuit is used to generate a target digital signal corresponding to the analog input signal according to the digital code output by the two-stage analog-to-digital converter.

2. The pipelined successive approximation analog-to-digital conversion circuit according to claim 1, characterized in that: The first-stage analog-to-digital converter includes: a first analog-to-digital conversion unit and an inverse residual amplifier; The analog input terminal of the first analog-to-digital conversion unit serves as the analog input terminal of the first-stage analog-to-digital converter, the input terminal of the inverse residual amplifier serves as the feedback input terminal of the first-stage analog-to-digital converter, the output terminal of the inverse residual amplifier is connected to the feedback input terminal of the first analog-to-digital conversion unit, the residual output terminal of the first analog-to-digital conversion unit serves as the residual output terminal of the first-stage analog-to-digital converter, and the digital output terminal of the first analog-to-digital conversion unit serves as the digital output terminal of the first-stage analog-to-digital converter; The second-stage analog-to-digital converter includes: a second analog-to-digital conversion unit.

3. The pipelined successive approximation analog-to-digital conversion circuit according to claim 2, characterized in that: The first analog-to-digital conversion unit includes: M+1 first capacitors and a first control switch group, a second control switch, a third control switch, a first comparator and a first successive approximation logic circuit, where M is the number of quantization bits of the first-stage analog-to-digital converter; One end of the first M first control switch groups is respectively connected to a positive reference signal, a negative reference signal, a preset common mode signal and the analog input signal, one end of the M+1 first control switch group is respectively connected to the preset common mode signal and the analog input signal, and the other end of the M+1 first control switch group is connected to the bottom plate of the M+1 first capacitor; The top plates of the M+1 first capacitors are connected as the feedback input terminal of the first analog-to-digital conversion unit, and the capacitor connection point thereof is connected to the preset common mode signal through the second control switch; The capacitor connection point is also connected to the third control switch as a residual output terminal of the first analog-to-digital conversion unit; The capacitor connection point is also connected to the positive input terminal of the first comparator, the negative input terminal of the first comparator is connected to the preset common mode signal, the output terminal of the first comparator is connected to the input terminal of the first successive approximation logic circuit, and the output terminal of the first successive approximation logic circuit serves as the digital output terminal of the first analog-to-digital conversion unit; The output end of the first successive approximation logic circuit is also connected to the control ends of the M+1 first control switch groups.

4. The pipelined successive approximation analog-to-digital conversion circuit according to claim 2, characterized in that: The inverse residual amplifier comprises: B+1 second capacitors and a fourth control switch group, wherein the ratio of the total value of the B+1 second capacitors to the sum of the total value of the M+1 first capacitors and the total value of the B+1 second capacitors is the gain of the inverse residual amplifier, and B is the number of feedback bits of the feedback circuit; One end of the first B fourth control switch groups are respectively connected to a positive reference signal, a negative reference signal, a preset common mode signal and an analog input signal, one end of the B+1th fourth control switch group is respectively connected to the preset common mode signal and the analog input signal, and the other end of the B+1th fourth control switch group is connected to the bottom plate of the B+1 second capacitor; The control ends of the B+1 fourth control switch groups serve as input ends of the inverse residual amplifier, and the top plates of the B+1 second capacitors are connected as output ends of the inverse residual amplifier.

5. The pipelined successive approximation analog-to-digital conversion circuit according to claim 2, characterized in that: The second analog-to-digital conversion unit includes: L+1 third capacitors and a fifth control switch group, a sixth control switch group, a seventh control switch, a fourth capacitor, a fifth capacitor, a second comparator, a second successive approximation logic circuit and a first selector, where L is the number of quantization bits of the second-stage analog-to-digital converter; One end of the first L fifth control switch groups is respectively connected to the positive reference signal, the negative reference signal, the preset common mode signal and the output end of the residual amplifier, one end of the L+1th fifth control switch group is respectively connected to the preset common mode signal and the output end of the residual amplifier, and the other end of the L+1th fifth control switch group is connected to the bottom plate of the L+1 third capacitor; One end of the sixth control switch group is connected to the preset common mode signal and the output end of the residual amplifier respectively, and the other end of the sixth control switch group is connected to the bottom plate of the fourth capacitor; The top plates of the L+1 third capacitors are connected to the bottom plate of the fifth capacitor, the top plate of the fifth capacitor is connected to the top plate of the fourth capacitor, and the capacitor connection point is connected to the preset common mode signal through the seventh control switch; The capacitor connection point is also connected to the positive input terminal of the second comparator, the negative input terminal of the second comparator is connected to the preset common mode signal, the output terminal of the second comparator is connected to the input terminal of the second successive approximation logic circuit, and the output terminal of the second successive approximation logic circuit serves as the digital output terminal of the second-stage analog-to-digital converter; The output end of the second successive approximation logic circuit is connected to the first input end of the first selector, and the second input end of the first selector serves as the feedback input end of the second-stage analog-to-digital converter; The output end of the first selector is connected to the control ends of the fifth control switch group and the sixth control switch group.

6. The pipelined successive approximation analog-to-digital conversion circuit according to claim 1, characterized in that: The residual amplifier comprises: an amplifier, two sixth capacitors, two seventh capacitors, a plurality of first phase switches, a plurality of second phase switches, a plurality of second phase first sub switches and a plurality of second phase second sub switches; The residual output end of the first-stage analog-to-digital converter is respectively connected to the positive input end and the negative input end of the amplifier through two second phase switches, and the positive input end and the negative input end of the amplifier are also respectively connected to a preset common-mode signal through two first phase switches; The positive output terminal and the negative output terminal of the amplifier are respectively connected to the top plates of the two sixth capacitors through two second-phase first sub-switches, the positive output terminal and the negative output terminal of the amplifier are respectively connected to the bottom plates of the two sixth capacitors through two second-phase second sub-switches, and the bottom plates of the two sixth capacitors are also respectively connected to the preset common-mode signal through two second-phase first sub-switches; The positive input terminal of the amplifier is connected to the top plate of the sixth capacitor at the negative output terminal through a seventh capacitor, and the negative input terminal of the amplifier is connected to the top plate of the sixth capacitor at the positive output terminal through another seventh capacitor; The two seventh capacitors are further connected via a first phase switch, and the two seventh capacitors are further connected to the preset common mode signal via two first phase switches respectively; The two seventh capacitors are connected as output terminals of the residual amplifier.

7. The pipelined successive approximation analog-to-digital conversion circuit according to claim 6, characterized in that: The amplifier is a gain-enhanced telescopic cascode amplifier.

8. The pipelined successive approximation analog-to-digital conversion circuit according to claim 1, characterized in that: The feedback circuit includes: a plurality of D flip-flops, a plurality of gain error feedback modules with increasing orders, and a second selector; The input end of the first D flip-flop serves as the input end of the feedback circuit, multiple D flip-flops are connected in series in sequence, the input end of the i-th order gain error feedback module is connected to the output end of the first i D flip-flops, the output ends of the multiple gain error feedback modules are respectively connected to the multiple input ends of the second selector, and the output end of the second selector serves as the output end of the feedback circuit; The clock terminals of the plurality of D flip-flops are used to receive a clock signal.

9. An analog-to-digital conversion method, characterized in that: Applied to the pipelined successive approximation analog-to-digital conversion circuit according to any one of claims 1 to 8, the method comprising: In the working stage of the first-stage analog-to-digital converter, the analog input signal is quantized to generate a first digital code and a first-stage residual signal; In the residual amplification stage of the residual amplifier, the first-stage residual signal is amplified to obtain an amplified residual signal; In the working stage of the second-stage analog-to-digital converter, the amplified residual signal and the feedback signal of the current cycle are added and quantized to generate a second digital code; In the feedback phase of the feedback circuit, the second digital code is processed by a preset feedback function to generate a feedback signal and feed it back to the working phase of the first-stage analog-to-digital converter and the working phase of the second-stage analog-to-digital converter in the next cycle; In the coding field of the digital coding circuit, the first digital code and the second digital code are combined to generate a target digital signal corresponding to the analog input signal.

10. The method according to claim 9, characterized in that In the working stage of the first-stage analog-to-digital converter, the analog input signal is quantized to generate a first digital code and a first-stage residual signal, including: In the first sampling stage, the analog input signal is sampled; In the first reset stage, the sampled analog input signal is held; In the first quantization stage, the analog input signal is quantized to generate the first digital code and the original residual signal; In the first-stage subtraction stage, the original residual signal and the feedback signal are subtracted to generate the first-stage residual signal.

11. The method according to claim 9, characterized in that In the working stage of the second-stage analog-to-digital converter, the amplified residual signal and the feedback signal of the current cycle are added, and quantized to generate a second digital code, including: In the second sampling stage, the amplified residual signal is sampled; In the second stage reset phase, the sampled amplified residual signal is maintained; In the second stage of addition, the amplified residual signal and the feedback signal are added to generate a restored input signal; In the second-level quantization stage, the restored input signal is quantized to generate the second digital code.

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