Self-aligned shield gate double-epitaxial super-junction IGBT and manufacturing method thereof

Abstract

The invention discloses a self-aligned shield gate double-epitaxial super-junction IGBT and a manufacturing method, and the IGBT comprises a semiconductor layer disposed on a substrate, and the semiconductor layer is internally provided with a source region and a body region which are distributed from the surface to the substrate; a plurality of pairs of side walls arranged on the surface of the semiconductor layer; the gate trench is arranged below the surface of the semiconductor layer between each pair of side walls, and a gate oxide layer and a gate electrode are arranged in the gate trench; the super junction trench is arranged below the surface of the semiconductor layer between two adjacent pairs of side walls, a first epitaxial layer of a first conductive type is arranged on the inner wall of the super junction trench, a second epitaxial layer of a second conductive type is arranged in the first epitaxial layer, and the first epitaxial layer and the second epitaxial layer are connected with the body region through the top. According to the invention, the area of the device can be reduced while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a self-aligned shielded gate dual epitaxial super junction IGBT and a manufacturing method thereof. Background Art

[0002] Compared with planar MOSFET, super junction (SJ) MOSFET has the characteristics of low on-resistance, fast switching speed, small chip size and low heat generation. Super junction has smaller junction capacitance. For super junction MOSFET, the reduction of resistance will bring obvious benefits, such as lower conduction loss or smaller die at the same on-resistance (Ron). In addition, the reduction of chip area will lead to lower junction capacitance and gate and output charge, which can reduce dynamic loss. Using the super junction MOSFET structure, super junction IGBT devices can be further formed.

[0003] However, as the device area continues to shrink, the number of processing steps and the number of masks in the manufacturing process also increase, which undoubtedly increases the manufacturing cost. In addition, due to the existence of overlay error, the short-circuit resistance also increases.

[0004] At the same time, how to improve charge balance, further increase voltage resistance, reduce on-resistance, avoid avalanche breakdown and reduce parasitic capacitance have also become important topics for continuous improvement. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a self-aligned shielded gate dual epitaxial super junction IGBT and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a self-aligned shielded gate dual epitaxial super junction IGBT, comprising:

[0008] A semiconductor layer disposed on the front side of the substrate, wherein the semiconductor layer is provided with a source region and a body region distributed in sequence from the surface of the semiconductor layer toward the substrate;

[0009] A plurality of pairs of side walls are arranged in parallel on the surface of the semiconductor layer;

[0010] A gate trench is provided below the surface of the semiconductor layer between each pair of the sidewalls, wherein a shielding gate and a gate are provided in the gate trench from bottom to top;

[0011] A super junction trench is provided below the surface of the semiconductor layer between two adjacent pairs of the sidewalls, a first epitaxial layer of a first conductivity type is provided on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is provided in the super junction trench within the first epitaxial layer, and the first epitaxial layer and the second epitaxial layer are connected to the body region through the top facing the surface of the semiconductor layer;

[0012] A collector region layer and a buffer region layer are sequentially arranged below the back surface of the substrate.

[0013] Further, a drift region of the first conductivity type is provided in the semiconductor layer, and the body region of the second conductivity type, the source region of the first conductivity type, the first epitaxial layer and the second epitaxial layer are located in the drift region; or, the semiconductor layer is an intrinsic semiconductor layer.

[0014] Further, bottoms of the super junction trench and the gate trench pass through the source region and the body region and are located in the semiconductor layer, and a depth of the super junction trench is greater than a depth of the gate trench.

[0015] Further, the first epitaxial layer and the second epitaxial layer are connected to the body region through a first transition connection region of the second conductivity type provided on the top facing the surface of the semiconductor layer; and / or, a second transition connection region of the first conductivity type surrounding the super junction trench and connecting the first epitaxial layer and the body region is also provided in the semiconductor layer below the body region; and / or, the second epitaxial layer has a gradient doping concentration inward along the inner wall of the super junction trench.

[0016] Furthermore, it also includes: a metal layer arranged on the surface of the semiconductor layer; an interlayer dielectric layer, a metal interconnect layer and a passivation layer arranged in sequence on the surface of the metal layer; and a collector layer arranged on the back surface of the substrate; the metal layer includes a gate metal separated between each pair of the side walls and connected to the gate, and a source contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and the interlayer dielectric layer is located on the top of the gate metal, the top of the source contact metal and the top of the side walls.

[0017] The present invention also provides a method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT, comprising:

[0018] providing a substrate, and forming a semiconductor layer on a front surface of the substrate;

[0019] Forming a source region of a first conductivity type and a body region of a second conductivity type in the semiconductor layer, which are distributed in sequence from the surface of the semiconductor layer toward the substrate;

[0020] Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer;

[0021] The second hard mask layer pattern is removed, and then, sidewalls are formed on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern, respectively, so as to form a pair of sidewalls formed by two sidewalls on adjacent sides between two adjacent first hard mask layer patterns and the third hard mask layer patterns;

[0022] Forming a gate trench passing through the source region and the body region below the surface of the semiconductor layer between each pair of the sidewalls, and forming a shielding gate and a gate from bottom to top in the gate trench;

[0023] forming a fourth hard mask layer pattern between each pair of the spacers, and then removing the first hard mask layer pattern and the third hard mask layer pattern;

[0024] A super junction trench passing through the source region and the body region is formed below the surface of the semiconductor layer between two adjacent pairs of the sidewalls, a first epitaxial layer of a first conductivity type is formed on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is filled in the super junction trench within the first epitaxial layer, and then, by back etching, the tops of the first epitaxial layer and the second epitaxial layer are made lower than the surface of the semiconductor layer;

[0025] forming a first transition connection region of a second conductivity type connected to the body region on top of the first epitaxial layer and the second epitaxial layer, and then removing the fourth hard mask layer pattern;

[0026] Also includes:

[0027] The back side of the substrate is thinned, and a collector region layer and a buffer region layer are sequentially formed below the back side surface of the thinned substrate.

[0028] Further, forming a plurality of first hard mask layer patterns on the surface of the semiconductor layer, contacting second hard mask layer patterns located on both sides of the first hard mask layer patterns, and contacting a third hard mask layer pattern between two of the second hard mask layer patterns located on adjacent sides, specifically includes:

[0029] Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer;

[0030] Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns on adjacent sides;

[0031] A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form a third hard mask layer pattern that contacts two of the second hard mask layer patterns located on adjacent sides and exposes the tops of the first hard mask layer pattern and the second hard mask layer pattern.

[0032] Furthermore, by sequentially forming a plurality of second sub-epitaxial layers of the second conductivity type having a gradient doping concentration in the super junction trench within the first epitaxial layer, the second epitaxial layer formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench; and / or, by forming an implantation window between two adjacent pairs of the side walls and by ion implantation, the first transition connection region is formed on top of the first epitaxial layer and the second epitaxial layer; and / or, by forming an implantation window between two adjacent pairs of the side walls and by pocket ion implantation, a second transition connection region of the first conductivity type surrounding the super junction trench is formed in the semiconductor layer below the body region.

[0033] Further, a semiconductor layer of the first conductivity type is formed on the surface of the substrate to form a drift region of the first conductivity type in the semiconductor layer, and the body region, the source region, the first epitaxial layer and the second epitaxial layer are formed in the drift region; or, an intrinsic semiconductor layer is formed on the surface of the substrate.

[0034] Furthermore, after removing the fourth hard mask layer pattern, it also includes: filling metal layer material in the gap between each of the side walls, and removing excess metal layer material on the top surface of the side wall, forming a gate metal separated between each pair of the side walls and connected to the gate, and a source region contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, thereby forming a metal layer; forming an interlayer dielectric layer on the top of the metal layer and the top of the side wall; forming a metal interconnect layer and a passivation layer in sequence on the surface of the interlayer dielectric layer; and including: forming a collector layer on the back surface of the substrate after forming the collector region layer and the buffer layer.

[0035] It can be seen from the above technical scheme that the present invention can reduce the photomask while reducing the pitch by adopting multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern to the third hard mask layer pattern and the sidewall), so that the MOSFET device has a smaller tube core area, further reducing the resistance per square area, increasing the current density, and significantly reducing the cost; at the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced; in this way, by removing the second hard mask layer pattern and the first hard mask layer pattern and the third hard mask layer pattern in steps, and using the formed sidewall structure, the super junction trench can be accurately self-aligned between adjacent gate trenches to effectively reduce the resistance and increase the switching speed. In addition, by adding the first epitaxial layer of the first conductivity type in the super junction trench, the doping concentration and thickness of the second epitaxial layer of the second conductivity type and the first epitaxial layer can be easily controlled to achieve a perfect charge balance. In this way, the drift region of the first conductivity type that is originally required to be formed by forming a semiconductor layer of the first conductivity type can be omitted by increasing the doping concentration of the first epitaxial layer, and thus the semiconductor layer of the first conductivity type can be directly changed to an intrinsic semiconductor layer, thereby improving the withstand voltage while reducing the on-resistance. At the same time, the shielded gate trench (SGT) structure formed also plays a role in avoiding avalanche breakdown and reducing parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic structural diagram of a self-aligned shielded gate dual epitaxial superjunction IGBT according to a preferred embodiment of the present invention;

[0037] Figure 2-Figure 10 The present invention is a process flow chart of a method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0039] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various materials that can conduct electricity, such as metal, doped polysilicon layer, or a stacked gate conductor including a metal and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate dielectric (gate oxide layer) may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.

[0040] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type may be formed by implanting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by implanting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0041] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0042] refer to Figure 1 A self-aligned shielded gate dual epitaxial superjunction IGBT of the present invention comprises a substrate 10, a semiconductor layer 23 disposed on the front surface (the upper surface in the figure) of the substrate 10, and a collector layer 25 and a buffer layer 24 disposed below (inside) the back surface of the substrate 10 in sequence.

[0043] The semiconductor layer 23 is provided with a source region 13 of a first conductivity type and a body region 12 of a second conductivity type which are sequentially distributed from the surface of the semiconductor layer 23 toward the substrate 10 .

[0044] A plurality of pairs of sidewalls 15 are arranged in parallel on the surface of the semiconductor layer 23, and each pair of sidewalls 15 is provided with two sidewalls 151. Each pair of sidewalls 15 can be vertically arranged on the surface of the semiconductor layer 23, and the two sidewalls 151 in each pair of sidewalls 15 are spaced apart by a certain first distance L, and any two adjacent pairs of sidewalls 15 (i.e., the two sidewalls 151 located on adjacent (close) sides of the two adjacent pairs of sidewalls 15) are also spaced apart by a certain second distance H. The first distance L and the second distance H can be adjusted according to the process design.

[0045] A gate trench 31 extending from the surface of the semiconductor layer 23 downward into the semiconductor layer 23 is disposed between the two sidewalls 151 in each pair of sidewalls 15. In addition, the bottom of the gate trench 31 may sequentially pass through the source region 13 and the body region 12 and be located in the semiconductor layer 23. The width of the gate trench 31 is determined by the first distance L between the pair of sidewalls 15.

[0046] The gate trench 31 is provided with a shielding gate 30 , an isolation layer 29 and a gate 28 from bottom to top. A gate oxide layer 27 is formed between the shielding gate 30 and the inner wall of the gate trench 31 , and between the gate 28 and the inner wall of the gate trench 31 and the isolation layer 29 .

[0047] At the same time, a super junction trench 36 extending from the surface of the semiconductor layer 23 downward into the semiconductor layer 23 is respectively provided between any two adjacent pairs of sidewalls 15. In addition, the bottom of the super junction trench 36 can sequentially pass through the source region 13 and the body region 12 and be located in the semiconductor layer 23. The width of the super junction trench 36 is determined by the second distance H between the two adjacent pairs of sidewalls 15.

[0048] refer to Figure 1 A first epitaxial layer 35 of the first conductivity type is provided on the inner wall of the super junction trench 36; a second epitaxial layer 34 of the second conductivity type is filled in the super junction trench 36 within the first epitaxial layer 35. The first epitaxial layer 35 and the second epitaxial layer 34 are used to form a double epitaxial super junction. The first epitaxial layer 35 and the second epitaxial layer 34 are connected to the body region 12 through the top 331 facing the surface of the semiconductor layer 23.

[0049] The super junction trench 36 is formed between every two adjacent gate trenches 31 in a self-aligned manner through the openings (having a second distance H) between every two pairs of adjacent spacers 15 .

[0050] The following description is made by taking the case where the first conductivity type is N type and the second conductivity type is P type as an example.

[0051] refer to Figure 1 In some embodiments, the substrate 10 may be a heavily doped N+ type silicon substrate 10 (N+ substrate) of the first conductivity type.

[0052] In some embodiments, the semiconductor layer 23 may be an epitaxial N-type silicon semiconductor layer 23 of the first conductivity type disposed on the surface of the substrate 10, and an epitaxial N-type drift region 11 (N driftEPI) of the first conductivity type is formed in the semiconductor layer 23. The body region 12, the source region 13, the first epitaxial layer 35, and the second epitaxial layer 34 are formed in the drift region 11.

[0053] In some embodiments, the depth of the super junction trench 36 below the surface of the semiconductor layer 23 is greater than the depth of the gate trench 31 below the surface of the semiconductor layer 23. For example, the bottom of the super junction trench 36 may be located at the interface between the semiconductor layer 23 and the substrate 10 (i.e., located on the surface of the substrate 10), and the bottom of the gate trench 31 may be located in the semiconductor layer 23 above the bottom of the super junction trench 36, and may maintain a certain distance from the substrate 10.

[0054] The body region 12 may be a lightly doped P-type body region 12 (P-body) of the second conductivity type.

[0055] The source region 13 may be a heavily doped N+ type source region 13 of the first conductivity type.

[0056] The first epitaxial layer 35 may be a first conductivity type, medium-doped N-type silicon first epitaxial layer 35 (NEPI).

[0057] The second epitaxial layer 34 may be a P-type silicon second epitaxial layer 34 (PEPI) doped with a second conductivity type.

[0058] In some embodiments, the second epitaxial layer 34 has a gradient doping concentration along the inner wall of the super junction trench 36 toward the inside of the super junction trench 36 .

[0059] In some embodiments, the second epitaxial layer 34 is composed of multiple second sub-epitaxial layers formed sequentially in the super junction trench 36 within the first epitaxial layer 35, and each second sub-epitaxial layer has a different doping concentration, thereby forming a second epitaxial layer 34 with a gradient doping concentration along the inner wall of the super junction trench 36 toward the inside of the super junction trench 36.

[0060] In some embodiments, since an N-type first epitaxial layer 35 is added between the N-type drift region 11 and the P-type second epitaxial layer 34 in the super junction trench 36, the doping concentration and thickness of the P-type second epitaxial layer 34 and the N-type first epitaxial layer 35 can be easily controlled to achieve a perfect charge balance, so that the N-type semiconductor layer 23 with the N-type drift region 11 can be directly changed to the intrinsic semiconductor layer 23 by increasing the doping concentration of the first epitaxial layer 35, thereby eliminating the need to set the drift region 11 in the intrinsic semiconductor layer 23. In this way, the on-resistance can be reduced while the withstand voltage is increased.

[0061] In some embodiments, the top 331 of the first epitaxial layer 35 and the second epitaxial layer 34 facing the surface of the semiconductor layer 23 is lower than the surface of the semiconductor layer 23 by a certain distance, and the first epitaxial layer 35 and the second epitaxial layer 34 are connected to the body region 12 exposed at the sidewall of the super junction trench 36 through the first transition connection region 33 of the second conductivity type provided on the top 331 facing the surface of the semiconductor layer 23. The first transition connection region 33 can be a heavily doped P+ type first transition connection region 33 of the second conductivity type to increase the P-type doping concentration in the top region of the second epitaxial layer 34 and improve the dynamic reliability of the formed device.

[0062] In some embodiments, a second transition connection region 32 of the first conductivity type surrounding the super junction trench 36 is further provided in the semiconductor layer 23 below the body region 12. In addition, the second transition connection region 32 is connected to the side of the first epitaxial layer 35 located in the super junction trench 36 and the bottom of the body region 12. The second transition connection region 32 can be a medium-doped N-type second transition connection region 32 of the first conductivity type to reduce the resistance of the region.

[0063] In some embodiments, the bottom of the gate 28 away from the surface of the semiconductor layer 23 is located below the bottom of the body region 12 .

[0064] In some embodiments, the gate oxide layer 27 may include a first gate oxide layer 271 disposed between the shield gate 30 and the inner wall of the gate trench 31 , and a second gate oxide layer 272 disposed between the gate 28 and the inner wall of the gate trench 31 and the isolation layer 29 .

[0065] In some embodiments, the shield gate 30 may be a heavily doped N+ type polysilicon shield gate 30 (poly 1) of a first conductivity type.

[0066] The gate 28 may be a heavily doped N+ type polysilicon gate 28 (Gate poly2) of the first conductivity type.

[0067] The gate oxide layer 27 (Gate OX) may be made of silicon dioxide.

[0068] The material of the isolation layer 29 may be tetraethyl orthosilicate oxide (ie, CVD oxide using tetraethyl orthosilicate TEOS precursor, referred to as TEOS OX), but is not limited thereto.

[0069] In some embodiments, the gate 28 and the top of the gate oxide layer 27 may protrude above the surface of the semiconductor layer 23 and be located between the pair of spacers 15 .

[0070] In some embodiments, a metal layer 18 is further provided on the surface of the semiconductor layer 23 between each pair of sidewalls 151. The metal layer 18 includes a gate metal 16 that fills and separates between each pair of sidewalls 15 and connects to the gate 28, and a source region contact metal 17 that is separated between two adjacent pairs of sidewalls 15 and connects to the source region 13, the body region 12, the first epitaxial layer 35, and the second epitaxial layer 34 (connected through the first transition connection region 33). That is, the gate metal 16 in the metal layer 18 is isolated from the source region contact metal 17 by the sidewalls 151.

[0071] In some embodiments, the sidewall spacer 151 may be formed of a dielectric material.

[0072] In some embodiments, the gate metal 16 and the source contact metal 17 materials (metal layer 18 materials) include at least one of Au, Ag, Pt, Al, and W.

[0073] Adhesion layers (not shown) may be provided respectively between the gate metal 16 and the sidewall 151 and the top of the gate 28 (including the gate oxide layer 27), and between the source contact metal 17 and the sidewall 151, the exposed sidewall of the super junction trench 36 and the top of the first transition connection region 33. The adhesion layer material includes at least one of Ti, TiN and TaN.

[0074] refer to Figure 1 In some embodiments, an interlayer dielectric layer 14 is further disposed on the surface of the metal layer 18 . The interlayer dielectric layer 14 is located on the top of the gate metal 16 , the top of the source region contact metal 17 , and the top of each spacer 151 .

[0075] In some embodiments, a metal interconnection layer 21 may be further provided on the interlayer dielectric layer 14. The gate 28 may be interconnected with the metal interconnection layer 21 through the gate metal 16 and the conductive contact hole 22 provided in the interlayer dielectric layer 14; the source region 13, the body region 12, the first epitaxial layer 35 and the second epitaxial layer 34 (the first transition connection region 33) may be interconnected with the metal interconnection layer 21 through the source region contact metal 17 and the conductive contact hole 22 provided in the interlayer dielectric layer 14.

[0076] In some embodiments, a dielectric passivation layer 20 (Passivation) may be further provided on the metal interconnection layer 21; a pad window 19 connected to the metal interconnection layer 21 may be provided on the surface of the passivation layer 20 for forming a pad (not shown).

[0077] refer to Figure 1 In some embodiments, the collector region layer 25 is located below (inside) the back surface of the substrate 10, and the buffer layer 24 is further located in the substrate 10 below (inside) the collector region layer 25. The collector region layer 25 may be a heavily doped P+ type collector region layer 25; and the buffer layer 24 may be a heavily doped N+ type buffer layer 24.

[0078] In some embodiments, a collector layer 26 is further disposed on the back surface of the substrate 10 ; the collector layer 26 is in contact with the collector region layer 25 .

[0079] In some embodiments, the collector layer 26 material includes at least one of Al, Ti, NiV, and Ag.

[0080] A method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT of the present invention is described in detail below through specific implementation modes and in conjunction with the accompanying drawings.

[0081] refer to Figure 2-Figure 10 The self-aligned shielded gate dual epitaxial superjunction IGBT manufacturing method of the present invention can be used to manufacture the above-mentioned Figure 1 A self-aligned shielded gate dual epitaxial super junction IGBT of the present invention may include the following steps:

[0082] Step S1 : providing a substrate 10 , and forming a semiconductor layer 23 on the front surface of the substrate 10 .

[0083] like Figure 2 As shown, a heavily doped N+ silicon substrate 10 (N+ substrate) can be used, and an N-type epitaxial silicon semiconductor layer 23 is formed on the front side (the upper surface is shown) of the silicon substrate 10, and an epitaxial N-type drift region 11 (N driftEPI) is also formed.

[0084] Step S2 : forming a source region 13 of the first conductivity type and a body region 12 of the second conductivity type in the semiconductor layer 23 , which are sequentially distributed from the surface of the semiconductor layer 23 toward the substrate 10 .

[0085] like Figure 2 As shown, an ion implantation process may be used to implant P-type light doping into the semiconductor layer 23 from the surface of the semiconductor layer 23 to form a P-type body region 12 of the second conductivity type.

[0086] Next, an ion implantation process may be used to implant N+ type heavy doping into the semiconductor layer 23 from the surface of the semiconductor layer 23 , so as to form an N+ type source region 13 of the first conductivity type below the surface of the semiconductor layer 23 above the body region 12 .

[0087] Step S3: forming a plurality of first hard mask layer patterns 37, second hard mask layer patterns 38 contacting both sides of the first hard mask layer patterns 37, and third hard mask layer patterns 39 contacting between two second hard mask layer patterns 38 on adjacent sides on the surface of the semiconductor layer 23.

[0088] like Figure 2As shown, a first hard mask layer material may be deposited on the surface of the semiconductor layer 23. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 37 (HM1) are formed on the surface of the semiconductor layer 23 through photolithography and etching patterning processes. Figure 2 FIG. 2 exemplarily shows that two first hard mask layer patterns 37 are formed, but the present invention is not limited thereto. Afterwards, the photoresist remaining on the first hard mask layer patterns 37 is removed.

[0089] The first hard mask layer material may be a conventional hard mask layer material, for example, the first hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0090] like Figure 3 As shown, a conformal CVD process can be used to form a second hard mask layer on the surface of the semiconductor layer 23 to cover the first hard mask layer pattern 37. Then, the second hard mask layer is back-etched to form a second hard mask layer pattern 38 (HM2) on both sides of each first hard mask layer pattern 37, which is in contact with the side surface of the first hard mask layer pattern 37, and exposes the top of the first hard mask layer pattern 37 and the two second hard mask layer patterns 38 located on the adjacent sides (i.e., located at Figure 3 The surface of the semiconductor layer 23 between two second hard mask layer patterns 38 inside two adjacent first hard mask layer patterns 37 is shown.

[0091] When the second hard mask layer is deposited, the thickness during deposition can be controlled to reserve a width for subsequent deposition of the third hard mask layer.

[0092] The second hard mask layer material may be a conventional hard mask layer material, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0093] like Figure 3 As shown, a deposition process may be used to form a third hard mask layer on the surface of the semiconductor layer 23, covering the first hard mask layer pattern 37 and the second hard mask layer pattern 38, and completely filling the gap between the two second hard mask layer patterns 38 on the adjacent sides. Then, the third hard mask layer material may be etched back to form a third hard mask layer pattern 39 (HM3) in contact with the side surface of the second hard mask layer pattern 38 between the two second hard mask layer patterns 38 on the adjacent sides, and expose the tops of the first hard mask layer pattern 37 and the second hard mask layer pattern 38.

[0094] By conformally forming a second hard mask layer on the first hard mask layer pattern 37 and back-etching to form a second hard mask layer pattern 38 on both sides of the first hard mask layer pattern 37, a third hard mask layer pattern 39 can be self-aligned between the second hard mask layer patterns 38, thereby achieving a reduction in pitch while saving one photomask.

[0095] The third hard mask layer material may be a conventional hard mask layer material, for example, the third hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0096] Step S4: remove the second hard mask layer pattern 38, and then form sidewalls 151 on both sides of the first hard mask layer pattern 37 and on both sides of the third hard mask layer pattern 39, respectively, to form a pair of sidewalls 15 formed by two sidewalls 151 on adjacent sides between two adjacent first hard mask layer patterns 37 and third hard mask layer patterns 39.

[0097] like Figure 4 As shown, the second hard mask layer pattern 38 can then be removed using different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material to expose the surface of the semiconductor layer 23 located between the first hard mask layer pattern 37 and the third hard mask layer pattern 39.

[0098] like Figure 4 As shown, next, a spacer 151 material is deposited on the surface of the semiconductor layer 23 exposed between the first hard mask layer pattern 37 and the third hard mask layer pattern 39, and the first hard mask layer pattern 37 and the third hard mask layer pattern 39 are covered. Then, a spacer process is adopted and back-etching is performed to form a spacer 151 (Spacer) structure on both sides of each first hard mask layer pattern 37 and each third hard mask layer pattern 39. Among them, a pair of spacers 15 is formed by the spacers 151 on two adjacent sides between the adjacent first hard mask layer pattern 37 and the third hard mask layer pattern 39.

[0099] The material of the spacer 151 may be a conventional spacer material having different etching selectivities with the material of the first hard mask layer and the material of the third hard mask layer.

[0100] Step S5 : forming a gate trench 31 passing through the source region 13 and the body region 12 below the surface of the semiconductor layer 23 between each pair of spacers 15 , and forming a shielding gate 30 and a gate 28 from bottom to top in the gate trench 31 .

[0101] like Figure 4As shown, then, using the combined pattern of the first hard mask layer pattern 37 and the side walls 151 on both sides, and the combined pattern of the third hard mask layer pattern 39 and the side walls 151 on both sides as a common mask, etching is performed downward on the surface of the semiconductor layer 23 exposed between each pair of side walls 15 to form a plurality of parallel deep trenches serving as gate trenches 31 in the semiconductor layer 23, and the bottom end of the gate trench 31 passes through the source region 13 and the body region 12 in sequence and is located in the semiconductor layer 23 (i.e., the area where the drift region 11 is located).

[0102] Then, a first gate oxide layer 271 material is deposited on the inner wall surface of the gate trench 31, and a shielding gate 30 material is further filled in the gate trench 31 within the first gate oxide layer 271 material, until the gap between each pair of side walls 15 is filled, so that the shielding gate 30 material covers the first gate oxide layer 271 material.

[0103] Next, the shielding gate 30 material may be etched back to form a first gate oxide layer 271 on the inner wall of the gate trench 31 , and the shielding gate 30 may be formed in the lower portion of the gate trench 31 within the first gate oxide layer 271 .

[0104] When etching back the material of the shielding gate 30 , the etching back time can be controlled so that the top of the shielding gate 30 is located in the semiconductor layer 23 below the body region 12 .

[0105] Then, the isolation layer 29 material is continuously filled in the gate trench 31 , and is etched back to form the isolation layer 29 on the top surface of the shielding gate 30 .

[0106] When etching back the isolation layer 29 material, the etching back time can be controlled so that the top of the isolation layer 29 is located in the semiconductor layer 23 below the body region 12 .

[0107] like Figure 5 As shown, next, a second gate oxide layer 272 material is deposited on the inner wall of the gate trench 31 above the isolation layer 29, and then the gate 28 material is continued to be filled in the remaining upper portion of the gate trench 31 within the second gate oxide layer 272, and back-etching is performed to form a second gate oxide layer 272 on the side wall of the gate trench 31 above the isolation layer 29, and a gate 28 is formed in the remaining upper portion of the gate trench 31 on the isolation layer 29.

[0108] When etching back the gate 28 material, the etching back time can be controlled so that the top of the gate 28 and the second gate oxide layer 272 protrude above the surface of the semiconductor layer 23 and are located between a pair of side walls 15, even if the top of the gate 28 and the second gate oxide layer 272 are located below the top of the pair of side walls 15.

[0109] Meanwhile, the bottom of the gate 28 can be formed to be located in the semiconductor layer 23 below the body region 12 by controlling the deposition thickness of the isolation layer 29 material.

[0110] The first gate oxide layer 271 and the second gate oxide layer 272 in the gate trench 31 constitute a gate oxide layer 27 .

[0111] The shield gate 30 and the gate 28 may be made of heavily doped N+ type polysilicon.

[0112] It can be seen that when forming the side wall 151, the horizontal width of the side wall 151 formed by back etching can be adjusted by controlling the deposition thickness of the side wall 151 material, so as to adjust the spacing between a pair of side walls 15 located between two adjacent first hard mask layer patterns 37 and third hard mask layer patterns 39, thereby achieving the adjustment of the horizontal width of the gate trench 31 formed by etching later.

[0113] Step S6: forming a fourth hard mask layer pattern 40 between each pair of spacers 15, and then removing the first hard mask layer pattern 37 and the third hard mask layer pattern 39;

[0114] like Figure 5 As shown, then, the fourth hard mask layer material can be filled between each pair of spacers 15 through a deposition process to cover the spacers 151, the first hard mask layer pattern 37 and the third hard mask layer pattern 39. Then, the fourth hard mask layer is etched back to remove the excess fourth hard mask layer material on the top surfaces of the spacers 151, the first hard mask layer pattern 37 and the third hard mask layer pattern 39, thereby forming a fourth hard mask layer pattern 40 (HM4) located between a pair of spacers 15 and covering the gate 28 and the gate oxide layer 27.

[0115] The fourth hard mask layer material includes tetraethyl orthosilicate oxide (ie, CVD oxide using tetraethyl orthosilicate TEOS precursor, TEOS OX for short), but is not limited thereto.

[0116] like Figure 6 As shown, then, the third hard mask layer pattern 39 and the first hard mask layer pattern 37 are removed by etching back.

[0117] Step S7: A super junction trench 36 passing through the source region 13 and the body region 12 is formed below the surface of the semiconductor layer 23 between two adjacent pairs of side walls 15, a first epitaxial layer 35 of a first conductivity type is formed on the inner wall of the super junction trench 36, and a second epitaxial layer 34 of a second conductivity type is filled in the super junction trench 36 within the first epitaxial layer 35. Then, by back etching, the tops 331 of the first epitaxial layer 35 and the second epitaxial layer 34 are made lower than the surface of the semiconductor layer 23.

[0118] like Figure 6As shown, next, the fourth hard mask layer pattern 40 and the combined pattern of the sidewalls 151 on both sides thereof are used as a common mask to perform etching downward on the surface of the semiconductor layer 23 between two adjacent pairs of sidewalls 15, so as to form a super junction trench 36 passing through the source region 13 and the body region 12 in the semiconductor layer 23. The bottom of the super junction trench 36 can be located on the surface of the substrate 10 by etching.

[0119] Next, an N-type silicon first epitaxial layer 35 is first formed on the inner wall of the super junction trench 36 by using a doping epitaxial process. Then, the epitaxial process is continued to be used to fill the super junction trench 36 within the formed first epitaxial layer 35 to form a P-type silicon second epitaxial layer 34, and the super junction trench 36 is filled. When the second epitaxial layer 34 is formed by epitaxy, a plurality of P-type silicon second sub-epitaxial layers can be sequentially formed in the super junction trench 36 within the first epitaxial layer 35, and a gradient doping concentration can be provided between each second sub-epitaxial layer, so that the second epitaxial layer 34 formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench 36, thereby forming a second epitaxial layer 34 with a doping concentration gradient.

[0120] In other embodiments, an undoped epitaxial process may be used to first form an undoped silicon second epitaxial layer 34, and then, through multiple steps of ion implantation with different doping doses, a P-type silicon second epitaxial layer 34 having a doping concentration gradient inwardly along the inner wall of the super junction trench 36 is formed.

[0121] Next, the first epitaxial layer 35 and the second epitaxial layer 34 may be etched back so that the top 331 of the first epitaxial layer 35 and the second epitaxial layer 34 is lower than the surface of the semiconductor layer 23 (i.e., lower than the top surface of the super junction trench 36) to form a super junction. By controlling the etch-back time, the top 331 of the first epitaxial layer 35 and the second epitaxial layer 34 may be located at a height position below the bottom of the source region 13, so that the source region 13 is exposed on the side wall of the super junction trench 36.

[0122] Step S8: forming a first transition connection region 33 of a second conductivity type connected to the body region 12 on the top 331 of the first epitaxial layer 35 and the second epitaxial layer 34, and then removing the fourth hard mask layer pattern 40.

[0123] like Figure 7 As shown, by utilizing the implantation window formed between two adjacent pairs of sidewalls 15 and adopting a pocket implant process, an N-type ion implantation region surrounding the super junction trench 36 is formed in the semiconductor layer 23 below the body region 12 to form a second transition connection region 32.

[0124] Then, the implantation window formed between two adjacent pairs of side walls 15 is utilized again, and an ion implantation process is adopted to form a heavily doped P+ type ion implantation region on the top 331 of the first epitaxial layer 35 and the second epitaxial layer 34 exposed in the super junction trench 36, as the first transition connection region 33, and the first transition connection region 33 is connected to the body region 12 exposed on the side wall of the super junction trench 36.

[0125] Then, the fourth hard mask layer pattern 40 is removed by etching back, leaving a deposition space for the metal layer 18 between the sidewalls 151 .

[0126] In other embodiments, since the doping concentration and thickness of the P-type second epitaxial layer 34 and the N-type first epitaxial layer 35 can be easily controlled and a perfect charge balance can be achieved by adding an N-type first epitaxial layer 35, the N-type semiconductor layer 23 having the N-type drift region 11 can be directly changed to the intrinsic semiconductor layer 23 by increasing the doping concentration of the first epitaxial layer 35, thereby eliminating the need to set the drift region 11 in the intrinsic semiconductor layer 23 (i.e., forming the intrinsic semiconductor layer 23 on the surface of the substrate 10, and no longer forming the N-type drift region 11).

[0127] Afterwards, a metal layer 18 may be further formed between the spacers 151 , and an interlayer dielectric layer 14 may be formed on the metal layer 18 .

[0128] like Figure 8 As shown, an adhesion layer (not shown) can be formed on the exposed surface of each sidewall 151, on the sidewall of the exposed super junction trench 36, on the top 331 of the first epitaxial layer 35 and the second epitaxial layer 34, and on the top of the gate 28 and the gate oxide layer 27 through a deposition process, and the metal layer 18 material is filled in the gaps between the sidewalls 151 on the adhesion layer to fill the gaps between the sidewalls 151. Then, by etching back or chemical mechanical polishing (CMP) the metal layer 18 material and the adhesion layer, the excess metal layer 18 material on the top surface of each sidewall 151 is removed to form a gate metal 16 separated between each pair of sidewalls 15 and connected to the gate 28, and a source region contact metal 17 separated between two adjacent pairs of sidewalls 15 and connected to the source region 13, the body region 12, the first epitaxial layer 35 and the second epitaxial layer 34 (connected through the first transition connection region 33), thereby forming a metal layer 18. That is, the gate metal 16 and the source contact metal 17 in the metal layer 18 are isolated by the spacer 151 .

[0129] Thereafter, an interlayer dielectric layer 14 (ILD) may be formed on the top surfaces of the spacers 151 , the gate metal 16 , and the source contact metal 17 (ie, the top surface of the metal layer 18 ) through a deposition process.

[0130] like Fig. 9As shown, then, a conductive contact hole 22 (eg, a tungsten contact hole) whose bottom is respectively connected to the gate metal 16 and the source contact metal 17 can be formed in the interlayer dielectric layer 14 through photolithography, etching, filling and planarization processes.

[0131] Then, a metal interconnection layer 21 connected to the top of the conductive contact hole 22 may be formed on the interlayer dielectric layer 14 through an interconnection process.

[0132] Next, a dielectric passivation layer 20 (Passivation) may be formed on the metal interconnection layer 21 through a deposition process, and a pad window 19 connected to the metal interconnection layer 21 may be formed on the surface of the passivation layer 20 through a photolithography and etching process, and the pad window 19 may be filled with pad metal and planarized to form a pad (not shown). No further details will be given.

[0133] Step S9: thinning the back side of the substrate 10 , and sequentially forming a collector region layer 25 and a buffer region layer 24 below the back side surface of the thinned substrate 10 .

[0134] like Fig.10 As shown, the front side of the substrate 10 is inverted so that the back side of the substrate 10 faces upward and the front side faces downward. Then, the front side of the substrate 10 can be fixed using existing technology (i.e., the surface of the passivation layer 20 can be fixed). For example, the front side of the substrate 10 can be fixed using a blue tape or by bonding with another substrate.

[0135] Next, the back side of the substrate 10 may be thinned using existing technology. For example, the back side of the substrate 10 may be thinned using a combination of chemical etching (wet etching) and mechanical grinding.

[0136] In a preferred embodiment, the back side of the substrate 10 may be ground and thinned to a thickness of 60-200 μm, and then chemical etching may be used to thin the back side of the substrate 10 to a final thickness.

[0137] Then, conventional ion implantation can be used to form a heavily doped P+ collector layer 25 below the back surface of the substrate 10. For example, B implantation can be used, and an implantation energy of 20 to 80 KeV can be used to form a heavily doped P+ collector layer 25 (P+imp) on the back side of the substrate 10.

[0138] Next, conventional ion implantation can be used to continue to form a heavily doped N+ type buffer layer 24 from deep to shallow in the back side of the substrate 10 below the collector region layer 25. For example, a multi-step implantation of H deep implantation (Himp deep) with an implantation energy of 0.8 to 2 MeV and H shallow implantation (Himp shallow) with an implantation energy of 0.3 to 0.8 MeV can be used to form a heavily doped N+ type buffer layer 24 (N+H imp) in the back side of the substrate 10 below the collector region layer 25. Afterwards, annealing is performed. For example, furnace annealing can be used.

[0139] Finally, conventional metal electrode manufacturing processes can be used to deposit and pattern electrode metal on the collector region layer 25 to form a collector layer 26. For example, the collector layer 26 can be formed by using at least one of Al, Ti, NiV, Ag, etc.

[0140] In summary, the present invention can reduce the number of masks and reduce the pitch by adopting multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern 37 to the fourth hard mask layer pattern 40 and the sidewall 151), so that the MOSFET device has a smaller die area, further reduces the resistance per square area, increases the current density, and significantly reduces the cost; at the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced; thus, by removing the second hard mask layer pattern 38 and the first hard mask layer pattern 37 and the third hard mask layer pattern 39 step by step, and using the formed sidewall 151 structure, the super junction trench 36 can be accurately self-aligned between adjacent gate trenches 31, which can effectively reduce the resistance and increase the switching speed. In addition, by adding the first epitaxial layer 35 of the first conductivity type in the super junction trench 36, the doping concentration and thickness of the second epitaxial layer 34 of the second conductivity type and the first epitaxial layer 35 can be easily controlled to achieve a perfect charge balance. In this way, the drift region 11 (drift) of the first conductivity type that originally needs to be formed by forming the semiconductor layer 23 of the first conductivity type can be omitted by increasing the doping concentration of the first epitaxial layer 35, and thus the semiconductor layer 23 of the first conductivity type can be directly changed to the intrinsic semiconductor layer 23, so that the on-resistance can be reduced while the withstand voltage is improved. At the same time, the shielding gate 30 trench (SGT) structure formed also advantageously plays a role in avoiding avalanche breakdown and reducing parasitic capacitance. All of these lay the foundation for further optimization of device performance.

[0141] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A self-aligned shielded gate dual epitaxial superjunction IGBT, characterized in that: include: A semiconductor layer disposed on the front side of the substrate, wherein the semiconductor layer is provided with a source region and a body region distributed in sequence from the surface of the semiconductor layer toward the substrate; A plurality of pairs of side walls are arranged in parallel on the surface of the semiconductor layer; A gate trench is provided below the surface of the semiconductor layer between each pair of the sidewalls, wherein a shielding gate and a gate are provided in the gate trench from bottom to top; A super junction trench is provided below the surface of the semiconductor layer between two adjacent pairs of the sidewalls, a first epitaxial layer of a first conductivity type is provided on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is provided in the super junction trench within the first epitaxial layer, and the first epitaxial layer and the second epitaxial layer are connected to the body region through the top facing the surface of the semiconductor layer; A collector region layer and a buffer region layer are sequentially arranged below the back surface of the substrate.

2. The self-aligned shielded gate dual epitaxial super junction IGBT according to claim 1, characterized in that: A drift region of the first conductivity type is provided in the semiconductor layer, and the body region of the second conductivity type, the source region of the first conductivity type, the first epitaxial layer and the second epitaxial layer are located in the drift region; or, the semiconductor layer is an intrinsic semiconductor layer.

3. The self-aligned shielded gate dual epitaxial super junction IGBT according to claim 1, characterized in that: Bottom portions of the super junction trench and the gate trench pass through the source region and the body region and are located in the semiconductor layer, and a depth of the super junction trench is greater than a depth of the gate trench.

4. The self-aligned shielded gate dual epitaxial superjunction IGBT according to claim 1, characterized in that: The first epitaxial layer and the second epitaxial layer are connected to the body region through a first transition connection region of the second conductivity type provided on the top facing the surface of the semiconductor layer; and / or, a second transition connection region of the first conductivity type surrounding the super junction trench and connecting the first epitaxial layer and the body region is also provided in the semiconductor layer below the body region; and / or, the second epitaxial layer has a gradient doping concentration inward along the inner wall of the super junction trench.

5. The self-aligned shielded gate dual epitaxial superjunction IGBT according to claim 1, characterized in that: Also includes: A metal layer disposed on the surface of the semiconductor layer; an interlayer dielectric layer, a metal interconnect layer and a passivation layer disposed in sequence on the surface of the metal layer; and a collector layer disposed on the back surface of the substrate; The metal layer includes a gate metal separated between each pair of the side walls and connected to the gate, and a source region contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and the interlayer dielectric layer is located on the top of the gate metal, the top of the source region contact metal and the top of the side walls.

6. A method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT, characterized in that: include: providing a substrate, and forming a semiconductor layer on a front surface of the substrate; Forming a source region of a first conductivity type and a body region of a second conductivity type in the semiconductor layer, which are distributed in sequence from the surface of the semiconductor layer toward the substrate; Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer; The second hard mask layer pattern is removed, and then, sidewalls are formed on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern, respectively, so as to form a pair of sidewalls formed by two sidewalls on adjacent sides between two adjacent first hard mask layer patterns and the third hard mask layer patterns; Forming a gate trench passing through the source region and the body region below the surface of the semiconductor layer between each pair of the sidewalls, and forming a shielding gate and a gate from bottom to top in the gate trench; forming a fourth hard mask layer pattern between each pair of the spacers, and then removing the first hard mask layer pattern and the third hard mask layer pattern; A super junction trench passing through the source region and the body region is formed below the surface of the semiconductor layer between two adjacent pairs of the sidewalls, a first epitaxial layer of a first conductivity type is formed on the inner wall of the super junction trench, a second epitaxial layer of a second conductivity type is filled in the super junction trench within the first epitaxial layer, and then, by back etching, the tops of the first epitaxial layer and the second epitaxial layer are made lower than the surface of the semiconductor layer; forming a first transition connection region of a second conductivity type connected to the body region on top of the first epitaxial layer and the second epitaxial layer, and then removing the fourth hard mask layer pattern; Also includes: The back side of the substrate is thinned, and a collector region layer and a buffer region layer are sequentially formed below the back side surface of the thinned substrate.

7. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT according to claim 6, characterized in that: The forming of a plurality of first hard mask layer patterns on the surface of the semiconductor layer, contacting second hard mask layer patterns located on both sides of the first hard mask layer patterns, and contacting a third hard mask layer pattern between two of the second hard mask layer patterns located on adjacent sides specifically includes: Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer; Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns on adjacent sides; A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form a third hard mask layer pattern that contacts two of the second hard mask layer patterns located on adjacent sides and exposes the tops of the first hard mask layer pattern and the second hard mask layer pattern.

8. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT according to claim 6, characterized in that: By sequentially forming a plurality of second sub-epitaxial layers of the second conductivity type having a gradient doping concentration in the super junction trench within the first epitaxial layer, the second epitaxial layer formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench; and / or, by forming an implantation window between two adjacent pairs of the side walls and by ion implantation, the first transition connection region is formed on top of the first epitaxial layer and the second epitaxial layer; and / or, by forming an implantation window between two adjacent pairs of the side walls and by pocket ion implantation, a second transition connection region of the first conductivity type surrounding the super junction trench is formed in the semiconductor layer below the body region.

9. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT according to claim 6, characterized in that: A semiconductor layer of the first conductivity type is formed on the surface of the substrate to form a drift region of the first conductivity type in the semiconductor layer, and the body region, the source region, the first epitaxial layer and the second epitaxial layer are formed in the drift region; or, an intrinsic semiconductor layer is formed on the surface of the substrate.

10. The method for manufacturing a self-aligned shielded gate dual epitaxial super junction IGBT according to claim 6, characterized in that: After removing the fourth hard mask layer pattern, it also includes: filling the metal layer material in the gap between each of the side walls, and removing the excess metal layer material on the top surface of the side wall, forming a gate metal separated between each pair of the side walls and connected to the gate, and a source region contact metal separated between two adjacent pairs of the side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, thereby forming a metal layer; forming an interlayer dielectric layer on the top of the metal layer and the top of the side wall; forming a metal interconnect layer and a passivation layer in sequence on the surface of the interlayer dielectric layer; and including: forming a collector layer on the back surface of the substrate after forming the collector region layer and the buffer layer.

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