Channel stress forming method, semiconductor structure, chip and circuit
By reducing the thickness of the gate sidewalls and increasing the spacing between the sidewalls, more effective transmission between the stress layer and the channel area is achieved, which solves the porosity problem during the deposition of the stress layer in the existing technology and improves the performance and efficiency of the semiconductor device.
Patent Information
- Application Number
- CN202411317296.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-01-17
AI Technical Summary
In the prior art, adjacent gate side walls have a small spacing, resulting in pores easily generated when depositing stress layers, reducing stress transferred to the channel region, and affecting device performance.
By reducing the thickness of the sidewalls on both sides of the gate, increasing the spacing between adjacent gate sidewalls, and reducing the distance between the stress layer and the channel, the stress can be transferred to the channel area more effectively. The specific method includes forming a lightly doped drain structure and multiple gates, forming sidewall structures on both sides of each gate, using an ashing process to remove amorphous carbon sidewalls, and forming a tensile layer on the surface of the gate and substrate. Stress the silicon oxide layer, form a tensile stress silicon nitride layer on its surface, and perform annealing treatment to conduct and remember the tensile stress to the channel.
Through this method, stress can be transferred to the channel region more effectively, device performance can be improved, carrier mobility and current driving capabilities can be enhanced, power consumption can be reduced, and thermal management can be improved.
Smart Images
Figure CN119325260A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a channel stress forming method, a semiconductor structure, a chip and a circuit. Background Art
[0002] Stress Memorization Technique (SMT) is a stress engineering method that improves the speed of MOS devices. This technology can significantly accelerate the electron mobility of MOS devices by virtue of the tensile stress, thereby increasing the driving current of the device. Usually, when performing stress memory engineering, a stress layer is deposited and quickly annealed after the source and drain ion implantation, and then the stress layer is removed. Although the stress layer is removed, the stress is memorized through the annealing process, that is, the channel region still retains the stress. The retained stress in the channel region can be used to improve the carrier mobility.
[0003] In the prior art, it is usually necessary to form sidewalls on both sides of the gate before stress memory is performed. As the process nodes continue to shrink, the spacing between gate structures is also shrinking. When depositing a stress layer of the required thickness, the stress layer needs to cover the top surface, side surfaces and spacing areas outside the gate structure. Due to the presence of the sidewalls, the spacing between adjacent gate sidewalls is small, which often creates gaps between the gate structures, reduces the deposited stress layer material, and then reduces the stress transferred to the channel area, affecting the performance of the device. Summary of the invention
[0004] Aiming at the technical problem that the distance between adjacent gate sidewalls in the prior art is small, pores are easily generated when depositing a stress layer, the stress transferred to the channel region is reduced, and the device performance is affected, the present invention provides a channel stress forming method, a semiconductor device structure, a chip and a circuit. The channel stress forming method can reduce the thickness of the sidewalls on both sides of the gate, thereby increasing the distance between adjacent gate sidewalls, reducing the distance between the stress layer and the channel, so that the stress can be more effectively transferred to the channel region, and the device performance is improved.
[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a channel stress forming method, which comprises: after forming a lightly doped drain structure and a plurality of gates, forming a sidewall structure on both sides of each gate; wherein the gate protrudes from the upper surface of the substrate in a step-like manner; the lightly doped drain structure is formed in the substrate and is located on both sides of the gate; the sidewall structure comprises at least one layer of layered sidewalls, and the outermost layer of the sidewall structure is an amorphous carbon sidewall; forming a source-drain injection region in the substrate by using the sidewall structure; removing the amorphous carbon sidewall by an ashing process; forming a tensile stress silicon oxide layer on the surface of the gate and the substrate; forming a tensile stress silicon nitride layer on the surface of the tensile stress silicon oxide layer; and annealing the tensile stress silicon nitride layer to conduct and memorize the tensile stress to the channel.
[0006] Furthermore, the sidewall structure is a double-layer sidewall structure, and the sidewall structure includes, from inside to outside, silicon oxide sidewalls and the amorphous carbon sidewalls.
[0007] Furthermore, the forming of the tensile stress silicon oxide layer on the gate and the substrate surface comprises: forming the tensile stress silicon oxide layer on the gate and the substrate surface by using a sub-atmospheric pressure vapor deposition process.
[0008] Furthermore, after forming the tensile stress silicon oxide layer on the gate and the substrate surface, the method further comprises: performing ultraviolet treatment on the tensile stress silicon oxide layer.
[0009] Furthermore, after the tensile stress silicon oxide layer is subjected to ultraviolet treatment, the method further comprises: using nitrogen-containing gas as a treatment atmosphere to perform nitridation treatment on the tensile stress silicon oxide layer after the ultraviolet treatment.
[0010] Furthermore, after forming the tensile stress silicon nitride layer, the method further comprises: performing ultraviolet treatment on the tensile stress silicon nitride layer.
[0011] Furthermore, after annealing the tensile stressed silicon nitride layer, the method further comprises: removing part of the tensile stressed silicon nitride layer and part of the tensile stressed silicon oxide layer on the upper surface of the substrate and the upper surface of the gate, and using the tensile stressed silicon oxide layer and part of the tensile stressed silicon nitride layer on both sides of the gate as stress sidewalls.
[0012] Furthermore, the thickness of the tensile stress silicon oxide layer is between 40 and 80 angstroms.
[0013] Furthermore, the thickness of the tensile stress silicon nitride layer is between 250 and 500 angstroms.
[0014] A second aspect of the present invention provides a semiconductor device structure, comprising a channel with tensile stress formed by using the channel stress forming method described above.
[0015] A third aspect of the present invention provides a chip, which includes the semiconductor device structure described above.
[0016] A fourth aspect of the present invention provides a circuit, which includes the semiconductor device structure described above.
[0017] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:
[0018] The channel stress forming method of the present invention forms a sidewall structure on both sides of each gate after forming a lightly doped drain structure and a plurality of gates, wherein the gate protrudes from the upper surface of the substrate in a step-like manner, the lightly doped drain structure is formed in the substrate and is located between two adjacent gates, the sidewall structure includes at least one layer of layered sidewalls, and the outermost layer of the sidewall structure is an amorphous carbon sidewall. The sidewall structure is used to form a source-drain injection region in the substrate, and then the amorphous carbon sidewall is removed by an ashing process, a tensile stress silicon oxide layer is formed on the surface of the gate and the substrate, a tensile stress silicon nitride layer is formed on the surface of the tensile stress silicon oxide layer, and the tensile stress silicon nitride layer is annealed to conduct the tensile stress to the channel. The channel stress forming method provided by the present invention can reduce the thickness of the sidewalls on both sides of the gate, thereby increasing the spacing between adjacent gate sidewalls, reducing the distance between the stress layer and the channel, so that the stress can be more effectively transferred to the channel region, and improving the device performance.
[0019] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:
[0022] Figure 1 A flow chart of a channel stress forming method provided by an embodiment of the present invention;
[0023] Figure 2 It is a schematic structural diagram of a gate and a lightly doped drain structure formed in a channel stress forming method in the prior art;
[0024] Figure 3 A schematic diagram of a sidewall structure formed in an embodiment of a channel stress forming method in the prior art;
[0025] Figure 4 A schematic structural diagram of a sidewall structure formed in another embodiment of a channel stress forming method in the prior art;
[0026] Figure 5A schematic structural diagram of a source-drain implantation region formed in a channel stress forming method provided in an embodiment of the present invention;
[0027] Figure 6 A schematic diagram of the structure after removing the amorphous carbon sidewall in the channel stress forming method provided in an embodiment of the present invention;
[0028] Figure 7 A schematic structural diagram of a tensile stress silicon oxide layer formed in a channel stress forming method provided in an embodiment of the present invention;
[0029] Figure 8 A schematic structural diagram of a tensile stress silicon nitride layer formed in a channel stress forming method provided in an embodiment of the present invention;
[0030] Fig. 9 A schematic structural diagram of a stress sidewall formed in a channel stress forming method provided in an embodiment of the present invention.
[0031] Description of Reference Numerals
[0032] 1-substrate; 2-gate; 3-lightly doped drain structure; 4-silicon oxide sidewall; 5-amorphous carbon sidewall; 6-source and drain injection region; 7-tensile stress silicon oxide layer; 8-tensile stress silicon nitride layer. DETAILED DESCRIPTION
[0033] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.
[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0035] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.
[0036] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.
[0037] Please refer to Figure 1According to a first aspect of an embodiment of the present invention, a channel stress forming method is provided, the method comprising: S101: after forming a lightly doped drain structure 3 and a plurality of gates 2, forming a sidewall structure on both sides of each gate 2; wherein the gate 2 protrudes from the upper surface of the substrate 1 in a step-like manner; the lightly doped drain structure 3 is formed in the substrate 1 and is located on both sides of the gate 2; the sidewall structure comprises at least one layer of layered sidewalls, and the outermost layer of the sidewall structure is an amorphous carbon sidewall 5; S102: forming a source-drain injection region 6 in the substrate 1 by using the sidewall structure; S103: removing the amorphous carbon sidewall 5 by using an ashing process; S104: forming a tensile stress silicon oxide layer 7 on the surface of the gate 2 and the substrate 1; S105: forming a tensile stress silicon nitride layer 8 on the surface of the tensile stress silicon oxide layer 7; S106: annealing the tensile stress silicon nitride layer 8 to conduct and memorize the tensile stress to the channel.
[0038] Specifically, step S101 is first performed: after forming a lightly doped drain structure 3 and a plurality of gates 2, a sidewall structure is formed on both sides of each gate 2; wherein the gate 2 protrudes from the upper surface of the substrate 1 in a step-like manner; the lightly doped drain structure 3 is formed in the substrate 1 and is located on both sides of the gate 2; the sidewall structure includes at least one layer of layered sidewall, and the outermost layer of the sidewall structure is an amorphous carbon sidewall 5.
[0039] Furthermore, the sidewall structure is a double-layer sidewall structure, and the sidewall structure includes, from inside to outside, a silicon oxide sidewall 4 and the amorphous carbon sidewall 5 .
[0040] Specifically, in the embodiment of the present invention, Figure 2 As shown, multiple gates 2 are formed on the surface of the substrate 1, and the multiple gates 2 protrude from the upper surface of the substrate 1 in a step-like manner. Then, light doping is performed on both sides of the gates 2 to form a lightly doped drain structure 3 in the substrate 1. Then, a sidewall structure is formed on both sides of each gate 2. The sidewall structure includes at least one layer of layered sidewalls, and the outermost layer of the sidewall structure is an amorphous carbon sidewall 5. Please refer to Figure 3 In a possible implementation manner, the sidewall structure is a double-layer sidewall structure, and the sidewall structure includes, from the inside to the outside, a silicon oxide sidewall 4 and an amorphous carbon sidewall 5. Please refer to Figure 4 In another possible implementation manner, the sidewall structure only includes a layer of amorphous carbon sidewall 5 .
[0041] Then, step S102 is performed: forming a source-drain implantation region 6 in the substrate 1 by using the sidewall structure.
[0042] Specifically, in the embodiment of the present invention, after forming the sidewall structure, the sidewall structure is used to perform heavy doping ion implantation on the substrate on both sides of the gate 2 to form Figure 5As shown, the source-drain implantation region 6, the lightly doped drain structure 3 and the source-drain implantation region 6 are located between two gates to form a source-drain structure.
[0043] Then, step S103 is performed: removing the amorphous carbon sidewalls 5 by an ashing process.
[0044] Specifically, in the embodiment of the present invention, Figure 6 As shown, after the source-drain injection region 6 is formed, the amorphous carbon sidewall 5 can be removed by an ashing process. After the amorphous carbon sidewall 5 is removed, the distance between two adjacent gate electrodes 2 can be increased, so that when the silicon nitride stress layer is deposited later, no pores will be formed between the gate electrodes 2, and the silicon nitride stress layer can be deposited uniformly, so that the stress can be more effectively transferred to the channel region, thereby improving the device performance.
[0045] Then, step S104 is performed: a tensile stress silicon oxide layer 7 is formed on the surface of the gate 2 and the substrate 1 .
[0046] Furthermore, the forming of the tensile stress silicon oxide layer 7 on the surfaces of the gate 2 and the substrate 1 comprises: forming the tensile stress silicon oxide layer 7 on the surfaces of the gate 2 and the substrate 1 by using a sub-atmospheric pressure vapor deposition process.
[0047] Furthermore, after forming the tensile stress silicon oxide layer 7 on the surfaces of the gate 2 and the substrate 1 , the method further comprises: performing ultraviolet treatment on the tensile stress silicon oxide layer 7 .
[0048] Furthermore, after the tensile stress silicon oxide layer 7 is subjected to ultraviolet treatment, the method further comprises: using nitrogen-containing gas as a treatment atmosphere to perform nitridation treatment on the tensile stress silicon oxide layer 7 after the ultraviolet treatment.
[0049] Furthermore, the thickness of the tensile stress silicon oxide layer 7 is between 40 and 80 angstroms.
[0050] Specifically, in the embodiment of the present invention, Figure 7As shown, after removing the amorphous carbon sidewall 5, a tensile stress silicon oxide layer 7 is formed on the surface of the gate 2 and the substrate 1. The silicon oxide layer deposited here and the silicon nitride layer deposited later also have tensile stress, so that the distance between the tensile stress layer and the channel is closer, and the stress can be more effectively transferred to the channel area, thereby improving the device performance. In addition, the tensile stress silicon oxide layer 7 can protect the surface of the device and reduce the damage to the device caused by etching the silicon nitride stress layer later. In this embodiment, a sub-atmospheric pressure vapor deposition process is used to form the tensile stress silicon oxide layer 7. The tensile stress silicon oxide layer 7 formed in this way can play a stress buffering role, reduce the cracking of the silicon nitride stress layer, and enable the stress of the silicon nitride stress layer to be effectively transferred to the channel, thereby improving the device performance. The thickness of the tensile stress silicon oxide layer 7 is between 40 and 80 angstroms. If the thickness of the tensile stress silicon oxide layer 7 is too thin, there will be a risk of substrate damage in the subsequent etching process. If the thickness of the tensile stress silicon oxide layer 7 is too thick, the silicon nitride stress layer cannot be effectively transferred to the channel.
[0051] After the tensile stress silicon oxide layer 7 is formed, the tensile stress silicon oxide layer 7 is subjected to ultraviolet treatment.
[0052] In this embodiment, the substrate (i.e., wafer) on which the tensile stress silicon oxide layer 7 is deposited is placed in an ultraviolet treatment device, and helium is introduced as a protective gas for ultraviolet irradiation, the irradiation time is between 40-100s, and the irradiation temperature is between 200-500°C. Boron ions are usually injected into the source and drain injection regions 6 of the PMOS, and the hydrogen atoms in the stress layer will induce the boron ions in the source and drain injection regions 6 of the PMOS to diffuse into the channel, increasing the short channel effect, and at the same time, it will also cause the boron ions to be inactivated, reduce the content of boron ions in the source and drain regions of the PMOS, and reduce the performance of the PMOS device. By ultraviolet treatment of the tensile stress silicon oxide layer 7, the content of hydrogen atoms in the tensile stress silicon oxide layer 7 can be reduced, the loss of boron ions in the source and drain injection regions 6 of the PMOS can be reduced, and the performance of the PMOS device can be improved.
[0053] After the ultraviolet treatment, the silicon oxide layer is nitrided using nitrogen-containing gas as the treatment atmosphere. Nitrogen atoms enter the silicon dioxide lattice, and the nitrogen atoms on the surface increase, making the tensile stress silicon oxide layer 7 more compact, preventing hydrogen atoms from entering the source and drain injection region 6 of the PMOS downward, reducing the loss of boron ions in the source and drain injection region 6 of the PMOS, and ensuring the performance of the PMOS device.
[0054] Then, step S105 is performed: forming a tensile stressed silicon nitride layer 8 on the surface of the tensile stressed silicon oxide layer 7 .
[0055] Furthermore, after forming the tensile stress silicon nitride layer 8 , the method further comprises: performing ultraviolet treatment on the tensile stress silicon nitride layer 8 .
[0056] Furthermore, the thickness of the tensile stress silicon nitride layer 8 is between 250 and 500 angstroms.
[0057] Specifically, in the embodiment of the present invention, Figure 8 As shown, a tensile stress silicon nitride layer 8 is formed on the surface of the tensile stress silicon oxide layer 7 by vapor deposition and process. The thickness of the tensile stress silicon nitride layer 8 is between 250 and 500 angstroms. If the tensile stress silicon nitride layer 8 is too thick, it is not easy to remove. If the tensile stress silicon nitride layer 8 is too thin, the stress may cause the risk of cracking of the tensile stress silicon nitride layer 8. After the tensile stress silicon nitride layer 8 is deposited, the tensile stress silicon nitride layer 8 is treated with ultraviolet light. The ultraviolet light can reduce or eliminate the compressive stress in the tensile stress silicon nitride layer 8, improve the performance of the MOS device, reduce the defects in the tensile stress silicon nitride layer 8, thereby improving its reliability in subsequent processes and reducing the failure probability of the device during operation. At the same time, ultraviolet light irradiation can promote the release of hydrogen in the tensile stress silicon nitride layer 8, reduce the hydrogen content, and reduce the formation of hydrogen-induced defects.
[0058] Finally, step S106 is performed: annealing is performed on the tensile stress silicon nitride layer 8 to conduct and memorize the tensile stress to the channel.
[0059] Furthermore, after annealing the tensile stressed silicon nitride layer 8, the method further comprises: removing part of the tensile stressed silicon nitride layer 8 and part of the tensile stressed silicon oxide layer 7 on the upper surface of the substrate 1 and the upper surface of the gate 2, and using the tensile stressed silicon oxide layer 7 and part of the tensile stressed silicon nitride layer 8 on both sides of the gate 2 as stress sidewalls.
[0060] Specifically, in the embodiment of the present invention, the tensile stress silicon nitride layer 8 is annealed at a temperature between 1035 and 1080°C. After annealing, the tensile stress is memorized in the channel, which can improve the carrier mobility and increase the current driving capability, thereby improving the switching speed and overall performance of the device, reducing power consumption, and reducing the heat generation of the device, which helps to improve the thermal management of the device and extend the life of the device; under the same electric field, carriers can pass through the channel faster, enhancing the current carrying capacity; under the same carrier migration speed requirements, the device size can be reduced and the integration of the integrated circuit can be improved.
[0061] Please refer to Fig. 9After annealing, combined with the Self-Aligned Block (SAB) process, the tensile stress silicon nitride layer 8 is not completely removed, only part of the tensile stress silicon nitride layer 8 and part of the tensile stress silicon oxide layer 7 on the upper surface of the substrate 1 and the upper surface of the gate 2 are removed, and the tensile stress silicon oxide layer 7 and part of the tensile stress silicon nitride layer 8 on both sides of the gate 2 are retained, and a SAB structure is formed at the same time (not shown in the figure). The tensile stress silicon oxide layer 7 and part of the tensile stress silicon nitride layer 8 on both sides of the gate 2 are used as stress sidewalls, and the stress sidewalls and the silicon oxide sidewalls 4 are used together as the sidewall structure of the gate 2. The stress sidewalls can improve the isolation ability of the sidewalls, isolate the gate 2 from the source and drain injection region 6, increase the distance between the source and drain injection region 6 and the gate 2, reduce the parasitic capacitance and leakage current between the gate 2 and the source and drain injection region 6, reduce the static power consumption of the device, effectively control the distribution of the electric field, and improve the breakdown voltage of the device. The area where the silicon oxide and silicon nitride are retained can be used as a self-aligned metal silicide barrier. By combining a self-aligned block (SAB) process to simultaneously form a sidewall and a SAB structure, the process cost can be reduced.
[0062] A second aspect of the present invention provides a semiconductor device structure, comprising a channel with tensile stress formed by using the channel stress forming method described above.
[0063] A third aspect of the present invention provides a chip, which includes the semiconductor device structure described above.
[0064] A fourth aspect of the present invention provides a circuit, which includes the semiconductor device structure described above.
[0065] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0066] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.
[0067] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.
Claims
1. A channel stress forming method, characterized in that: The channel stress forming method comprises: After forming a lightly doped drain structure and a plurality of gates, forming sidewall structures on both sides of each gate; wherein the gate protrudes from the upper surface of the substrate in a step-like manner; the lightly doped drain structure is formed in the substrate and is located on both sides of the gate; the sidewall structure includes at least one layer of layered sidewalls, and the outermost layer of the sidewall structure is an amorphous carbon sidewall; Forming a source-drain injection region in the substrate by using the sidewall structure; Removing the amorphous carbon sidewalls by an ashing process; forming a tensile stress silicon oxide layer on the gate and the substrate surface; forming a tensile stress silicon nitride layer on the surface of the tensile stress silicon oxide layer; The tensile stress silicon nitride layer is annealed to conduct and memorize the tensile stress to the channel.
2. The channel stress forming method according to claim 1, characterized in that: The sidewall structure is a double-layer sidewall structure, and the sidewall structure includes, from inside to outside, silicon oxide sidewalls and the amorphous carbon sidewalls.
3. The channel stress forming method according to claim 1, characterized in that: The step of forming a tensile stress silicon oxide layer on the gate and the substrate surface comprises: The tensile stress silicon oxide layer is formed on the gate and the substrate surface by using a subatmospheric pressure vapor deposition process.
4. The channel stress forming method according to claim 1, characterized in that: After forming a tensile stress silicon oxide layer on the gate and the substrate surface, the method further comprises: The tensile stress silicon oxide layer is subjected to ultraviolet treatment.
5. The channel stress forming method according to claim 4, characterized in that: After the tensile stress silicon oxide layer is subjected to ultraviolet treatment, the method further comprises: The tensile stress silicon oxide layer after the ultraviolet treatment is nitrided by using nitrogen-containing gas as the treatment atmosphere.
6. The channel stress forming method according to claim 1, characterized in that: After forming the tensile stress silicon nitride layer, the method further comprises: The tensile stress silicon nitride layer is subjected to ultraviolet treatment.
7. The channel stress forming method according to claim 1, characterized in that: After annealing the tensile stress silicon nitride layer, the method further comprises: Part of the tensile stress silicon nitride layer and part of the tensile stress silicon oxide layer on the upper surface of the substrate and the upper surface of the gate are removed, and the tensile stress silicon oxide layer and part of the tensile stress silicon nitride layer on both sides of the gate are used as stress sidewalls.
8. The channel stress forming method according to claim 1, characterized in that: The thickness of the tensile stress silicon oxide layer is between 40 and 80 angstroms.
9. The channel stress forming method according to claim 1, characterized in that: The thickness of the tensile stress silicon nitride layer is between 250-500 angstroms.
10. A semiconductor device structure, characterized in that: The semiconductor device structure includes a channel with tensile stress formed by using the channel stress forming method according to any one of claims 1 to 8.
11. A chip, characterized in that: The chip comprises the semiconductor device structure according to claim 10.
12. A circuit, characterized in that: The circuit comprises the semiconductor device structure according to claim 10.