Method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of suppressing peeling of a coating film while reducing an ineffective region. A method for manufacturing a semiconductor device includes a preparation step of preparing a semiconductor structure and a dicing step of dicing a dicing line region. The thickness of the side monitoring electrode is smaller than the thickness of the coating film, and 15 > b > 1.15 * d + 6.88 is satisfied between the distance b [[mu] m] between the coating film and the side monitoring electrode and the length d [mm] of the side monitoring electrode in the direction in which the cutting line region extends in plan view.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. Background Art

[0002] A semiconductor chip having a coating film provided in a terminal region is proposed. In such a semiconductor chip, after the coating film is formed by a developer, if the developer is retained in a concave portion adjacent to the coating film, there is a problem that the coating film is peeled off by the developer. In response to this, Patent Document 1 proposes a technology for covering the concave portion with a coating film to suppress the retention of the developer, thereby suppressing the peeling of the coating film.

[0003] Patent Document 1: International Publication No. 2014 / 013581

[0004] If a covering film is provided near the cutting line, the covering film may get stuck when cutting with a blade. Therefore, the covering film needs to be provided at a certain distance from the cutting line. However, if an opening is provided as in the technology of Patent Document 1, the distance between the covering film and the cutting line needs to be greater than the certain distance. As a result, there is a problem of increasing the ineffective area in the semiconductor substrate and increasing the manufacturing cost of the semiconductor device. In addition, if a side monitoring electrode is provided for monitoring the electrical characteristics of the semiconductor chip during the manufacturing process, there is a problem of increasing the ineffective area in the semiconductor substrate and increasing the manufacturing cost of the semiconductor device. Summary of the invention

[0005] Therefore, the present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a technology capable of reducing the ineffective area and suppressing the peeling of the coating film.

[0006] The manufacturing method of the semiconductor device disclosed in the present invention comprises the following steps: a preparation step of preparing a semiconductor structure that defines a terminal area of ​​a semiconductor chip and a cut line area adjacent to the terminal area when viewed from above; and a cutting step of cutting the cut line area, wherein the semiconductor structure comprises: a semiconductor substrate that defines the terminal area and the cut line area; a side monitor electrode that is arranged on the semiconductor substrate in the cut line area; a passivation film that is arranged from the upper part of the semiconductor substrate in the terminal area to the upper part of the side monitor electrode; and a coating film that is arranged on the passivation film in the terminal area, wherein the thickness of the side monitor electrode is smaller than the thickness of the coating film, and between the distance b [μm] between the coating film and the side monitor electrode and the length d [mm] of the side monitor electrode in the extension direction of the cut line area when viewed from above, 15>b>1.15×d+6.88 holds.

[0007] According to the present disclosure, the thickness of the side monitoring electrode is smaller than the thickness of the coating film, and between the distance b [μm] between the coating film and the side monitoring electrode and the length d [mm] of the side monitoring electrode in the extending direction of the cutting line region when viewed from above, 15>b>1.15×d+6.88 holds. According to such a structure, the ineffective area can be reduced and the peeling of the coating film can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a plan view showing the structure of the semiconductor structure according to the first embodiment.

[0009] Figure 2 This is a plan view showing the structure of the semiconductor structure according to the first embodiment.

[0010] Figure 3 This is a cross-sectional view showing the structure of the semiconductor structure according to the first embodiment.

[0011] Figure 4 It is a diagram showing the experimental results of the semiconductor structure according to the first embodiment.

[0012] Figure 5 It is a cross-sectional view showing the structure of a semiconductor structure according to the second embodiment.

[0013] Figure 6 It is a top view showing the structure of a semiconductor structure according to the second embodiment.

[0014] Figure 7 It is a plan view showing the structure of a semiconductor structure according to a modification of the second embodiment.

[0015] Figure 8 It is a cross-sectional view showing the structure of a semiconductor structure according to a modification of the second embodiment.

[0016] Fig. 9 It is a cross-sectional view showing the structure of a semiconductor structure according to a modification of the second embodiment.

[0017] Explanation of the reference numerals: 1…semiconductor substrate; 2…side monitoring electrode; 3…passivation film; 4…coating film; 5…insulating film; 6…concave and convex; 11…semiconductor chip; 11b…terminal area; 11c…surface electrode; 12…cutting line area; 13…remaining area. DETAILED DESCRIPTION

[0018] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in the following embodiments are illustrative, and not all features are necessary. In addition, in the description shown below, the same components are marked with the same or similar reference numerals in multiple embodiments, and different components are mainly described. In addition, in the description recorded below, specific positions and directions such as "upper", "lower", "left", "right", "table" or "back" may not necessarily be consistent with the positions and directions during actual implementation.

[0019] <Implementation method 1>

[0020] Figure 1 1 is a plan view showing the structure of the semiconductor structure of the first embodiment. The semiconductor structure is prepared in a semiconductor structure preparation step in the middle of the semiconductor device manufacturing process. In the semiconductor structure, the unit structure region 11a and the terminal region 11b of the semiconductor chip 11 and the dicing region 12 are defined.

[0021] A semiconductor element is provided in the unit structure region 11a. The semiconductor element includes, for example, at least one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting-IGBT), an SBD (Schottky Barrier Diode), and a PND (PN junction diode). In addition, in this specification, for example, at least one of A, B, C, ..., and Z refers to any one of all combinations of one or more selected from the group of A, B, C, ..., and Z.

[0022] The terminal region 11 b is a region surrounding the unit structure region 11 a in a plan view, and is a region for maintaining the withstand voltage of the unit structure region 11 a .

[0023] The scribe line region 12 is a region provided between adjacent semiconductor chips 11 when viewed from above and adjacent to the terminal region 11b of each semiconductor chip 11. The semiconductor chips 11 are cut and individualized by a dicing process of dicing the scribe line region 12 of the semiconductor structure. In order to ensure a width for a dicing blade such as a grinding wheel blade to pass through, the width of the scribe line region 12 is, for example, 80 to 120 μm in most cases.

[0024] Figure 2 Yes Figure 1The enlarged top view of the part surrounded by the dotted line, Figure 3 It is along Figure 2 A-A' line cross-sectional view. Figure 2 and Figure 3 As shown, the semiconductor structure includes a semiconductor substrate 1 , a side monitor electrode 2 , a passivation film 3 , and a cover film 4 .

[0025] Figure 3 The semiconductor substrate 1 is composed of, for example, silicon (Si) or a wide bandgap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxial growth layer. The wide bandgap semiconductor includes, for example, silicon carbide (SiC), gallium nitride (GaN), diamond, etc. In the case where the semiconductor substrate 1 is composed of a wide bandgap semiconductor, stable operation at high temperature and high voltage and high switching speed can be achieved for the semiconductor element. However, since the price of the semiconductor substrate 1 composed of SiC is high, from the perspective of low cost of the semiconductor device, it is required to minimize the ineffective area in the semiconductor substrate 1. In this regard, as described below, according to the present embodiment 1, the ineffective area in the semiconductor substrate 1 can be reduced.

[0026] The semiconductor substrate 1 is provided with Figure 1 The semiconductor chip 11 is provided with a unit structure region 11a, a terminal region 11b, and a dicing line region 12. A surface electrode of the semiconductor chip 11 is formed on the surface of the semiconductor substrate 1, and a back electrode of the semiconductor chip 11 is formed on the back surface of the semiconductor substrate 1. In addition, the back surface of the semiconductor substrate 1 may be ground before the back electrode is formed.

[0027] like Figure 3 As shown, the side monitor electrode 2 is provided on the semiconductor substrate 1 in the cutting line area 12. The side monitor electrode 2 is provided to detect abnormalities in the manufacturing process of the semiconductor device. For example, a diffusion layer is provided on the semiconductor substrate 1 under the side monitor electrode 2, and the diffusion layer is formed simultaneously with the unit diffusion layer of the semiconductor element constituting the unit structure area 11a. Before cutting, the operator electrically connects the probe to the side monitor electrode 2 and measures the resistance of the diffusion layer under the side monitor electrode 2, thereby being able to detect abnormalities in the manufacturing process at a relatively early stage. In addition, if the operator discovers that the characteristics of the semiconductor chip 11 are poor, the abnormal process can be traced back by analyzing the measured values ​​of the side monitor electrode 2. In addition, the operator can also achieve production line management by comparing the changes in the characteristic values ​​obtained from the side monitor electrode 2.

[0028] The side monitor electrode 2 is provided at least at one point of the scribe line region 12 within the exposure irradiation. Although it also depends on the size of the semiconductor chip 11, it is preferable to provide a plurality of side monitor electrodes 2 with a size that can be accommodated in one side of the semiconductor chip 11. At the intersection where the scribe line region 12 intersects, a mark type used for calibration in the exposure process is often provided, so it is preferable not to provide the side monitor electrode 2 at the intersection. In addition, the side monitor electrode 2 is made of AlSi, for example.

[0029] The passivation film 3 is provided from the upper part of the semiconductor substrate 1 in the terminal region 11b to the upper part of the side monitor electrode 2. The passivation film 3 provided as an insulating film on the semiconductor substrate 1 in the terminal region 11b has the function of suppressing the creeping discharge of the semiconductor chip 11, similarly to the coating film 4 described later. The passivation film 3 is provided with an opening for partially exposing the upper part of the side monitor electrode 2 electrically connected to the probe. For example, after a silicon oxide film or a nitride film is deposited on the upper surface of the semiconductor substrate 1, it is etched through the resist in a photolithography process, thereby forming a pattern of the passivation film 3.

[0030] The coating film 4 is provided on the passivation film 3 in the terminal region 11b. If the coating film 4 is caught in the grinding wheel blade during cutting, it may be clogged and productivity may be reduced, or cracks may be formed at the end of the semiconductor chip 11. Figure 2 and Figure 3 As shown, the cover film 4 exposes the passivation film 3 in the scribe line region 12 .

[0031] The coating film 4 is composed of, for example, photosensitive polyimide. The pattern of the coating film 4 is formed by a developing step included in the preparation step of the semiconductor structure. For example, after a photosensitive polyimide precursor solution is applied to the semiconductor substrate 1 provided with the passivation film 3, pre-baking is performed, and an arbitrary pattern is formed in a photolithography process and formal baking is performed, thereby forming the coating film 4. If, after the photosensitive polyimide is applied to the wafer, it is selectively exposed using a mask, the exposed portion is melted in the developer, so that the coating film 4 can be formed in an arbitrary pattern.

[0032] The coating film 4 provided as an insulating film on the passivation film 3 in the terminal region 11b has a function of suppressing creeping discharge of the semiconductor chip 11. In addition, the coating film 4 composed of polyimide has flexibility, and thus has a function of protecting the structure of the terminal region 11b of the semiconductor chip 11 from the stress caused by the expansion and contraction of the external sealing material, etc. In addition, after the back surface of the semiconductor substrate 1 is polished so that the thickness of the semiconductor substrate 1 becomes, for example, about 100 μm or less, the warping of the semiconductor substrate 1 after the polishing process becomes large, so that the formation of the passivation film 3 or the coating film 4 becomes difficult. Therefore, the formation of the passivation film 3 or the coating film 4 is preferably performed before the polishing process of the semiconductor substrate 1.

[0033] According to the above structure, since the side monitor electrode 2 is provided on the scribe line region 12, there is no need for a dedicated area for the side monitor electrode 2. Therefore, the ineffective area in the semiconductor substrate 1 can be reduced. Figure 3 As shown, since a recess is formed between side monitor electrode 2 and cover film 4, the developer used to form cover film 4 is retained in the recess, and cover film 4 may peel off. Therefore, the inventors conducted an experiment to investigate a structure in which cover film 4 does not peel off.

[0034] Figure 4 is a graph showing the experimental results. In this experiment, when the thickness c of the side monitor electrode 2 is smaller than the thickness a of the coating film 4, the distance between the coating film 4 and the side monitor electrode 2 is set to b [μm], and the length of the side monitor electrode in the extending direction of the cutting line area 12 when viewed from above is set to d [mm]. Figure 3 The distance b is shown in the figure. Figure 2 The length d is illustrated in FIG.

[0035] like Figure 4 As shown, when 15 [μm] > b > 1.15 × d + 6.88, preferably 10 [μm] > b > 1.15 × d + 6.88 is established, the peeling of the coating film 4 is suppressed. Therefore, the semiconductor structure of the first embodiment is configured so that 15 [μm] > b > 1.15 × d + 6.88 is established. In addition, as long as this formula is established, the peeling of the coating film 4 can be suppressed even when the length d is greater than 100 μm.

[0036] <Summary of Implementation 1>

[0037] According to the method for manufacturing a semiconductor device of the first embodiment as described above, a semiconductor structure in which the side monitor electrode 2 is provided on the dicing line region 12 is used. According to such a structure, the ineffective area in the semiconductor substrate 1 can be reduced. In addition, in the first embodiment, between the distance b [μm] between the coating film 4 and the side monitor electrode 2 when viewed from above, and the length d [mm] of the side monitor electrode 2 in the extending direction of the dicing line region 12 when viewed from above, 15>b>1.15×d+6.88 holds. According to such a structure, the developer can be prevented from being retained in the recessed portion between the side monitor electrode 2 and the coating film 4, and the coating film 4 can be prevented from peeling off. As a result, the reliability degradation and appearance abnormality of the semiconductor device can be prevented.

[0038] In addition, when the passivation film 3 is a glass coating film including silicon nitride (SiN), for example, the adhesion between the passivation film 3 and the coating film 4 can be improved compared to the adhesion between the semiconductor substrate 1 and the coating film 4. Therefore, even if a developer remains in the concave portion, it is possible to suppress the coating film 4 from peeling off due to the developer penetrating between the passivation film 3 and the coating film 4.

[0039] Furthermore, when the semiconductor substrate 1 is made of SiC, the ineffective region can be reduced in the expensive semiconductor substrate 1 , thereby reducing the cost of the semiconductor device.

[0040] <Implementation method 2>

[0041] Figure 5 is a cross-sectional view showing the structure of the semiconductor structure of the second embodiment, and is Figure 3 In the semiconductor structure of the second embodiment, a surplus region 13 is defined between the terminal region 11b and the scribe region 12. The surplus region 13 is a region outside the depletion layer at the end of the semiconductor chip 11. The semiconductor substrate 1, the passivation film 3, and the coating film 4 are also provided in the surplus region 13, similarly to the terminal region 11b.

[0042] Semiconductor structures except Figure 3 In addition to the structure, it also includes one or more insulating films 5. Figure 6 1 is a top view showing the structure of the remaining region 13. The insulating film 5 is provided only in the remaining region 13 and between the passivation film 3 and the semiconductor substrate 1. Figure 5 As shown, only in the remaining area 13 and in the passivation film 3 and the coating film 4, there are provided with concavoconvex 6 which are mutually interlocked and correspond to the shape of the insulating film 5 when viewed in cross section. The number of concavoconvex 6 may be one, or a plurality of concavoconvex 6 may be provided at intervals. In addition, the insulating film 5 is composed of TEOS (tetra ethoxy silane), for example.

[0043] <Summary of Implementation 2>

[0044] According to the method for manufacturing a semiconductor device of the second embodiment as described above, the passivation film 3 and the coating film 4 are provided with concavo-convex portions 6 that fit into each other and correspond to the shape of the insulating film 5 when viewed in cross section. According to such a structure, the surface area of ​​the boundary surface between the passivation film 3 and the coating film 4 can be increased, so that the adhesion between them can be improved. Thus, even if a developer remains in the concave portion, it is possible to suppress the peeling of the coating film 4 due to the developer penetrating between the passivation film 3 and the coating film 4.

[0045] In the second embodiment, the concavo-convex portions 6 are provided only in the remaining region 13. With such a configuration, the remaining region 13 can be effectively utilized.

[0046] <Modification>

[0047] exist Figure 5 and Figure 6 In the embodiment, the plurality of insulating films 5 are arranged in a direction from the terminal region 11b toward the cutting line region 12, but the present invention is not limited thereto. Figure 7 As shown, the plurality of insulating films 5 may be arranged in both the direction from the terminal region 11b toward the cutting line region 12 and the direction perpendicular to the direction. In addition, for example, the insulating film 5 may be arranged continuously or intermittently in a manner of winding around the remaining region 13. In addition, the number, size and arrangement of the insulating films 5 are not limited to the above description.

[0048] In addition, Figure 5 The side surface of the insulating film 5 is perpendicular to the bottom surface of the insulating film 5. Figure 8 As shown, the taper angle of the insulating film 5 may also be less than 90°, so that the insulating film 5 has a tapered shape that tapers toward the upper tip when viewed in cross section. According to such a structure, the shape of the concave-convex 6 between the passivation film 3 and the coating film 4 becomes smooth, and bubbles are difficult to form between the passivation film 3 and the coating film 4, thereby improving the adhesion between the passivation film 3 and the coating film 4.

[0049] In the second embodiment, the concavoconvex 6 is provided only in the remaining region 13. However, if it is not necessary to effectively utilize the remaining region 13, the concavoconvex 6 may be provided in the terminal region 11b. Fig. 9 As shown, the surface electrode 11c of the semiconductor chip 11 may be provided instead of the insulating film 5, thereby providing the passivation film 3 and the cover film 4 with concavoconvexities 6 that fit each other and correspond to the shape of the surface electrode 11c when viewed in cross section. In this case, the same effect as that of the second embodiment can be obtained.

[0050] Furthermore, the embodiments and modifications may be freely combined, or the embodiments and modifications may be appropriately modified or omitted.

[0051] Hereinafter, each aspect of the present disclosure will be collectively described as a supplementary note.

[0052] (Note 1)

[0053] A method for manufacturing a semiconductor device comprises the following steps:

[0054] a preparation step of preparing a semiconductor structure defining a terminal region of the semiconductor chip and a dicing line region adjacent to the terminal region when viewed from above; and

[0055] A cutting process is performed to cut the cutting line area.

[0056] The semiconductor structure comprises:

[0057] A semiconductor substrate, which defines the terminal area and the cutting line area;

[0058] a side monitoring electrode disposed on the semiconductor substrate in the cutting line region;

[0059] a passivation film provided from an upper portion of the semiconductor substrate in the terminal region to an upper portion of the side monitor electrode; and

[0060] a coating film disposed on the passivation film in the terminal region,

[0061] The thickness of the side monitoring electrode is smaller than the thickness of the coating film,

[0062] Between the distance b [μm] between the cover film and the side monitor electrode and the length d [mm] of the side monitor electrode in the extending direction of the scribe line region in a plan view, 15>b>1.15×d+6.88 holds.

[0063] (Note 2)

[0064] According to the method for manufacturing a semiconductor device according to Supplement 1,

[0065] The distance b is greater than 7 μm, and the length d is greater than 100 μm.

[0066] (Note 3)

[0067] The method for manufacturing a semiconductor device according to Supplement 1 or 2,

[0068] The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate.

[0069] The passivation film and the cover film are provided with concavities and convexities which fit each other in a cross-sectional view and correspond to the shape of the insulating film.

[0070] (Note 4)

[0071] The method for manufacturing a semiconductor device according to Supplement 1 or 2,

[0072] In the semiconductor structure, a remaining area is further defined between the terminal area and the scribe line area.

[0073] The semiconductor substrate, the passivation film and the coating film are arranged in the remaining area.

[0074] The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate.

[0075] Concavities and convexities are provided only in the remaining region and in the passivation film and the coating film, which are fitted with each other and correspond to the shape of the insulating film when viewed in cross section.

[0076] (Note 5)

[0077] The method for manufacturing a semiconductor device according to Supplement 3 or 4,

[0078] The taper angle of the insulating film is smaller than 90°.

[0079] (Note 6)

[0080] The method for manufacturing a semiconductor device according to any one of appendices 1 to 5,

[0081] The semiconductor structure further includes one or more surface electrodes provided between the passivation film and the semiconductor substrate.

[0082] The passivation film and the coating film, when viewed in cross section, are provided with projections and depressions that fit each other when viewed in cross section and correspond to the shapes of the surface electrodes.

[0083] (Note 7)

[0084] The method for manufacturing a semiconductor device according to any one of appendices 1 to 6,

[0085] The semiconductor substrate is made of SiC.

[0086] (Note 8)

[0087] The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the preparation step includes a development step of forming a pattern of the coating film.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following processes are available: A preparation step of preparing a semiconductor structure defining a terminal region of the semiconductor chip and a dicing line region adjacent to the terminal region when viewed from above; and A cutting process is performed to cut the cutting line area. The semiconductor structure comprises: A semiconductor substrate, which defines the terminal area and the cutting line area; a side monitoring electrode disposed on the semiconductor substrate in the cutting line region; a passivation film provided from an upper portion of the semiconductor substrate in the terminal region to an upper portion of the side monitor electrode; and a coating film disposed on the passivation film in the terminal region, The thickness of the side monitoring electrode is smaller than the thickness of the coating film, Between the distance b [μm] between the cover film and the side monitor electrode and the length d [mm] of the side monitor electrode in the extending direction of the scribe line region in a plan view, 15>b>1.15×d+6.88 holds.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The distance b is greater than 7 μm, and the length d is greater than 100 μm.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate. The passivation film and the cover film are provided with concavities and convexities which fit each other in a cross-sectional view and correspond to the shape of the insulating film.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: In the semiconductor structure, a remaining area is further defined between the terminal area and the scribe line area. The semiconductor substrate, the passivation film and the coating film are arranged in the remaining area. The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate. Concavities and convexities are provided only in the remaining region and in the passivation film and the coating film, which are fitted with each other and correspond to the shape of the insulating film when viewed in cross section.

5. The method for manufacturing a semiconductor device according to claim 3 or 4, characterized in that: The taper angle of the insulating film is smaller than 90°.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor structure further includes one or more surface electrodes provided between the passivation film and the semiconductor substrate. The passivation film and the coating film, when viewed in cross section, are provided with projections and depressions that fit each other when viewed in cross section and correspond to the shapes of the surface electrodes.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor substrate is made of SiC.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein: The preparation step includes a development step of forming a pattern of the coating film.

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