Controller, segment code type liquid crystal display device and state detection method of display module

Abstract

The invention provides a controller, segment code type liquid crystal display equipment and a state detection method of a display module. The controller is suitable for driving a display module having a plurality of pixels, and includes a signal generation circuit and an abnormality detection circuit. The signal generating circuit is coupled to the display module and generates a plurality of control signals for driving the plurality of pixels based on a power supply signal, where the signal generating circuit outputs a control signal having a test waveform in a test mode. The anomaly detection circuit receives the power supply signal and is used for detecting the change of the power supply signal in response to the test waveform in the test mode so as to generate a detection value corresponding to the pixel to be tested.

Description

Technical Field

[0001] The present disclosure relates to a detection technology for a display device, and more particularly to a state detection method for a controller, a segment code liquid crystal display device and a display module. Background Art

[0002] Segment code liquid crystal display device (segment code LCD) is a pattern type liquid crystal display, which is commonly used in the display interface of electronic devices such as air conditioner remote controllers, electronic blood pressure monitors and electronic calculators. The display mechanism of segment code liquid crystal display devices is mainly to drive the pixels / fields in the display module through the control of shared signals (COM signals) and field signals (SEG signals) to display different patterns and numbers.

[0003] The connection interface of the display module of the segment code LCD is usually composed of pins for receiving SEG signals and COM signals, wherein the controller connects to the display module through the connection interface and sends a control signal to drive the display module to display an image.

[0004] This type of display module has a common abnormality, that is, a short circuit may occur between its pins, or the pins may short-circuit to other external circuits, causing the segment code LCD to display abnormally. Therefore, in the production process, it is necessary to detect whether the display image / number of each pixel / field is abnormal. The common method of the above detection is to confirm whether each pin has a short circuit through manual visual inspection or by using I / O to control the pin to be tested to a high / low level through the signal status.

[0005] Although manual inspection can more intuitively confirm whether each pixel / field can be displayed normally, this method is very time-consuming, and manual inspection may not detect abnormal conditions due to distraction or fatigue, making it difficult to improve overall efficiency and detection accuracy.

[0006] On the other hand, in the detection method using I / O to control the pin to be tested to a high / low level, whether the pin to be tested is short-circuited is mainly determined by confirming whether other pins have the same high / low level, wherein if the same high / low level as the pin to be tested is detected on other pins, it means that a short circuit has occurred. Although this method can detect basic short circuit conditions, it is impossible to know the severity of the short circuit condition. Sometimes, although a short circuit occurs between pins, the equivalent impedance at both ends is large enough to indicate that no abnormality has occurred. This situation does not need to be classified as an abnormal state that needs to be screened out in some applications. However, through the above-mentioned I / O control detection method, no matter what the short circuit condition is, it will be screened as an abnormality, which results in an unnecessary increase in manufacturing costs. Summary of the invention

[0007] The present disclosure provides a controller, a segment code liquid crystal display device and a state detection method of a display module, which can detect the degree of short circuit between pins to avoid filtering out pixels that can be displayed normally.

[0008] The present disclosure provides a controller, which is suitable for driving a display module having a plurality of pixels, wherein the controller includes a signal generating circuit and an abnormality detection circuit. The signal generating circuit is used to couple the display module, and to generate a plurality of control signals for driving the plurality of pixels based on a power supply signal, wherein the signal generating circuit outputs a control signal having a test waveform in a test mode. The abnormality detection circuit receives the power supply signal, and is used to detect changes in the power supply signal in response to the test waveform in the test mode, so as to generate a detection value corresponding to a pixel to be tested among the plurality of pixels.

[0009] The present disclosure provides a segment code liquid crystal display device, including a segment code liquid crystal display module and a controller. The segment code liquid crystal display module has a plurality of display fields, wherein each display field has two pins. The controller is coupled to the plurality of pins, and is used to generate a plurality of control signals based on a power supply signal and output them to the plurality of pins respectively to drive the segment code liquid crystal display module. The controller outputs a control signal having a test waveform in a test mode, and detects changes in the power supply signal in response to the test waveform to generate a detection value indicating the degree of short circuit of the corresponding display field.

[0010] The present disclosure provides a state detection method for a display module, comprising the following steps: sending a first control signal having a first test waveform to one of a plurality of pins of the display module, and sending a second control signal having a second test waveform to another of the plurality of pins of the display module, wherein the one of the pins and the another of the pins correspond to pixels to be tested of the display module; detecting a power signal used to generate the control signal; and generating a detection value corresponding to the pixel to be tested according to a change in the power signal.

[0011] Based on the above, the controller, segment code liquid crystal display device and display module state detection method disclosed in the present invention can more accurately detect the actual short circuit degree and abnormal situation of the pins corresponding to each pixel of the display module, so that the availability of the display module can be more accurately evaluated according to the required application scenario in the back-end application, thereby avoiding excessive screening of modules with slight short circuits but no effect on the display, resulting in unnecessary increase in manufacturing costs; or avoiding the risk of unexpected product reliability caused by the failure to screen out mild short circuits in some applications requiring high reliability. In addition, some embodiments of the present invention can set the functions and operations of the test mode on the existing LCD driver without any additional output setting modification or additional circuit addition, effectively reducing the manufacturing cost of designing and modifying the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of a controller according to an embodiment of the present disclosure;

[0014] Figure 3 A schematic diagram of signal timing of a controller in a test mode according to an embodiment of the present disclosure; and

[0015] Figure 4 A schematic diagram of signal timing of a controller in a test mode according to another embodiment of the present disclosure;

[0016] Figure 5 A flowchart of a method for detecting a state of a display module according to an embodiment of the present disclosure; and

[0017] Figure 6 The present invention is a flowchart of a method for detecting a state of a display module according to another embodiment of the present invention. DETAILED DESCRIPTION

[0018] The present disclosure proposes a new controller, a segment code liquid crystal display device and a state detection method of a display module to solve the problems mentioned in the background technology. In order to make the features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the drawings. The following description contains specific information related to the exemplary embodiments in the present disclosure. The drawings and the accompanying detailed descriptions in the present disclosure are only exemplary embodiments. However, the present disclosure is not limited to these exemplary embodiments. Other variations and embodiments of the present disclosure will occur to those skilled in the art. Unless otherwise specified, the same or corresponding components in the drawings may be indicated by the same or corresponding figure numbers. In addition, the drawings and illustrations in the present disclosure are generally not drawn to scale and are not intended to correspond to actual relative sizes.

[0019] All descriptions related to specific values ​​in this disclosure, although not directly described, include the meaning of "approximately" or "substantially", that is, these specific values ​​will include possible numerical error ranges to characterize possible unintended effects and deviations in process or material selection. The numerical error range may include numerical changes that do not significantly change the material structure, characteristics, and effects, such as a range of 0% to 10% deviation, and this error range is clear to those with ordinary knowledge in the field.

[0020] Figure 1 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. Figure 1, the display device 10 includes a display module LCM and a controller 100 for driving the display module LCM. The present disclosure does not limit the category / type of the display device 10 and its display module LCM. In some embodiments, the display device 10 may be an electronic device with a display function, such as an electronic watch, an electronic clock, or a display interface of a remote control. In some embodiments, the display module LCM may be a liquid crystal display (LCD) module or a segment LCD module. When the display module LCM is an LCD module, the display device 10 may also be referred to as a liquid crystal display device; similarly, when the display module LCM is a segment LCD module, the display device 10 may be referred to as a segment LCD display device.

[0021] In this embodiment, the display module LCM is a segment LCD module with multiple pins. The multiple pins may be, for example, n+1 pins P_COM0 to P_COMn for receiving COM signals and m+1 pins P_SEG1 to P_SEGm for receiving SEG signals, where m and n are natural numbers and may be selected according to actual design.

[0022] Specifically, the display module LCM includes a plurality of pixels, each pixel receives a COM signal and a SEG signal through two corresponding pins, wherein because some or all of the plurality of pixels can share the COM signal, the number of pins used to receive the COM signal can be less than the number of pixels. On the other hand, each pixel receives a corresponding SEG signal, so the number of pins used to receive the SEG signal can correspond to the number of pixels one by one, but the present disclosure is not limited thereto. In the application of the segment code liquid crystal display device, each pixel can refer to a corresponding display field.

[0023] The controller 100 is coupled to the pins P_COM0-P_COMn and P_SEG0-P_SEGm of the display module LCM, and is used to generate a plurality of control signals Sc_0-Sc_x as LCD driving signals (i.e., the COM signal and the SEG signal) based on a power signal, and respectively provide them to the pixels in the display module LCM through the corresponding pins P_COM0-P_COMn and P_SEG0-P_SEGm to drive the display module LCM. In the present embodiment, the control signals Sc_0-Sc_x may be in a one-to-one correspondence with the pins P_COM0-P_COMn and P_SEG0-P_SEGm, that is, when driving the display module LCM, the control signal Sc_0 is the COM0 signal provided to the pin P_COM0, the control signal Sc_1 is the COM1 signal provided to the pin P_COM1, and so on; therefore, the number x of control signals may be less than or equal to m+n+2. However, the present disclosure is not limited thereto.

[0024] Taking a segment code liquid crystal display device that displays "8" as an example, it may include 7 display fields, so the display module LCM may include 1 pin P_COM0 (i.e. n=0) for receiving a COM signal and 7 pins P_SEG0~P_SEG6 (i.e. m=6) for receiving a SEG signal, so that each SEG signal pin P_SEG0~P_SEG6 is matched with the COM signal pin P_COM0 to form two corresponding pins of a display field to receive control signals Sc_0~Sc_7 issued by the controller 100, wherein the control signal Sc_0 is the COM signal provided to the pin P_COM0, the control signal Sc_1 is the SEG signal provided to the pin P_SEG0, and the control signal Sc_2 is the SEG signal provided to the pin P_SEG1, and the others can be deduced by analogy.

[0025] An example configuration of the controller 100 may be as follows Figure 2 As shown, Figure 2 Schematic diagram of a controller according to an embodiment of the present disclosure. Figure 1 and Figure 2 In addition to being used to drive the display module LCM, the controller 100 of this embodiment can also output control signals with corresponding test waveforms to each pin P_COM0~P_SEGm of the display module LCM in the test mode TM to detect each pixel / display field in the display module LCM, and can output a detection value indicating the short circuit degree / type of each pixel / display field.

[0026] Specifically, the controller 100 may include a signal generating circuit 110, an abnormality detecting circuit 120, and a power supply circuit 130. In addition to generating control signals Sc_0-Sc_x as LCD driving signals when driving the display module LCM, the signal generating circuit 110 may also be used to generate control signals Sc_0-Sc_x having test waveforms WF1 and WF2 based on the power signal VLCD in the test mode TM, and output the control signals Sc_0-Sc_x to corresponding pins, so as to sequentially test the short circuit degree of each pixel.

[0027] For example, Figure 2The signal output state of the pixel Pab is illustrated as an example. The signal generating circuit 110 outputs a first control signal Sc_a having a test waveform WF1 and a second control signal Sc_b having a test waveform WF2 to the corresponding two pins of the pixel Pab, so that the pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, and the pixels corresponding to the remaining pins are disabled in response to the received control signals. The detection value obtained at this time will reflect the degree of short circuit of the pixel Pab. After completing the detection of the pixel Pab, the signal generating circuit 110 can select the two pins corresponding to the next pixel to output the control signal having the test waveforms WF1 and WF2 to continue to detect the next pixel, and the first control signal Sc_a / second control signal Sc_b originally having the test waveforms WF1 / WF2 is now switched to a control signal that disables the corresponding pixel Pab. The testing of other pixels can be deduced in this way.

[0028] For example, if the two pins corresponding to the pixel Pab are the pins P_COM0 and the pin P_SEG0, the signal generating circuit 110 will output the control signal Sc_0 having the test waveform WF1 to the pin P_COM0, and output the control signal having the test waveform WF2 to the pin P_SEG0; the other pins P_COM1 to P_COMn and P_SEG1 to P_SEGm will receive the control signal that will not enable the pixels corresponding to the pins P_COM1 to P_COMn and P_SEG1 to P_SEGm. When the pixel Pab completes the detection, the signal generating circuit 110 will instead output the control signal having the test waveform WF2 to the pin P_SEG1 to enable the pixels corresponding to the pins P_COM0 and P_SEG1 to be tested, and the pin P_SEG0 will then receive the control signal that disables the pixel Pab.

[0029] In other words, the signal generating circuit 110 outputs a first control signal (such as Sc_a) having a test waveform WF1 and a second control signal (such as Sc_b) having a test waveform WF2 to the corresponding two pins of the pixel to be tested (such as Pab) in the display module LCM under the test mode TM, so that the abnormality detection circuit 120 generates a detection value CTV corresponding to the pixel to be tested.

[0030] It should be noted here that the short circuit refers to the circuit / pin associated with the pixel being unexpectedly electrically connected to the surrounding circuit / component / pin, so that the circuit / pin of the pixel can be seen as electrically connected to the surrounding circuit / component / pin through a short-circuit resistor, and causes leakage current through the short-circuit resistor, wherein the short-circuit degree / situation refers to the magnitude of the short-circuit resistor and / or the leakage current. A more severe short-circuit degree may indicate a larger leakage current / a smaller short-circuit resistor, while a milder short-circuit degree may indicate a smaller leakage current / a larger short-circuit resistor.

[0031] In some embodiments, the test waveforms WF1 and WF2 may be square waves that are in opposite phases to each other to form an AC signal to enable the corresponding pixel to be tested.

[0032] In some embodiments, the test waveforms WF1 and WF2 may be waveforms that conform to the LCD drive signal format; that is, the LCD drive signal may be directly used as the test signal for testing. Specifically, the waveform that conforms to the LCD drive signal format may be a step signal waveform having multiple steps (e.g., at least three steps) of different voltage levels in one cycle, and each step of the voltage level conforms to the output voltage under the LCD drive signal format. In other words, the voltage difference between the test waveforms WF1 and WF2 can constitute a periodic multi-step AC square wave that can drive LCD pixels. Specific examples of the controller 100 performing detection under different test waveforms WF1 and WF2 will be further described in subsequent embodiments.

[0033] Since the controller 100 can use the test waveforms WF1 and WF2 that conform to the LCD driving signal format for detection, the hardware of the signal generating circuit 110 can be implemented using a general LCD driver architecture without additional hardware configuration.

[0034] The abnormality detection circuit 120 can receive the power signal VLCD and be used to detect changes of the power signal VLCD in response to the test waveforms WF1 and WF2 in the test mode TM to generate detection values ​​CTV corresponding to the respective pins P_COM0 ˜P_SEGm.

[0035] Specifically, when the controller 100 sends the first control signal Sc_a and the second control signal Sc_b with test waveforms WF1 and WF2 to the corresponding pins to enable the pixel Pab to be tested, the state of the pixel Pab to be tested is similar to that in the driving mode, so the power signal VLCD will respond to the operating current of the pixel Pab to be tested and have a charging and discharging waveform similar to that in the driving mode.

[0036] In the case where there is no short circuit in the circuit / pin of the pixel Pab to be tested, the load current caused by the basic power consumption is very small, and the voltage level of the power signal VLCD will be relatively gentle when pulled down (i.e., the slope is small), and will also recover to the steady-state voltage relatively quickly when charged. On the contrary, when a short circuit occurs in the circuit / pin of the pixel Pab to be tested, the short circuit path will cause additional leakage current, so that the voltage level of the power signal VLCD is quickly pulled down (i.e., the slope is large), wherein the larger the leakage current, the faster the voltage level of the power signal VLCD is pulled down. In addition, the short-circuit resistance will also cause the power supply circuit 130 to recharge the voltage level of the power signal VLCD to the steady-state voltage for a longer time.

[0037] In other words, the variation of the power signal VLCD is related to the magnitude of the leakage current / short-circuit resistance, that is, it is related to the degree of the short circuit of the pin to be detected.

[0038] The controller 100 of the present embodiment utilizes the variation characteristics of the voltage level to obtain the detection value CTV reflecting the short-circuit degree of the pins P_COM0-P_SEGm and / or the wiring related to the detection pixel. In other words, the controller 100 of the present embodiment can output the control signals Sc_0-Sc_x having the test waveforms WF1 and WF2 in the test mode TM, and the detection power signal VLCD responds to the variation of the test waveforms WF1 and WF2 to generate the detection value CTV indicating the short-circuit degree of the pixel Pab to be tested.

[0039] The detection value CTV may be a value indicating the short circuit degree of the test pin in a proportional relationship, and may be, for example, a count value, a voltage value, or other types of values, depending on the actual implementation of the abnormality detection circuit.

[0040] It should be noted here that the short circuit described in the present disclosure does not limit the short-circuited pins / components / lines to have no impedance on their short-circuit paths, or to have only negligible impedance. As long as the pins / components at both ends can be equivalent to being connected through impedance, and the leakage current caused by the impedance path is identifiably greater than the load current caused by the basic power consumption, it may be a short circuit described in the present disclosure. For example, if there is a short-circuit impedance of 5 ohms, 50 ohms, 500 ohms or 5000 ohms between two pins, it can be regarded as a short circuit in the present disclosure, and the difference is only in the degree of short circuit.

[0041] In some embodiments, the abnormality detection circuit 120 may include a voltage detection unit 122 and a counting unit 124. The voltage detection unit 122 is used to detect the voltage level of the power signal VLCD in the test mode TM to generate trigger signals St1 and St2. The counting unit 124 is coupled to the voltage detection unit 122 and is used to count in response to the trigger signals St1 and St2 and generate a detection value CTV accordingly.

[0042] More specifically, the voltage detection unit 122 can generate a first trigger signal St1 to trigger the counting unit 124 to start counting when the voltage level of the power signal VLCD exceeds the first voltage Vt1 (which can be a voltage drop from a high voltage to less than the first voltage Vt1, or a voltage increase from a low voltage to greater than the first voltage Vt1), and generate a second trigger signal St2 to trigger the counting unit 124 to stop counting when the voltage level of the power signal VLCD exceeds the second voltage Vt2 (which can be a voltage drop from a high voltage to less than the second voltage Vt2, or a voltage increase from a low voltage to greater than the second voltage Vt2). In other words, the counting unit 124 starts counting in response to the first trigger signal St1, and stops counting in response to the second trigger signal St2. The voltage detection unit 122 may generate a first trigger signal St1 when the voltage level of the power signal VLCD starts to decrease from a steady-state voltage, or generate the first trigger signal St1 when the voltage level of the power signal VLCD reaches a valley voltage; in addition, the voltage detection unit 122 may generate a second trigger signal St2 when the voltage level of the power signal VLCD reaches a valley voltage, or generate the second trigger signal St2 when the voltage level of the power signal VLCD returns to a steady-state voltage.

[0043] In other words, the detection value CTV generated by the counting unit 124 can be a count value of the time required for the voltage level of the counting power signal VLCD to drop from the steady-state voltage to the valley voltage, a count value of the time required for the voltage level of the counting power signal VLCD to rise from the valley voltage to the steady-state voltage, or a count value of the time required for the voltage level of the counting power signal VLCD to drop from the steady-state voltage to the valley voltage and then rise back to the steady-state voltage, but the present disclosure is not limited to this.

[0044] Similar to what has been described previously, since the time required for the voltage level of the power signal VLCD to drop from the steady-state voltage to the valley voltage and then rise back to the steady-state voltage is related to the leakage current / short-circuit impedance of the pixel to be tested, and the leakage current / short-circuit impedance is related to the degree of short circuit, the count value obtained by the counting unit 124 can be used as the detection value CTV indicating the degree of short circuit. In other words, in this embodiment, the abnormality detection circuit 120 reflects the change amplitude of the power signal VLCD by counting the time when the voltage level of the power signal VLCD changes, and uses this as the detection value CTV indicating the degree of short circuit.

[0045] The power supply circuit 130 is coupled to the signal generating circuit 110 and the abnormality detecting circuit 120, and is used to generate a power signal VLCD and provide it to the signal generating circuit 110 and the abnormality detecting circuit 120. In actual applications, according to the different driving voltages required by the display module LCM, the power supply circuit 130 can be implemented using a charge pump, an internal analog voltage source, or an external voltage source, but the present disclosure is not limited thereto.

[0046] Through the above-mentioned method, the controller 100 disclosed in the present invention can more accurately detect the actual short-circuit degree of the pins P_COM0~P_SEGm corresponding to each pixel of the display module LCM, so that the availability of the display module LCM can be more accurately evaluated according to the required application scenario in the back-end application, avoiding excessive screening of modules with slight short-circuit conditions but not affecting the display in some applications, resulting in unnecessary increase in manufacturing costs; or avoiding the situation in some applications with high reliability requirements where mild short-circuit conditions are not screened out, resulting in unexpected product reliability risks.

[0047] In addition, compared to traditional detection methods, the controller 100 disclosed in the present invention does not need to use an input / output port (I / Oport) for detection, but can use a signal output that conforms to the LCD drive signal format and detect power supply signal changes to determine a short circuit condition, so that the detection mechanism can be directly integrated into the LCD drive control circuit without the need for additional hardware development costs.

[0048] It should be noted that the test mode TM can be a mode different from the normal driving situation that is enabled by user operation. As long as any controller has the function and / or operation that can be controlled to enable the above-mentioned detection of the short circuit degree of the pins of the display module LCM, it can be regarded as including the test mode, or including all operations under the test mode. In other words, even if the characteristics of the controller 100 described in the present disclosure cannot be directly observed in the appearance of a display device in operation, it does not necessarily mean that the controller included in the display device does not fall within the scope of rights claimed by the present disclosure. In fact, as long as it can be discovered / verified through any testing method or reverse engineering means (including conventional usage methods not indicated by the display device) that the controller included in the display device has the test mode, or operates in a test mode that complies with the scope of rights claimed by the present disclosure, the controller can be regarded as falling within the scope of rights claimed by the present disclosure.

[0049] The following match Figure 3 and Figure 4 The operation of the controller in the test mode is further explained by the signal timing of Figure 3 In accordance with Figure 2 A schematic diagram of signal timing of a controller in a test mode according to an embodiment of the present invention; and Figure 4 In accordance with Figure 2 A signal timing diagram of a controller in a test mode according to another embodiment of the present invention.

[0050] Please refer to Figure 2 and Figure 3 ,in Figure 3The signal timing when the controller 100 tests the pixel Pab of the display module LCM is shown as an example. In the present embodiment, the signal generating circuit 110 sends a first control signal Sc_a having a periodic square wave waveform and a second control signal Sc_b having a waveform opposite to that of the first control signal Sc_a (i.e., the phase difference between the two signals is 180 degrees) to the pixel Pab to be tested, wherein the first control signal Sc_a may be, for example, a signal sent to the COM pin of the pixel Pab, and the second control signal Sc_b may be, for example, a signal sent to the SEG pin of the pixel Pab, but the present disclosure is not limited thereto.

[0051] In addition, the signal generating circuit 110 can send a control signal having the same / in-phase waveform as one of the first control signal Sc_a and the second control signal Sc_b to other pins (or at least part of other pins) of the display module LCM, so that non-test pixels are not enabled. For example, when the first control signal Sc_a and the second control signal Sc_b are respectively given to the COM pin and the SEG pin of the pixel Pab, the signal generating circuit 110 can send a control signal having the same waveform as the first control signal Sc_a to other SEG pins that share the COM signal with the pixel Pab, so that other non-test pixels are not enabled.

[0052] While the pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, the power signal VLCD is repeatedly charged and discharged within a certain voltage range (eg, the range between voltage levels VL and VH) in response to the workload of the pixel Pab to maintain a substantially stable power supply.

[0053] In a normal state where none of the related pins / circuits of the pixel Pab are short-circuited, the time for the power signal VLCDn to discharge from the voltage level VH to the voltage level VL is Tfn, and the time for recharging from the voltage level VL to the voltage level VH is Trn, so a complete charge and discharge period Tn is the discharge period Tfn plus the charge period Trn.

[0054] In some embodiments, when a short circuit occurs at the associated pin / circuit of the pixel Pab, the additional leakage current will cause the power signal VLCDf to be quickly pulled down from the voltage level VH to the voltage level VL, so that the discharge period Tff will be shorter than the discharge period Tfn in the normal state. On the other hand, since the short circuit may cause an unexpected impedance to be connected in series, the series impedance caused by the short circuit will prolong the charging time of the power source VLCDf from the voltage level VL back to the voltage level VH, so the charging period Trf in the case of a short circuit will be longer than the charging period Trn in the normal state. In this way, when a short circuit occurs at the associated pin / circuit of the pixel Pab, a complete charging and discharging period Tf of the power signal VLCDf will be longer than the charging and discharging period Tn in the normal state.

[0055] Therefore, counting the charging period Tfn / Tff, the discharging period Trn / Trf, or the charging and discharging period Tn / Tf can be used to identify whether a short circuit occurs. Furthermore, according to the difference in specifications of the product to be tested, the above-mentioned different identification conditions can be selected for detection to improve the accuracy of the detection. For example, in the case of a small load detection application, it is more suitable to detect by counting the discharge period Tfn / Tff; and in the case of a large load or short-circuit impedance detection application, it is more suitable to detect by counting the charging period Trn / Trf, but the present disclosure is not limited to this.

[0056] Please refer to Figure 2 and Figure 4 ,in Figure 4 The signal timing when the controller 100 tests the pixel Pab of the display module LCM is also shown as an example. In this embodiment, the signal generating circuit 110 sends a first control signal Sc_a and a second control signal Sc_b with waveforms similar to / same as a conventional LCD driving signal to the pixel Pab to be tested, wherein the conventional LCD driving signal may be similar to a periodic multi-stage square wave with multiple levels such as voltage potentials V0 to V4 as shown in the figure.

[0057] The first control signal Sc_a of the present embodiment may be, for example, a signal sent to the COM pin of the pixel Pab, and the second control signal Sc_b may be, for example, a signal sent to the SEG pin of the pixel Pab, but the present disclosure is not limited thereto. The first control signal Sc_a and the second control signal Sc_b will form an alternating voltage difference VSEGab on the pixel Pab to enable the pixel Pab, wherein the maximum value of the voltage difference VSEGab is a voltage potential VP, which may be, for example, twice the difference between the voltage potentials V4 and V1.

[0058] Furthermore, in some embodiments, the signal generating circuit 110 may send a control signal having a fixed voltage level (eg, a ground level) to other pins (or at least part of other pins) of the display module LCM to disable non-test pixels.

[0059] In some other embodiments, the signal generating circuit 110 may also be similar to the aforementioned Figure 3 The embodiment sends a third control signal having the same / in-phase waveform as one of the first control signal Sc_a and the second control signal Sc_b to other pins (or at least part of other pins) of the display module LCM, so that the non-tested pixels are not enabled. In other words, for the non-tested pixels, the control signal received by the corresponding pin can have different forms, as long as the voltage difference formed by the corresponding pin is not enough to enable the non-tested pixels.

[0060] During the period when the pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, the changes of the power signal VLCDn in the normal state and the power signal VLCDf in the abnormal state (i.e., the state where a short circuit occurs) are similar to the above Figure 3 In the embodiment, that is, the discharge period Tff in the abnormal state will be shorter than the discharge period Tfn in the normal state, the charging period Trf in the abnormal state will be longer than the charging period Trn in the normal state, and the complete charge and discharge period Tf in the abnormal state will be longer than the complete charge and discharge period Tn in the normal state. Therefore, a counting method similar to the above can be used to determine whether the pins and circuits related to the pixel Pab currently being tested are abnormal.

[0061] Compared to Figure 3 In the embodiment, since the waveform of the LCD driving signal is directly used as the test waveform for testing, there is no need to perform any additional output setting modification or add any additional circuit for the signal generating circuit 110. The test can be implemented by only sending the corresponding test waveform to the pixel Pab to be tested in sequence according to the test order, so that the function and operation of the test mode can be easily implemented on the existing LCD driver, effectively reducing the manufacturing cost of designing and modifying the circuit.

[0062] Figure 5 This is a flowchart of a method for detecting the status of a display module according to an embodiment of the present disclosure. Figure 5 The state detection method of this embodiment can be applied to the above Figures 1 to 4In the display device and its controller described in the embodiment, the state detection method includes: in a test mode (such as TM), sending a first control signal (such as Sc_a) having a first test waveform (such as WF1) to one of the pins of the display module (such as LCM), and sending a second control signal (such as Sc_b) having a second test waveform (such as WF2) to another pin of the display module (step S110), wherein the one of the pins and the other of the pins are two pins corresponding to a pixel to be tested (such as Pab) in the display module.

[0063] Next, the power signal (such as VLCD) used to generate the control signal is detected (step S120), and a detection value (such as CTV) corresponding to the pixel to be tested is generated according to the change of the power signal (step S130), wherein the change of the power signal can be at least one of the charging period, the discharging period, and the charging and discharging period of the power signal. The detection value can represent whether a short circuit occurs in the related pin / line of the pixel to be tested and whether the short circuit is serious.

[0064] More specifically, the steps of the state detection method in some specific test scenarios can be as follows: Figure 6 As shown, Figure 6 The present invention is a flowchart of a method for detecting a state of a display module according to another embodiment of the present invention.

[0065] Please refer to Figure 6 In this embodiment, before conducting actual testing, engineers can first test the display modules of the same batch that are confirmed to be in normal condition, obtain the detection value of the display modules that are detected to be normal as the screening value (step S210), and use this screening value as the judgment standard for subsequent tests.

[0066] After obtaining the screening value, the controller may send a first control signal having a first test waveform and a second control signal having a second test waveform to a group of pins defined as detection pins in the display module (step S220) to enable the pixel to be tested. Step S220 is similar to step S110 of the aforementioned embodiment, and may refer to the above Figures 1 to 5 The relevant descriptions of the embodiments are given below and will not be repeated here.

[0067] In addition, the controller may also send a third control signal having a third test waveform to some or all of the remaining pins (step S230) to disable other non-test pixels. Depending on the test waveform used in step S220, the third test waveform may be the same as one of the first test waveform and the second test waveform, or a fixed voltage level, but the present disclosure is not limited thereto. Step S230 may also refer to the above Figures 1 to 5The relevant descriptions of the embodiments are given below and will not be repeated here.

[0068] Next, the controller detects the power signal used to generate the control signal (step S240), and counts the change time of the power signal to generate a detection value (step S250), and then determines whether the pixel currently being detected is abnormal by comparing the detection value and the screening value (step S260). The change time of the power signal can be at least one of the charging period, the discharging period, and the charging and discharging period of the power signal, and the present disclosure is not limited thereto.

[0069] If the pixel currently being detected is determined to be abnormal in step S260, the controller may further output the detection result and the related detection value (step S270); conversely, if the pixel currently being detected is determined to be normal in step S260, the controller may further determine whether the corresponding pins of all pixels have completed the test (step S280).

[0070] If there are still pixels that have not been tested, the controller selects a group of pins corresponding to an untested pixel as the detection pins (step S290), and returns to step S220 to perform the test to obtain the detection value. On the other hand, if it is determined in step S280 that all pixels have been tested, the controller will end the test process and leave the test mode.

[0071] It should be noted here that Figure 6 The step flow is only an illustrative example of the present disclosure. A person with ordinary knowledge in the field can refer to the above description and change the above step flow without affecting the test purpose. For example, in some embodiments, the controller can omit step S260, and output the test result to the engineer for judgment regardless of whether the test value exceeds the screening value. In other words, as long as a certain pixel to be tested of the display module is enabled by outputting a specific test waveform and other non-test pixels are disabled, and then the test method that indicates the abnormality of the related pins / circuits of the pixel to be tested is generated by detecting the change of the power supply signal, it belongs to the scope disclosed and protected by this application.

[0072] The present disclosure is not limited to the above-mentioned embodiments, and various changes can be made within the scope indicated in the claims. The embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present disclosure. Furthermore, by combining the technical means disclosed in each embodiment, new technical features can be formed.

[0073] In summary, the controller, segment code liquid crystal display device and display module status detection method disclosed in the present invention can more accurately detect the actual short circuit degree and abnormal situation of the pins corresponding to each pixel of the display module, so that the availability of the display module can be more accurately evaluated according to the required application scenario in the back-end application, thereby avoiding excessive screening of modules with slight short circuits but no effect on the display, resulting in unnecessary increase in manufacturing costs; or avoiding the risk of unexpected product reliability caused by the failure to screen out mild short circuits in some applications requiring high reliability. In addition, some embodiments of the present invention can set the functions and operations of the test mode on the existing LCD driver without any additional output setting modification or additional circuit addition, effectively reducing the manufacturing cost of designing and modifying the circuit.

Claims

1. A controller, adapted to drive a display module having a plurality of pixels, characterized in that: The controller comprises: a signal generating circuit, coupled to the display module, and generating a plurality of control signals for driving the pixels based on a power signal, wherein the signal generating circuit outputs a control signal having a test waveform in a test mode; and An abnormality detection circuit receives the power signal and is used to detect the change of the power signal in response to the test waveform in the test mode to generate a detection value corresponding to a pixel to be tested among the pixels.

2. The controller according to claim 1, characterized in that: Each of the pixels has two pins for receiving the control signal, and the control signal includes a first control signal having a first test waveform and a second control signal having a second test waveform; the signal generating circuit is used to output the first control signal and the second control signal to the two pins of the pixel to be tested in the test mode, so that the abnormality detection circuit generates the detection value corresponding to the pixel to be tested.

3. The controller according to claim 2, characterized in that: The control signal further includes a third control signal having a third test waveform; the signal generating circuit is used to output the third control signal to the pins of at least some of the pixels other than the pixel to be tested in the test mode, wherein the third test waveform is different from at least one of the first test waveform and the second test waveform.

4. The controller according to claim 2, characterized in that: The detection value indicates the degree of short circuit of the pin of the pixel to be tested in a proportional relationship.

5. The controller according to claim 2, characterized in that: The voltage difference between the first test waveform and the second test waveform constitutes a periodic multi-stage AC square wave.

6. The controller according to claim 2, characterized in that: The first test waveform and the second test waveform are periodic square waves in opposite phases to each other.

7. The controller according to claim 1, characterized in that: The abnormality detection circuit comprises: a voltage detection unit, used for detecting the voltage level of the power signal in the test mode to generate a trigger signal; and a counting unit, coupled to the voltage detection unit, for counting in response to the trigger signal and generating the detection value accordingly, The counting unit counts at least one of a falling period and a rising period of the voltage level of the power signal as the detection value.

8. A segment code liquid crystal display device, characterized in that: include: A one-segment code liquid crystal display module has a plurality of display segments, wherein each of the display segments has two pins; as well as a controller, coupled to the pins, for generating a plurality of control signals based on a power signal and outputting them to the pins respectively to drive the segment code liquid crystal display module; The controller outputs a control signal having a test waveform in a test mode, and detects changes in the power signal in response to the test waveform to generate a detection value indicating the degree of short circuit of one of the display fields.

9. The segment code liquid crystal display device according to claim 8, characterized in that: The controller comprises: a signal generating circuit, configured to receive the power signal to generate the control signal; a voltage detection unit, used for detecting the voltage level of the power signal in the test mode to generate a trigger signal; and A counting unit is coupled to the voltage detection unit and is used for counting in response to the trigger signal and generating the detection value accordingly.

10. A method for detecting the state of a display module, characterized in that: include: Sending a first control signal having a first test waveform to one of the plurality of pins of a display module, and sending a second control signal having a second test waveform to another of the pins of the display module, wherein the one of the pins and the another of the pins correspond to a pixel to be tested of the display module; detecting a power supply signal for generating the first and second control signals; and A detection value corresponding to the pixel to be tested is generated according to the change of the power signal.

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