Bonding method and bonding system

Abstract

The present disclosure relates to a bonding method and a bonding system capable of suppressing a decrease in bonding strength. The bonding method includes: preparing a first semiconductor substrate having a first surface and a second semiconductor substrate having a second surface; hydrophilizing the first surface of the first semiconductor substrate and the second surface of the second semiconductor substrate; bonding the first surface of the first semiconductor substrate and the second surface of the second semiconductor substrate after hydrophilization; and improving the bonding strength between the first semiconductor substrate and the second semiconductor substrate by performing heat treatment on the first semiconductor substrate and the second semiconductor substrate after the bonding is performed, in which improving the bonding strength comprises: performing heat treatment on the first semiconductor substrate and the second semiconductor substrate in a first temperature range; and heat-treating the first semiconductor substrate and the second semiconductor substrate at a target temperature after heat-treating within a first temperature range which is a temperature range lower than the target temperature.

Description

Technical Field

[0001] The present disclosure relates to a joining method and a joining system. Background Art

[0002] A technique is known in which two semiconductor wafers are temporarily bonded together by laminating them and then heat-treated at a high temperature (for example, see Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-103291 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] The present disclosure provides a technology capable of suppressing a decrease in bonding strength.

[0008] Solutions for solving problems

[0009] A bonding method according to one embodiment of the present invention includes: preparing a first semiconductor substrate having a first surface and a second semiconductor substrate having a second surface; hydrophilizing the first surface of the first semiconductor substrate and the second surface of the second semiconductor substrate; bonding the first surface of the first semiconductor substrate to the second surface of the second semiconductor substrate after the hydrophilization; and improving the bonding strength between the first semiconductor substrate and the second semiconductor substrate by heat treating the first semiconductor substrate and the second semiconductor substrate after the bonding, wherein improving the bonding strength includes: heat treating the first semiconductor substrate and the second semiconductor substrate within a first temperature range; and heat treating the first semiconductor substrate and the second semiconductor substrate at a target temperature after the heat treatment within the first temperature range, wherein the first temperature range is a temperature range lower than the target temperature.

[0010] Effects of the Invention

[0011] According to the present disclosure, it is possible to suppress a decrease in bonding strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view showing the joining system according to the first embodiment.

[0013] Figure 2 This is a flowchart showing the bonding method according to the first embodiment.

[0014] Figure 3: is a cross-sectional view showing an example of a first bare chip carrier and a bare chip.

[0015] Figure 4 is a cross-sectional view showing an example of a second bare chip carrier.

[0016] Figure 5 : is a cross-sectional view showing an example of a second bare chip carrier and a bare chip.

[0017] Figure 6 It is a cross-sectional view showing an example of a substrate.

[0018] Figure 7 This is a cross-sectional view showing an example of a substrate with a bare chip.

[0019] Figure 8 This is a cross-sectional view showing an example of the operation of the bare chip array device.

[0020] Fig. 9 It is a cross-sectional view showing an example of electrostatic adsorption.

[0021] Fig.10 This is a cross-sectional view showing an example of the operation of the bonding device.

[0022] Fig.11 It shows that Fig.10 A cross-sectional view showing an example of the subsequent operation.

[0023] Fig.12 This is a diagram showing an example of the change over time of the control temperature during heat treatment.

[0024] Fig.13 This is a diagram showing another example of the change over time of the control temperature during heat treatment.

[0025] Fig.14 It is a plan view showing a system according to the second embodiment.

[0026] Fig.15 It is a cross-sectional view showing an example of superimposed wafers.

[0027] Fig.16 It is a flowchart which shows the joining method which concerns on 2nd Embodiment.

[0028] Fig.17 It is a cross-sectional view showing an example of a bonding device.

[0029] Fig.18 This is a cross-sectional view showing an example of the operation of the bonding device.

[0030] Fig.19 It shows that Fig.18 A cross-sectional view showing an example of the subsequent operation.

[0031] Fig. 20 It shows that Fig.19 A cross-sectional view showing an example of the subsequent operation. DETAILED DESCRIPTION

[0032] Below, the exemplary embodiments of the present disclosure are described with reference to the accompanying drawings, which are not intended to be limiting. In all the drawings, the same or corresponding components or parts are marked with the same or corresponding reference numerals, and repeated descriptions are omitted. In this specification, the X-axis direction, the Y-axis direction, and the Z-axis direction are mutually perpendicular directions. The X-axis direction and the Y-axis direction are horizontal directions, and the Z-axis direction is a vertical direction.

[0033] [First embodiment]

[0034] (Joint system)

[0035] Reference Figures 1 to 11 The joining system 1 according to the first embodiment will be described. Figure 7 As shown, the bonding system 1 manufactures a substrate CW with a bare chip by bonding a bare chip CP to a substrate W. The bare chip CP is an example of a first semiconductor substrate, and the substrate W is an example of a second semiconductor substrate. The substrate CW with a bare chip includes a substrate W and a plurality of bare chips CP bonded to the substrate W.

[0036] The bare chip CP has a base substrate S1 and a device D1 formed on the base substrate S1. The base substrate S1 is, for example, a silicon wafer, a compound semiconductor wafer or a glass substrate. The device D1 includes a semiconductor element, a circuit or a terminal, etc. The device D1 is formed on the bonding surface CPa of the bare chip CP.

[0037] The substrate W includes a base substrate S2 and a plurality of devices D2 formed on the base substrate S2. The base substrate S2 is, for example, a silicon wafer, a compound semiconductor wafer or a glass substrate. The devices D2 include semiconductor elements, circuits or terminals, etc. The devices D2 are formed on the bonding surface Wa of the substrate W.

[0038] The device D1 of the bare chip CP is electrically connected to the device D2 of the substrate W. Although not shown in the figure, multiple devices D1 can be electrically connected to one device D2. Multiple devices D1 can have different functions, that is, different circuits. The device D1 of one bare chip CP can be electrically connected to the device D2 of the substrate W via the device D1 of another bare chip CP.

[0039] like Figure 1 As shown, the bonding system 1 includes a loading and unloading station 2, a processing station 3, and a control device 9. The loading and unloading station 2 and the processing station 3 are arranged in the order described from the negative side of the X-axis to the positive side of the X-axis.

[0040] The loading and unloading station 2 is equipped with a loading platform 20. Boxes C1 to C6 are placed on the loading platform 20. Box C1 is used to accommodate a plurality of bare chips CP held in a first bare chip carrier FC. Box C2 is used to accommodate a used first bare chip carrier FC from which at least a portion of the bare chips CP have been removed. Boxes C3 and C4 are used to accommodate a second bare chip carrier SC. Box C5 is used to accommodate a substrate W before bonding with a bare chip CP. Box C6 is used to accommodate a substrate CW with a bare chip.

[0041] like Figure 3 As shown, the first bare chip carrier FC has a tape TP for bonding the bare chip CP, and a frame FR for bonding the periphery of the tape TP. A plurality of bare chips CP are arranged in the opening of the frame FR. The plurality of bare chips CP are obtained, for example, by cutting the substrate while the substrate is bonded to the tape TP. The bonding surface CPa of the bare chip CP is protected by a protective film PF before cutting. The protective film PF is arranged on the side opposite to the tape TP across the bare chip CP. The protective film PF is removed before bonding the bare chip CP to the substrate W.

[0042] like Figure 5 As shown, the second bare chip carrier SC holds multiple bare chips CP removed from the first bare chip carrier FC. The second bare chip carrier SC is, for example, an electrostatic carrier. The electrostatic carrier electrostatically adsorbs the multiple bare chips CP. The electrostatic carrier can perform vacuum adsorption while electrostatically adsorbing the multiple bare chips CP. After the electrostatic adsorption force disappears, the multiple bare chips CP can continue to be held by the vacuum adsorption force.

[0043] In the present embodiment, the second bare chip carrier SC holds a plurality of bare chips CP having the same function, but may also hold a plurality of bare chips CP having different functions. In the latter case, a plurality of first bare chip carriers FC are prepared according to the functions of the bare chips CP. It is also possible to transfer a plurality of bare chips CP having different functions from a plurality of first bare chip carriers FC to one second bare chip carrier SC.

[0044] The bare chip CP is transferred from the first bare chip carrier FC to the second bare chip carrier SC because the protective film PF is removed from the bare chip CP and the bonding surface CPa of the bare chip CP is modified before bonding the bare chip CP to the substrate W. This is to prevent the tape TP of the first bare chip carrier FC from being damaged during the modification of the bonding surface CPa. The details of the second bare chip carrier SC will be described later.

[0045] like Figure 1As shown, the loading / unloading station 2 includes a transfer area 21, a first bare chip carrier transfer arm 22, a second bare chip carrier transfer arm 23, and a substrate transfer arm 24. Hereinafter, the first bare chip carrier transfer arm 22, the second bare chip carrier transfer arm 23, and the substrate transfer arm 24 are sometimes collectively described as transfer arms 22-24.

[0046] The conveying area 21 is adjacent to the mounting table 20. The conveying arms 22 to 24 hold and convey the first bare chip carrier FC, the second bare chip carrier SC or the substrate W in the conveying area 21. The conveying arms 22 to 24 can each move in the horizontal direction (two directions of the X-axis direction and the Y-axis direction) and the vertical direction, and rotate around the vertical axis.

[0047] The transporting device is composed of the transporting arms 22 to 24 and a driving unit (not shown) for moving or rotating the transporting arms 22 to 24. The transporting arms 22 to 24 can be Figure 1 As shown, the transfer arms 22 to 24 are mounted on the same Y-axis slide and move simultaneously in the Y-axis direction, or they may be mounted on different Y-axis slides and move independently in the Y-axis direction. The transfer arms 22 to 24 are arranged at different height positions.

[0048] The loading / unloading station 2 is provided with a conveyor 25 on the side opposite to the mounting table 20 across the conveying area 21. The conveyor 25 is provided between the conveying area 21 of the loading / unloading station 2 and the conveying area 31 of the processing station 3, and is used to relay the first bare chip carrier FC, the second bare chip carrier SC or the substrate W between these areas. A plurality of conveyors 25 may be stacked in the Z-axis direction.

[0049] The processing station 3 includes a transfer area 31, a first bare chip carrier transfer arm 32, a second bare chip carrier transfer arm 33, and a substrate transfer arm 34. Hereinafter, the first bare chip carrier transfer arm 32, the second bare chip carrier transfer arm 33, and the substrate transfer arm 34 may be collectively described as transfer arms 32-34.

[0050] The conveying area 31 extends in the X-axis direction. The conveying arms 32 to 34 hold and convey the first bare chip carrier FC, the second bare chip carrier SC or the substrate W in the conveying area 31. The conveying arms 32 to 34 can each move in the horizontal direction (two directions of the X-axis direction and the Y-axis direction) and the vertical direction, and rotate around the vertical axis.

[0051] The transporting device is composed of the transporting arms 32 to 34 and a driving unit (not shown) for moving or rotating the transporting arms 32 to 34. The transporting arms 32 to 34 can be Figure 1As shown, the transfer arms 32 to 34 may be mounted on the same X-axis slide and moved simultaneously in the X-axis direction, or may be mounted on different X-axis slides and moved independently in the X-axis direction. The transfer arms 32 to 34 are arranged at different height positions.

[0052] The processing station 3 includes a bare chip arrangement device 35, a cleaning device 36, a first activation device 37, a first hydrophilization device 38, a reversing device 39, a second activation device 40, a second hydrophilization device 41, a bonding device 42, and an annealing device 43. These devices 35 to 43 are adjacent to the conveying area 31 and are respectively arranged on the Y-axis positive direction side or the Y-axis negative direction side of the conveying area 31.

[0053] like Figure 8 As shown, the bare chip arrangement device 35 transfers the bare chip CP from the first bare chip carrier FC to the second bare chip carrier SC. This can prevent the tape TP of the first bare chip carrier FC from being damaged when modifying the bonding surface CPa. The bare chip arrangement device 35 will be described in detail later.

[0054] The cleaning device 36 removes the protection film PF from the bare chip CP while the bare chip CP is held by the second bare chip carrier SC. In addition, the cleaning device 36 cleans the bonding surface Cpa of the bare chip CP, thereby improving the quality of the subsequent treatment of the bonding surface CPa.

[0055] The first activation device 37 activates the bonding surface CPa of the bare chip CP while the bare chip CP is held by the second bare chip carrier SC. The first activation device 37 is, for example, a plasma processing device. In the first activation device 37, oxygen gas as a processing gas is excited to plasma under reduced pressure, thereby ionizing it. The bonding surface CPa of the bare chip CP is activated by irradiating oxygen ions to the bonding surface CPa of the bare chip CP. The processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.

[0056] The first hydrophilizing device 38 hydrophilizes the bonding surface CPa of the bare chip CP while the bare chip CP is held by the second bare chip carrier SC. For example, the first hydrophilizing device 38 supplies pure water (e.g., deionized water) onto the bare chip CP while rotating the second bare chip carrier SC held on a rotating holding disk (holding disk: chuck). The pure water provides OH groups (silanol groups) to the bonding surface CPa of the bare chip CP that has been activated in advance. The bare chip CP can be bonded to the substrate W by hydrogen bonds between the OH groups.

[0057] The flipping device 39 flips the second bare chip carrier SC upside down while the bare chip CP is held by the second bare chip carrier SC. The plurality of bare chips CP can be flipped upside down at the same time so that the bonding surface CPa of each bare chip CP faces downward. In addition, the flipping device 39 can also be provided inside the bonding device 42.

[0058] The second activation device 40 activates the bonding surface Wa of the substrate W. The second activation device 40 is, for example, a plasma processing device. In the second activation device 40, oxygen gas as a processing gas is excited to plasma under reduced pressure, thereby ionizing it. The bonding surface Wa of the substrate W is activated by irradiating oxygen ions to the bonding surface Wa of the substrate W. The processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.

[0059] The second hydrophilizing device 41 hydrophilizes the bonding surface Wa of the substrate W. For example, the second hydrophilizing device 41 rotates the substrate W held on the rotating holding disk while supplying pure water (e.g., deionized water) onto the substrate W. The pure water provides OH groups to the bonding surface Wa of the pre-activated substrate W. The bare chip CP can be bonded to the substrate W by hydrogen bonds between the OH groups.

[0060] like Fig.10 and Fig.11 As shown, the bonding device 42 removes the bare chip CP from the second bare chip carrier SC, and bonds the bare chip CP to the substrate W in such a manner that the bonding surface CPa of the removed bare chip CP faces the bonding surface Wa of the substrate W. A substrate CW with a bare chip is obtained. The device D1 of the bare chip CP is electrically connected to the device D2 of the substrate W. The details of the bonding device 42 will be described later.

[0061] The annealing device 43 performs heat treatment on the substrate CW with the bare chip. Before the heat treatment, the bare chip CP and the substrate W are bonded by hydrogen bonds between OH groups. Through the heat treatment, a dehydration condensation reaction occurs, and a covalent bond is generated, and the bonding strength between the bare chip CP and the substrate W is improved. For example, a plurality of annealing devices 43 are stacked in the Z-axis direction. The plurality of annealing devices 43 are configured to perform heat treatment on the substrate CW with the bare chip at different set temperatures. The plurality of annealing devices 43 include an annealing device whose set temperature is a target temperature, and an annealing device whose set temperature is a first temperature range lower than the target temperature. The target temperature is a temperature at which a dehydration condensation reaction will occur and a covalent bond will be generated. The target temperature is, for example, above 350°C. In the present embodiment, the plurality of annealing devices 43 include five annealing devices 43a to 43e. The set temperatures of the annealing devices 43a, 43b, 43c, 43d, and 43e are 50°C, 100°C, 150°C, 200°C, and 350°C (target temperatures), respectively. The number of the annealing devices 43 is not limited to the number shown in the figure.

[0062] The control device 9 is, for example, a computer, and includes a computing unit 91 such as a CPU (Central Processing Unit) and a storage unit 92 such as a memory. The storage unit 92 stores a program for controlling various processes executed in the bonding system 1. The control device 9 controls the operation of the bonding system 1 by causing the computing unit 91 to execute the program stored in the storage unit 92. A unit control unit for controlling the operation of the unit may be provided for each unit constituting the bonding system 1, and a system control unit for uniformly controlling a plurality of unit control units may be provided. The control device 9 may also be constituted by a unit control unit and a system control unit.

[0063] (Joining method)

[0064] Reference Figure 2 The joining method according to the first embodiment is described below. Figure 2 processing.

[0065] First, the first bare chip carrier transfer arm 22 takes out a plurality of bare chips CP together with the first bare chip carrier FC from the cassette C1 and transfers them to the conveyor 25. Next, the first bare chip carrier transfer arm 32 takes out a plurality of bare chips CP together with the first bare chip carrier FC from the conveyor 25 and transfers them to the bare chip arrangement device 35.

[0066] The second chip carrier transfer arm 23 takes out the second chip carrier SC from the cassette C3 and transfers it to the conveyor 25 . Next, the second chip carrier transfer arm 33 takes out the second chip carrier SC from the conveyor 25 and transfers it to the chip array device 35 .

[0067] Next, the bare chip arrangement device 35 transfers the bare chips CP from the first bare chip carrier FC to the second bare chip carrier SC (step S101 ). After that, the second bare chip carrier transfer arm 33 takes out the plurality of bare chips CP together with the second bare chip carrier SC from the bare chip arrangement device 35 and transfers them to the cleaning device 36 .

[0068] Next, the cleaning device 36 removes the protection film PF from the bare chip CP while the bare chip CP is held by the second bare chip carrier SC (step S102 ). Thereafter, the second bare chip carrier transfer arm 33 takes out the plurality of bare chips CP together with the second bare chip carrier SC from the cleaning device 36 and transfers them to the first activation device 37 .

[0069] Next, the first activation device 37 activates the bonding surface CPa of the bare chip CP while the bare chip CP is held by the second bare chip carrier SC (step S103). After that, the second bare chip carrier transfer arm 33 takes out the plurality of bare chips CP together with the second bare chip carrier SC from the first activation device 37 and transfers them to the first hydrophilization device 38.

[0070] Next, the first hydrophilizing device 38 hydrophilizes the bonding surface CPa of the bare chip CP while the bare chip CP is held by the second bare chip carrier SC (step S104). After that, the second bare chip carrier transfer arm 33 takes out the plurality of bare chips CP together with the second bare chip carrier SC from the first hydrophilizing device 38 and transfers them to the flipping device 39.

[0071] Next, the flipping device 39 flips the second bare chip carrier SC upside down while the bare chip CP is held by the second bare chip carrier SC (step S105). After that, the second bare chip carrier transfer arm 33 takes out the plurality of bare chips CP together with the second bare chip carrier SC from the flipping device 39 and transfers them to the bonding device 42.

[0072] The following steps S106 and S107 are performed in parallel with the above-mentioned steps S101 to S105. First, the substrate transfer arm 24 takes out the substrate W from the cassette C5 and transfers it to the conveyor 25. Then, the substrate transfer arm 34 takes out the substrate W from the conveyor 25 and transfers it to the second activation device 40.

[0073] Next, the second activation device 40 activates the bonding surface Wa of the substrate W (step S106 ). Thereafter, the substrate transfer arm 34 takes out the substrate W from the second activation device 40 and transfers it to the second hydrophilization device 41 .

[0074] Next, the second hydrophilizing device 41 hydrophilizes the bonding surface Wa of the substrate W (step S107 ). Thereafter, the substrate transfer arm 34 takes out the substrate W from the second hydrophilizing device 41 and transfers it to the bonding device 42 .

[0075] Next, the bonding device 42 removes the bare chip CP from the second bare chip carrier SC, and bonds the bare chip CP to the substrate W in such a manner that the bonding surface CPa of the removed bare chip CP faces the bonding surface Wa of the substrate W (step S108). Thus, a substrate CW with a bare chip is obtained. Thereafter, the substrate transfer arm 34 takes out the substrate CW with a bare chip from the bonding device 42 and transfers it to the annealing device 43.

[0076] Next, the annealing device 43 performs heat treatment on the substrate CW with bare chips (step S109). As a result, the bonding strength between the bare chip CP and the substrate W is improved. The details of the heat treatment will be described later. After that, the substrate conveying arm 34 takes out the substrate CW with bare chips from the annealing device 43 and conveys it to the conveying device 25. Finally, the substrate conveying arm 24 takes out the substrate CW with bare chips from the conveying device 25 and stores it in the box C6. The substrate CW with bare chips is carried out from the bonding system 1 in a state of being stored in the box C6.

[0077] After step S101, the first die carrier transfer arm 32 takes out the first die carrier FC from the die array device 35 and transfers it to the conveyor 25. Then, the first die carrier transfer arm 22 takes out the first die carrier FC from the conveyor 25 and stores it in the cassette C2.

[0078] After step S108, the second chip carrier transfer arm 33 takes out the second chip carrier SC from the bonding device 42 and transfers it to the conveyor 25. Then, the second chip carrier transfer arm 23 takes out the second chip carrier SC from the conveyor 25 and stores it in the cassette C4.

[0079] (Bare Chip Arrangement Device)

[0080] Reference Figure 8 and Fig. 9 The details of the bare chip arrangement device 35 and the second bare chip carrier SC are described below. Figure 8 As shown, the bare chip arrangement device 35 transfers the bare chip CP from the first bare chip carrier FC to the second bare chip carrier SC. Thus, when modifying the bonding surface CPa, a bare chip carrier with relatively excellent durability can be used.

[0081] The second bare chip carrier SC is not particularly limited as long as it has better durability than the first bare chip carrier FC, and is, for example, an electrostatic carrier having, for example, a conductive substrate SC1 and an insulating film SC2, and electrostatically adsorbing the bare chip CP on the side opposite to the conductive substrate SC1 with respect to the insulating film SC2.

[0082] The conductive substrate SC1 is made of, for example, silicon, aluminum, aluminum alloy, stainless steel, or titanium. One or more through holes H1 may be formed in the conductive substrate SC1 for each bare chip CP. By supplying gas to the through hole H1 or inserting a pin (not shown) into the through hole H1, the bare chip CP can be peeled off from the second bare chip carrier SC. There is no particular limitation on the number and arrangement of the through holes H1.

[0083] like Fig. 9As shown, the insulating film SC2 maintains the electrostatic adsorption force by restricting the movement of charges between the base substrate S1 of the bare chip CP and the conductive substrate SC1. The dielectric breakdown voltage of the insulating film SC2 is preferably 30 kV or more, and more preferably 40 kV or more.

[0084] The insulating film SC2 is preferably made of a flexible material, specifically a material with an elastic modulus of 2 GPa or less, and more preferably a material with an elastic modulus of 0.5 GPa or less. From the perspective of durability when modifying the bonding surface CPa, for example, polyimide or EVA (ethylene-vinyl acetate copolymer) is used. The thickness of the insulating film SC2 is, for example, 10 μm.

[0085] A through hole connected to the through hole H1 of the conductive substrate SC1 may be formed in the insulating film SC2. The diameter of the through hole of the insulating film SC2 is preferably smaller than the diameter of the through hole H1 of the conductive substrate SC1. In addition, there may be no through hole. In this case, the bare chip CP can be removed by expanding the insulating film SC2.

[0086] The second bare chip carrier SC preferably has the same diameter as the substrate W. In this case, the second bare chip carrier transport arm 23 and the substrate transport arm 24 can use the same type of components (that is, the same size and the same shape), thereby reducing costs. The second bare chip carrier transport arm 33 and the substrate transport arm 34, the first activation device 37 and the second activation device 40, or the first hydrophilization device 38 and the second hydrophilization device 41 can also use the same type of components, thereby reducing costs. It is also possible to suppress the enlargement of the device.

[0087] like Figure 8 As shown, the bare chip arrangement device 35 includes a first bare chip carrier holding portion 351, a pressing portion 352, a second bare chip carrier holding portion 353, and a bare chip conveying mechanism 354. The first bare chip carrier holding portion 351 holds the first bare chip carrier FC from below the first bare chip carrier FC. The first bare chip carrier FC holds the bare chip CP in a state where the bonding surface CPa of the bare chip CP faces upward. The first bare chip carrier holding portion 351 holds the frame FR of the first bare chip carrier FC, but does not hold the tape TP.

[0088] The pressing part 352 partially presses the bare chip CP through the tape TP and partially deforms the tape TP. The bare chip CP can be lifted up individually, and friction between the bare chips CP can be suppressed when picking up the bare chip CP. The pressing part 352 and the first bare chip carrier holding part 351 can move relatively, so that the position of lifting the bare chip CP can be changed.

[0089] The second bare chip carrier holding portion 353 holds the second bare chip carrier SC from below the second bare chip carrier SC. The second bare chip carrier SC holds the bare chip CP in a state where the bonding surface CPa of the bare chip CP faces upward. Similarly, the first bare chip carrier FC also holds the bare chip CP in a state where the bonding surface CPa of the bare chip CP faces upward. Therefore, the bare chip conveying mechanism 354 also conveys the bare chip CP in a state where the bonding surface CPa of the bare chip CP faces upward. The bare chip conveying mechanism 354 does not turn the bare chip CP upside down.

[0090] The bare chip conveying mechanism 354 has an adsorption head 355 for adsorbing the bare chip CP. The adsorption head 355 is arranged above the bare chip CP. The bonding surface CPa of the bare chip CP is covered by the protective film PF, and the adsorption head 355 adsorbs the bare chip CP through the protective film PF. The adsorption head 355 contacts the protective film PF and does not contact the bare chip CP. Therefore, it is possible to suppress damage to the bare chip CP.

[0091] like Fig. 9 As shown, the bare chip arrangement device 35 includes a charge supply unit 356 and a charge removal unit 358. The charge supply unit 356 applies a voltage to the conductive substrate SC1 to provide a charge of a first polarity (e.g., positive) to the conductive substrate SC1. The charge removal unit 358 removes the charge of the first polarity from the bare chip CP, thereby leaving a charge of a second polarity (e.g., negative) opposite to the first polarity in the bare chip CP.

[0092] The first polarity charge is accumulated in the conductive substrate SC1, and the second polarity charge is accumulated in the bare chip CP. As a result, a potential difference is generated between the conductive substrate SC1 and the bare chip CP via the insulating film SC2, thereby generating an electrostatic adsorption force. The generated electrostatic adsorption force is maintained even after the application of the voltage to the conductive substrate SC1 and the removal of the charge of the bare chip CP are released.

[0093] The charge supply unit 356 includes, for example, a feed pin 357 in contact with the conductive substrate SC1. The feed pin 357 is provided in, for example, the second bare chip carrier holding unit 353 and is electrically connected to a power source (not shown). The charge removal unit 358 includes, for example, a ground line 359. The ground line 359 removes the charge of the first polarity from the bare chip CP via, for example, the protective film PF.

[0094] In this embodiment, the ground wire 359 is embedded in the adsorption head 355, but may be provided separately from the adsorption head 355. In this embodiment, the bare chips CP are electrostatically adsorbed one by one, but the plurality of bare chips CP may be electrostatically adsorbed simultaneously after being arranged on the insulating film SC2.

[0095] As described above, the insulating film SC2 is made of a flexible material. When the bare chip CP is pressed against the insulating film SC2 by electrostatic attraction, the insulating film SC2 deforms to discharge air from between the bare chip CP and the insulating film SC2, thereby generating a vacuum attraction between the bare chip CP and the insulating film SC2.

[0096] Even if the electrostatic adsorption force disappears due to charge leakage from the conductive substrate SC1 or the bare chip CP, the plurality of bare chips CP can be held by the vacuum adsorption force. The charge leakage may be caused by supplying a processing liquid to the bare chip CP during removal of the protective film PF or modification of the bonding surface CPa.

[0097] (Joining device)

[0098] Reference Fig.10 and Fig.11 The details of the joining device 42 will be described below. Fig.10 and Fig.11 As shown, the bonding device 42 removes the bare chip CP from the second bare chip carrier SC and bonds the bare chip CP to the substrate W in such a manner that the bonding surface CPa of the removed bare chip CP faces the bonding surface Wa of the substrate W. A substrate CW with bare chips is obtained. The device D1 of the bare chip CP is electrically connected to the device D2 of the substrate W.

[0099] The bonding device 42 includes, for example, a bare chip carrier holding portion 421, a substrate holding portion 422, a first bare chip conveying mechanism 423, and a second bare chip conveying mechanism 424. The bare chip carrier holding portion 421 holds the second bare chip carrier SC from above the second bare chip carrier SC in a state where the bonding surfaces CPa of the plurality of bare chips CP held on the second bare chip carrier SC are facing downward. The substrate holding portion 422 holds the substrate W from below the substrate W in a state where the bonding surface Wa of the substrate W is facing upward. The first bare chip conveying mechanism 423 receives the bare chip CP from the second bare chip carrier SC and conveys the bare chip CP in a state where the bonding surface CPa of the bare chip CP is facing downward. The second bare chip conveying mechanism 424 receives the bare chip CP from the first bare chip conveying mechanism 423 and bonds the bare chip CP to the substrate W in a state where the bonding surface CPa of the bare chip CP is facing downward.

[0100] According to the present embodiment, before the bare chip carrier holding portion 421 holds the second bare chip carrier SC, the flipping device 39 flips the second bare chip carrier SC upside down. A plurality of bare chips CP can be flipped upside down in advance, so that the bonding surface CPa of each bare chip CP can face downward. The first bare chip conveying mechanism 423 and the second bare chip conveying mechanism 424 do not flip the bare chip CP upside down individually in the middle of conveying the bare chip CP individually. The mechanism for flipping the bare chip CP upside down individually can be deleted, so that dust from the mechanism can be suppressed. In addition, the structure of the first bare chip conveying mechanism 423 and the second bare chip conveying mechanism 424 can be simplified. Moreover, the number of flipping times can be reduced, so that productivity can be improved.

[0101] According to the present embodiment, the bare chip carrier holding portion 421 holds the second bare chip carrier SC from above the second bare chip carrier SC, and the substrate holding portion 422 holds the substrate W from below the substrate W. By holding the substrate W that is larger and heavier than the bare chip CP from below the substrate W, the substrate W can be stably held, and the bare chip CP can be joined to the desired position of the substrate W. The accuracy of the joining position mainly depends on the position alignment accuracy between the second bare chip conveying mechanism 424 and the substrate holding portion 422. The position alignment accuracy between the first bare chip conveying mechanism 423 and the bare chip carrier holding portion 421 can be lower than the position alignment accuracy. Therefore, even if the bare chip carrier holding portion 421 holds the second bare chip carrier SC from above the second bare chip carrier SC, the accuracy of the joining position will not deteriorate.

[0102] In addition, in the present embodiment, the bare chip carrier holding portion 421 holds the second bare chip carrier SC, but may also hold the first bare chip carrier FC. When the bonding system 1 does not modify the bonding surface CPa of the bare chip CP, it is not necessary to transfer the bare chip CP from the first bare chip carrier FC to the second bare chip carrier SC. Therefore, the bare chip carrier holding portion 421 may also hold the first bare chip carrier FC.

[0103] When the bare chip carrier holding portion 421 holds the first bare chip carrier FC, the flipping device 39 flips the first bare chip carrier FC upside down. A plurality of bare chips CP can be flipped upside down in advance, so that the bonding surface CPa of each bare chip CP can face downward. The mechanism for flipping the bare chip CP upside down individually can be deleted, so that dust from the mechanism can be suppressed. In addition, the structures of the first bare chip conveying mechanism 423 and the second bare chip conveying mechanism 424 can be simplified. Furthermore, the number of flippings can be reduced, so that productivity can be improved. Furthermore, the accuracy of the bonding position between the bare chip CP and the substrate W can also be improved.

[0104] The first bare chip conveying mechanism 423 includes, for example, a first suction head 423a and a first driving unit 423b. The first suction head 423a is disposed below the bare chip CP and suctions the bonding surface CPa of the bare chip CP. The first suction head 423a is movable, for example, in the X-axis direction and the Z-axis direction. The first driving unit 423b moves the first suction head 423a.

[0105] The first adsorption head 423a preferably adsorbs the bonding surface CPa of the bare chip CP in a non-contact manner. That is, the first adsorption head 423a preferably adsorbs the bonding surface CPa of the bare chip CP in a state where a gap is formed between the bare chip CP. It is possible to prevent the bonding surface CPa of the bare chip CP from being contaminated. The first adsorption head 423a is, for example, an ultrasonic type or a Bernoulli type. The ultrasonic type utilizes an extrusion effect based on ultrasonic vibrations, and the Bernoulli type utilizes the Bernoulli effect. Compared with the Bernoulli type, the ultrasonic type can suppress displacement in the horizontal direction.

[0106] The second bare chip conveying mechanism 424 includes, for example, a second suction head 424a and a second driving unit 424b. The second suction head 424a is disposed above the bare chip CP and suctions the back surface CPb of the bare chip CP that faces in the opposite direction to the bonding surface Cpa. Since the back surface CPb does not matter even if it is contaminated, the second suction head 424a contacts the bare chip CP.

[0107] The second adsorption head 424a can be moved in, for example, the X-axis direction, the Y-axis direction, the Z-axis direction, and the θ direction. The θ direction is the circumferential direction of the vertical rotation center line. In other words, the second adsorption head 424a can rotate around the vertical rotation center line. The second driving unit 424b moves the second adsorption head 424a.

[0108] like Fig.10 and Fig.11 As shown, the bonding device 42 may include a first moving portion 428 and a second moving portion 429. The first moving portion 428 moves the bare chip carrier holding portion 421 in the horizontal direction. The first moving portion 428 may also move the bare chip carrier holding portion 421 in the vertical direction. The second moving portion 429 moves the substrate holding portion 422 in the horizontal direction. The second moving portion 429 may also move the substrate holding portion 422 in the vertical direction.

[0109] According to the present embodiment, the chip carrier holding portion 421 holds the second chip carrier SC from above the second chip carrier SC, and the substrate holding portion 422 holds the substrate W from below the substrate W. Therefore, the second chip carrier SC and the substrate W can be arranged at different heights. Therefore, the chip carrier holding portion 421 and the substrate holding portion 422 can be arranged at different heights. As a result, when the chip carrier holding portion 421 is observed from above, the moving range of the chip carrier holding portion 421 can overlap with the moving range of the substrate holding portion 422. Thus, the packaging of the bonding device 42 can be reduced.

[0110] The substrate holding portion 422 can move in a horizontal first axis direction and a horizontal second axis direction orthogonal to the first axis direction. The first axis direction is, for example, the X axis direction, and the second axis direction is, for example, the Y axis direction. The substrate holding portion 422 can move in two directions, the positive direction of the X axis and the negative direction of the X axis. In addition, the substrate holding portion 422 can move in two directions, the positive direction of the Y axis and the negative direction of the Y axis.

[0111] The bare chip carrier holding portion 421 may be movable in both the first axis direction and the second axis direction, or may be movable only in the second axis direction of the first axis direction and the second axis direction. In the latter case, when the bare chip carrier holding portion 421 is observed from above, the moving range of the bare chip carrier holding portion 421 and the moving range of the substrate holding portion 422 may overlap in the first axial direction. In the latter case, the package of the bonding device 42 can be further reduced compared to the former case.

[0112] like Fig.10 and Fig.11 As shown, the bonding device 42 may include a pressing mechanism 430. The pressing mechanism 430 presses the bare chip CP downward relative to the second bare chip carrier SC held by the bare chip carrier holding portion 421. The pressing mechanism 430 presses the bare chip CP downward individually to separate the bare chip CP from the second bare chip carrier SC individually.

[0113] The pressing mechanism 430 peels the bare chip CP from the second bare chip carrier SC by, for example, supplying gas to the through hole H1 of the conductive substrate SC1 or inserting a pin (not shown) into the through hole H1. The number and arrangement of the through holes H1 are not particularly limited. The insulating film SC2 may or may not have a through hole.

[0114] Furthermore, in the present embodiment, the bare chip carrier holding portion 421 holds the second bare chip carrier SC, but may hold the first bare chip carrier FC as described above.

[0115] (Heat Treatment)

[0116] The inventors of the present invention have found that when the substrate CW with bare chips is heat-treated at a certain target temperature, the bonding strength between the bare chip CP and the substrate W may decrease. In addition, the inventors of the present invention have found that the bonding strength of the substrate CW with bare chips can be suppressed from decreasing by heat-treating the substrate CW with bare chips within a first temperature range lower than the target temperature before heat-treating the substrate CW with bare chips at the target temperature. The inventors of the present invention presume that the reason for the above effect is as follows.

[0117] Before the heat treatment, the bare chip CP is bonded to the substrate W by hydrogen bonding between OH groups. The heat treatment generates a dehydration condensation reaction of the following reaction formula (1) and an oxidation reaction of the following reaction formula (2), thereby improving the bonding strength between the bare chip CP and the substrate W.

[0118] Si-OH Si-OH→Si-O-Si+H2O (1)

[0119] Si+H2O→SiO+H2 (2)

[0120] At this time, when H2O generated in the dehydration condensation reaction of reaction formula (1) remains at the bonding interface between the bare chip CP and the substrate W, pores (voids) are generated at the bonding interface, which becomes the main reason for the decrease in the bonding strength between the bare chip CP and the substrate W. For example, when the amount of H2O generated in the dehydration condensation reaction of reaction formula (1) (hereinafter also referred to as "H2O generation amount") is greater than the amount of H2O consumed (absorbed) in the oxidation reaction of reaction formula (2) (hereinafter also referred to as "H2O absorption amount"), H2O is likely to remain at the bonding interface between the bare chip CP and the substrate W. Therefore, during heat treatment, it is important to control the balance between the amount of H2O generated by the dehydration condensation reaction and the amount of H2O absorbed by the oxidation reaction.

[0121] Next, the heat treatment (step S109 ) of the bonding method according to the first embodiment will be described in detail.

[0122] In step S109, before the substrate CW with the bare chip is heat-treated at a certain target temperature, the substrate CW with the bare chip is heat-treated within a first temperature range lower than the target temperature. The lower the temperature, the slower the reaction rate of the dehydration condensation reaction. Therefore, by heat-treating the substrate CW with the bare chip within a first temperature range lower than the target temperature before the substrate CW with the bare chip is heat-treated at the target temperature, the heating rate of the substrate CW with the bare chip is slowed down. Therefore, the amount of H2O generated by the dehydration condensation reaction can be suppressed from exceeding the amount of H2O absorbed by the oxidation reaction. As a result, it is possible to suppress the residual H2O at the bonding interface between the bare chip CP and the substrate W, thereby suppressing the decrease in the bonding strength between the bare chip CP and the substrate W.

[0123] The target temperature is a temperature at which a dehydration condensation reaction occurs and a covalent bond is generated. The target temperature is, for example, 350° C. or higher.

[0124] Performing heat treatment within the first temperature range may include maintaining the atmosphere of the substrate CW provided with the bare chip in a temperature range of 100°C or more and less than 150°C. In the temperature range of 100°C or more and less than 150°C, a dehydration reaction is generated by the evaporation of water. Therefore, by maintaining the atmosphere of the substrate CW provided with the bare chip in a temperature range of 100°C or more and less than 150°C, a dehydration reaction can be generated by the evaporation of water. Thus, H2O can be generated in advance before the atmosphere of the substrate CW provided with the bare chip reaches the target temperature. As a result, it is possible to suppress a sharp increase in the amount of H2O generated when the substrate CW with the bare chip is heat treated at the target temperature, thereby suppressing the amount of H2O generated from exceeding the amount of H2O absorbed. The time for maintaining the atmosphere of the substrate CW provided with the bare chip in a temperature range of 100°C or more and less than 150°C can be longer than the time required for the temperature of the substrate CW with the bare chip to reach 100°C or more and less than 150°C, for example, 5 minutes.

[0125] The heat treatment within the first temperature range may include maintaining the atmosphere of the substrate CW provided with the bare chip in a temperature range of 300°C or more and less than 350°C. In the temperature range of 300°C or more and less than 350°C, a dehydration reaction is generated by the detachment of adsorbed water. Therefore, by maintaining the atmosphere of the substrate CW provided with the bare chip in a temperature range of 300°C or more and less than 350°C, a dehydration reaction can be generated by the detachment of adsorbed water. Thus, H2O can be generated in advance before the atmosphere of the substrate CW provided with the bare chip reaches the target temperature. As a result, it is possible to suppress a sharp increase in the amount of H2O generated when the substrate CW with the bare chip is heat-treated at the target temperature, thereby suppressing the amount of H2O generated from exceeding the amount of H2O absorbed. The time for maintaining the atmosphere of the substrate CW provided with the bare chip in a temperature range of 300°C or more and less than 350°C can be longer than the time required for the temperature of the substrate CW with the bare chip to reach 300°C or more and less than 350°C, for example, 5 minutes.

[0126] Next, an example of a method of heat-treating the substrate CW with a bare chip in the annealing device 43 will be described. The annealing device 43 includes five annealing devices 43a to 43e.

[0127] First, the substrate transfer arm 34 takes out the substrate CW with a bare chip from the bonding device 42 and transfers it to the annealing device 43 a .

[0128] Next, the annealing device 43a performs heat treatment on the substrate CW with bare chips. The set temperature of the annealing device 43a is 50°C. Therefore, the substrate CW with bare chips is heat treated in an atmosphere of 50°C. The time for heat treatment of the substrate CW with bare chips in the annealing device 43a is, for example, 5 minutes. After that, the substrate transfer arm 34 takes out the substrate CW with bare chips from the annealing device 43a and transfers it to the annealing device 43b.

[0129] Next, the annealing device 43b performs heat treatment on the substrate CW with bare chips. The set temperature of the annealing device 43b is 100°C. Therefore, the substrate CW with bare chips is heat treated in an atmosphere of 100°C. The time for heat treatment of the substrate CW with bare chips in the annealing device 43b is, for example, 5 minutes. After that, the substrate transfer arm 34 takes out the substrate CW with bare chips from the annealing device 43b and transfers it to the annealing device 43c.

[0130] Next, the annealing device 43c performs heat treatment on the substrate CW with bare chips. The set temperature of the annealing device 43c is 150°C. Therefore, the substrate CW with bare chips is heat treated in an atmosphere of 150°C. The time for heat treatment of the substrate CW with bare chips in the annealing device 43c is, for example, 5 minutes. After that, the substrate transfer arm 34 takes out the substrate CW with bare chips from the annealing device 43c and transfers it to the annealing device 43d.

[0131] Next, the annealing device 43d performs heat treatment on the substrate CW with bare chips. The set temperature of the annealing device 43d is 200°C. Therefore, the substrate CW with bare chips is heat treated in an atmosphere of 200°C. The time for heat treatment of the substrate CW with bare chips in the annealing device 43d is, for example, 5 minutes. After that, the substrate transfer arm 34 takes out the substrate CW with bare chips from the annealing device 43d and transfers it to the annealing device 43e.

[0132] Next, the annealing device 43e performs heat treatment on the substrate CW with the bare chip. The set temperature of the annealing device 43e is 350°C (target temperature). Therefore, the substrate CW with the bare chip is heat treated in an atmosphere of 350°C. As a result, the bonding strength between the bare chip CP and the substrate W is improved. The time for heat treatment of the substrate CW with the bare chip in the annealing device 43e is, for example, 60 minutes. Thereafter, the substrate conveying arm 34 takes out the substrate CW with the bare chip from the annealing device 43e and conveys it to the conveying device 25. Finally, the substrate conveying arm 24 takes out the substrate CW with the bare chip from the conveying device 25 and stores it in the box C6. The substrate CW with the bare chip is carried out from the bonding system 1 in a state of being stored in the box C6.

[0133] As described above, according to the first embodiment, the substrate CW with bare chips is moved sequentially through the five annealing devices 43a to 43e. Fig.12 As shown, the temperature of the atmosphere in which the substrate CW with the bare chip is provided is increased in a stepwise manner. In this case, when the heat treatment of step S109 is performed, the heating rate of the substrate CW with the bare chip is slowed down. Therefore, it is possible to suppress the amount of H2O generated by the dehydration condensation reaction from exceeding the amount of H2O absorbed by the oxidation reaction. As a result, it is possible to suppress the residual H2O at the bonding interface between the bare chip CP and the substrate W, thereby suppressing the decrease in the bonding strength between the bare chip CP and the substrate W. In addition, the set temperature of each annealing device 43a~43e is not changed in the middle of the heat treatment. Therefore, the time required for the heating and cooling of each annealing device 43a~43e is not required. In addition, the power consumption of each annealing device 43a~43e can be reduced.

[0134] In addition, the amount of H2O generated during heat treatment varies depending on the number of bare chips CP, the size of bare chips CP, the thickness of bare chips CP, the arrangement pitch of bare chips CP, etc. Therefore, it is preferred to determine the temperature rise conditions during heat treatment based on the number of bare chips CP, the size of bare chips CP, the thickness of bare chips CP, the arrangement pitch of bare chips CP, etc. In this case, H2O can be suppressed from remaining at the bonding interface between the bare chip CP and the substrate W, and the heat treatment time can be shortened. The temperature rise conditions include, for example, the time for heat treatment of the substrate CW with the bare chip in each annealing device 43a~43e. The temperature rise conditions may also include the set temperature of each annealing device 43a~43e.

[0135] In the first embodiment, the substrate CW with bare chips is sequentially moved through the five annealing devices 43a to 43e, but the present invention is not limited thereto. For example, the temperature of the atmosphere in which the substrate CW with bare chips is placed may be increased stepwise by changing the set temperature of one annealing device 43.

[0136] In the first embodiment, the case where the temperature of the atmosphere of the substrate CW with the bare chip is increased stepwise is described, but the present invention is not limited to this. Fig.13 As shown, the temperature of the atmosphere in which the substrate CW with the bare chip is placed can also be continuously increased from room temperature to the target temperature. In this case, it is preferred to increase the set temperature from room temperature to 350°C (target temperature) at a heating rate of 10°C / min or less. In this way, regardless of the type of the film to be bonded, the amount of H2O generated can be suppressed from exceeding the amount of H2O absorbed, thereby easily suppressing H2O from remaining at the bonding interface between the bare chip CP and the substrate W.

[0137] In addition, in the first embodiment, the case where the joining system 1 includes the annealing device 43 is described, but the present invention is not limited to this. For example, the annealing device may be provided separately from the joining system 1.

[0138] [Second embodiment]

[0139] (system)

[0140] Reference Figures 14 to 20 A system according to the second embodiment will be described. The system includes a bonding system BN1 and an annealing system AN1.

[0141] The bonding system BN1 bonds the first semiconductor substrate and the second semiconductor substrate to produce a superimposed substrate. Fig.15As shown, the substrate arranged on the lower side during bonding is called the lower wafer W1, and the substrate arranged on the upper side during bonding is called the upper wafer W2. The lower wafer W1 is equivalent to the first semiconductor substrate, and the upper wafer W2 is equivalent to the second semiconductor substrate, but the combination can also be reversed, and the lower wafer W1 can be equivalent to the second semiconductor substrate, and the upper wafer W2 can be equivalent to the first semiconductor substrate.

[0142] By bonding the lower wafer W1 and the upper wafer W2, an overlapped wafer T can be obtained. The plate surface of the lower wafer W1 on the side bonded to the upper wafer W2 is recorded as "bonding surface W1j", and the plate surface on the side opposite to the bonding surface W1j is recorded as "non-bonding surface W1n". The plate surface of the upper wafer W2 on the side bonded to the lower wafer W1 is recorded as "bonding surface W2j", and the plate surface on the side opposite to the bonding surface W2j is recorded as "non-bonding surface W2n".

[0143] The lower wafer W1 has a semiconductor substrate such as a silicon wafer, and a film formed on the semiconductor substrate. A glass substrate may also be used instead of the semiconductor substrate. The film, for example, has a device layer and a bonding layer. The device layer includes a plurality of electronic circuits. The bonding layer is formed on the device layer. The bonding layer is, for example, a silicon oxide film, a silicon nitride film, or a silicon carbonitride film.

[0144] The upper wafer W2 has a semiconductor substrate such as a silicon wafer, and a film formed on the semiconductor substrate. A glass substrate can also be used instead of the semiconductor substrate. The film, for example, has a device layer and a bonding layer. The device layer includes a plurality of electronic circuits. The bonding layer is formed on the device layer. The bonding layer is, for example, a silicon oxide film, a silicon nitride film, or a silicon carbonitride film.

[0145] In addition, one of the lower wafer W1 and the upper wafer W2 may not have a device layer.

[0146] like Fig.14 As shown, the bonding system BN1 includes a loading and unloading station BN2 and a processing station BN3. The loading and unloading station BN2 and the processing station BN3 are arranged in the order of loading and unloading station BN2 and processing station BN3 along the positive direction of the X axis. The loading and unloading station BN2 and the processing station BN3 are connected as a whole.

[0147] The loading and unloading station BN2 is provided with a loading platform BN10 and a conveying area BN20. The loading platform BN10 is provided with a plurality of loading plates BN11. Boxes C21, C22, and C23 for holding a plurality of (for example, 25) substrates are respectively placed on each loading plate BN11. Box C21 is a box for accommodating the lower wafer W1, box C22 is a box for accommodating the upper wafer W2, and box C23 is a box for accommodating the overlapping wafers T accommodated in a horizontal state. In addition, the lower wafer W1 and the upper wafer W2 are respectively accommodated in the boxes C21 and C22 in a manner in which the orientation is consistent with the bonding surfaces W1j and W2j being set as the upper surfaces.

[0148] The transport area BN20 is arranged adjacent to the positive direction side of the X-axis of the mounting table BN10. A transport path BN21 extending along the Y-axis direction and a transport device BN22 capable of moving along the transport path BN21 are provided in the transport area BN20. The transport device BN22 has a transport arm for holding and transporting the lower wafer W1, the upper wafer W2 or the overlapping wafer T. The transport arm can move in the horizontal direction and the vertical direction, and can rotate around the vertical axis. The number of transport arms can also be multiple. The transport arm transports the upper wafer W2, the lower wafer W1 or the overlapping wafer T to a specified device adjacent to the transport area BN20.

[0149] The number of cassettes C21 to C23 placed on the mounting table BN10 is not limited to the number shown in the figure. In addition to the cassettes C21, C22, and C23, a cassette for collecting defective substrates may be placed on the mounting table BN10.

[0150] The processing station BN3 is provided with, for example, three processing blocks G11, G12, and G13. Fig.14 A first processing block G11 is provided on the positive Y-axis side of the processing station BN3. Fig.14 A second processing block G12 is provided on the negative Y-axis side of the processing station BN3. Fig.14 A third processing block G13 is provided on the negative X-axis direction side.

[0151] A transfer area BN60 is formed in an area surrounded by the first processing block G11 to the third processing block G13. A transfer device BN61 is arranged in the transfer area BN60. The transfer device BN61 has a transfer arm for holding and transferring the lower wafer W1, the upper wafer W2 or the overlapping wafer T. The transfer arm can move in the horizontal direction and the vertical direction, and can rotate around the vertical axis. The number of transfer arms can also be multiple. The transfer arm transfers the lower wafer W1, the upper wafer W2 or the overlapping wafer T to a specified device adjacent to the transfer area BN60.

[0152] In the first processing block G11, for example, an activation device BN33 and a hydrophilization device BN34 are configured. The activation device BN33 uses plasma to modify the bonding surface W1j of the lower wafer W1 or the bonding surface W2j of the upper wafer W2. The hydrophilization device BN34 hydrophilizes the modified bonding surface W1j of the lower wafer W1 or the modified bonding surface W2j of the upper wafer W2. The positions of the activation device BN33 and the hydrophilization device BN34 are not limited to the positions shown in the figure. The number of the activation device BN33 and the hydrophilization device BN34 can be multiple.

[0153] The activation device BN33, for example, cuts the bonds of SiO2 in the bonding surfaces W1j and W2j to form dangling bonds of Si, so that subsequent hydrophilization can be performed. In the activation device BN33, for example, oxygen gas as a processing gas is excited to plasma under a reduced pressure atmosphere, thereby ionizing it. In addition, by irradiating the bonding surfaces W1j and W2j with oxygen ions, the bonding surfaces W1j and W2j are subjected to plasma treatment to modify them. The processing gas is not limited to oxygen gas, and may be nitrogen gas, for example.

[0154] The hydrophilization device BN34, for example, provides OH groups to the bonding surfaces W1j and W2j. The hydrophilization device BN34, for example, rotates the lower wafer W1 or the upper wafer W2 held on the rotating holding plate while supplying pure water to the lower wafer W1 or the upper wafer W2. The pure water diffuses on the bonding surfaces W1j and W2j, provides OH groups to the dangling bonds of Si, and hydrophilizes the bonding surfaces W1j and W2j. The hydrophilization device BN34 also has the function of cleaning the bonding surfaces W1j and W2j.

[0155] In the second processing block G12, for example, a bonding device BN41 is configured. The bonding device BN41 turns the upper wafer W2 upside down so that the bonding surface W2j of the upper wafer W2 faces downward. After that, the bonding device BN41 bonds the hydrophilized lower wafer W1 to the upper wafer W2 to produce a superimposed wafer T. In this embodiment, the device for turning the upper wafer W2 upside down is provided as a part of the bonding device BN41, but may also be provided separately from the bonding device BN41.

[0156] The third processing block G13 is provided with, for example, a conveyor device BN51 . The conveyor device BN51 temporarily stores the lower wafer W1 , the upper wafer W2 , or the overlapped wafer T. The number of the conveyor devices BN51 may be plural.

[0157] The joining system BN1 includes a control device BN90. The control device BN90 is, for example, a computer, and includes a computing unit BN91 such as a CPU, and a storage unit BN92 such as a memory. The storage unit BN92 stores a program for controlling various processes performed in the joining system BN1. The control device BN90 controls the operation of the joining system BN1 by causing the computing unit BN91 to execute the program stored in the storage unit BN92.

[0158] The annealing system AN1 includes a loading and unloading station AN2 and a processing station AN3. The loading and unloading station AN2 and the processing station AN3 are arranged in the order of loading and unloading station AN2 and processing station AN3 along the positive direction of the X axis. The loading and unloading station AN2 and the processing station AN3 are connected as one body.

[0159] The loading / unloading station AN2 includes a mounting table AN10 and a transfer area AN20. The mounting table AN10 includes a plurality of mounting plates AN11. A cassette C23 for storing a plurality of (eg, 25) substrates in a horizontal state is placed on each mounting plate AN11. The cassette C23 is a cassette for storing the stacked wafers T.

[0160] The conveying area AN20 is arranged adjacent to the positive direction side of the X-axis of the mounting table AN10. A conveying path AN21 extending along the Y-axis direction and a conveying device AN22 capable of moving along the conveying path AN21 are provided in the conveying area AN20. The conveying device AN22 has a conveying arm for holding and conveying overlapping wafers T. The conveying arm can move in the horizontal direction and the vertical direction, and can rotate around the vertical axis. The number of conveying arms can also be multiple. The conveying arm conveys the overlapping wafers T to a specified device adjacent to the conveying area AN20.

[0161] The number of cassettes C23 placed on the mounting table AN10 is not limited to the number shown in the figure. In addition to the cassettes C23, a cassette for collecting defective substrates may be placed on the mounting table AN10.

[0162] The processing station AN3 is provided with, for example, three processing blocks G21, G22, and G23. Fig.14 A first processing block G21 is provided on the positive Y-axis side of the processing station AN3. Fig.14 A second processing block G22 is provided on the negative side of the Y axis. Fig.14 A third processing block G23 is provided on the negative X-axis direction side.

[0163] A transfer area AN60 is formed in an area surrounded by the first processing block G21 to the third processing block G23. A transfer device AN61 is arranged in the transfer area AN60. The transfer device AN61 has a transfer arm for holding and transferring the overlapped wafer T. The transfer arm can move in the horizontal direction and the vertical direction, and can rotate around the vertical axis. The number of transfer arms can also be multiple. The transfer arm transfers the overlapped wafer T to a specified device adjacent to the transfer area AN60.

[0164] In the first processing block G21, for example, an annealing device AN43 and an annealing device AN44 are configured. The annealing device AN43 performs heat treatment on the overlapping wafer T. Before the heat treatment, the lower wafer W1 and the upper wafer W2 are bonded by hydrogen bonds between OH groups. Through the heat treatment, a dehydration condensation reaction occurs, and a covalent bond is generated, and the bonding strength between the lower wafer W1 and the upper wafer W2 is improved. For example, a plurality of annealing devices AN43 are stacked in the Z-axis direction. The plurality of annealing devices AN43 is configured to perform heat treatment on the overlapping wafer T at different set temperatures. The plurality of annealing devices AN43 includes an annealing device whose set temperature is a target temperature, and an annealing device whose set temperature is a first temperature range lower than the target temperature. The target temperature is a temperature at which a dehydration condensation reaction will occur and a covalent bond will be generated. The target temperature is, for example, above 350°C. In the present embodiment, the plurality of annealing devices AN43 includes five annealing devices AN43a to AN43e. The set temperatures of annealing devices AN43a, AN43b, AN43c, AN43d, and AN43e are 50°C, 100°C, 150°C, 200°C, and 350°C (target temperatures), respectively. The number of annealing devices AN43 is not limited to the number shown in the figure. Annealing device AN44 can be the same structure as annealing device AN43. Annealing device AN44 includes five annealing devices AN44a to AN44e. In the case of having annealing device AN44, multiple overlapping wafers T can be heat treated simultaneously. Annealing device AN44 may also be absent.

[0165] In the second processing block G22, for example, an annealing device AN45 and an annealing device AN46 are configured. The annealing device AN45 and the annealing device AN46 can each have the same structure as the annealing device AN43. The annealing device AN45 includes five annealing devices AN45a to AN45e. The annealing device AN46 includes five annealing devices AN46a to AN46e. In the case of having the annealing device AN45 and the annealing device AN46, a plurality of overlapping wafers T can be heat-treated simultaneously. The annealing device AN45 and the annealing device AN46 may not be provided.

[0166] In the third processing block G23, for example, a conveyor AN51 is disposed. The conveyor AN51 temporarily stores the overlapped wafer T. The number of conveyors AN51 may be plural.

[0167] The annealing system AN1 includes a control device AN90. The control device AN90 is, for example, a computer, and includes a computing unit AN91 such as a CPU and a storage unit AN92 such as a memory. The storage unit AN92 stores programs for controlling various processes performed in the annealing system AN1. The control device AN90 controls the operation of the annealing system AN1 by causing the computing unit AN91 to execute the program stored in the storage unit AN92.

[0168] (Joining method)

[0169] Reference Fig.16 The joining method according to the second embodiment is described below. Fig.16 processing.

[0170] First, the cassette C21 containing a plurality of lower wafers W1 , the cassette C22 containing a plurality of upper wafers W2 , and an empty cassette C23 are placed on the mounting table BN10 of the carry-in / carry-out station BN2 .

[0171] Next, the transfer device BN22 takes out the lower wafer W1 in the cassette C21 and transfers it to the transfer device BN51. Thereafter, the transfer device BN61 takes out the lower wafer W1 from the transfer device BN51 and transfers it to the activation device BN33.

[0172] Next, the activation device BN33 modifies the bonding surface W1j of the lower wafer W1 (step S201). The bonding surface W1j is modified with the bonding surface W1j facing upward. Thereafter, the transfer device BN61 takes the lower wafer W1 out of the activation device BN33 and transfers it to the hydrophilization device BN34.

[0173] Next, the hydrophilizing device BN34 hydrophilizes the bonding surface W1j of the lower wafer W1 (step S202). The bonding surface W1j is hydrophilized with the bonding surface W1j facing upward. Thereafter, the transport device BN61 takes the lower wafer W1 out of the hydrophilizing device BN34 and transports it to the bonding device BN41.

[0174] While the above-mentioned processing is being performed on the lower wafer W1, the following processing is performed on the upper wafer W2 in parallel. First, the transfer device BN22 takes out the upper wafer W2 in the cassette C22 and transfers it to the conveyor BN51. Then, the transfer device BN61 takes out the upper wafer W2 from the conveyor BN51 and transfers it to the activation device BN33.

[0175] Next, the activation device BN33 modifies the bonding surface W2j of the upper wafer W2 (step S203). The bonding surface W2j is modified with the bonding surface W2j facing upward. Thereafter, the transport device BN61 takes out the upper wafer W2 from the activation device BN33 and transports it to the hydrophilization device BN34.

[0176] Next, the hydrophilizing device BN34 hydrophilizes the bonding surface W2j of the upper wafer W2 (step S204). The bonding surface W2j is hydrophilized with the bonding surface W2j facing upward. After that, the transport device BN61 takes out the upper wafer W2 from the hydrophilizing device BN34 and transports it to the bonding device BN41.

[0177] Next, the bonding device BN41 turns the upper wafer W2 upside down so that the bonding surface W2j of the upper wafer W2 faces downward. Then, the bonding device BN41 bonds the lower wafer W1 to the upper wafer W2 to produce the overlapping wafer T (step S205). Then, the transport device BN61 takes out the overlapping wafer T from the bonding device BN41 and transports it to the conveying device BN51.

[0178] Next, the transfer device BN22 takes out the overlapped wafer T from the conveyor device BN51 and transfers it to the cassette C23 on the mounting table BN10. Next, the transfer device (not shown) transfers the cassette C23 on the mounting table BN10 to the mounting table AN10 of the annealing system AN1.

[0179] Next, the transfer apparatus AN22 takes out the overlapped wafer T in the cassette C23 and transfers it to the conveying apparatus AN51. Thereafter, the transfer apparatus AN61 takes out the overlapped wafer T from the conveying apparatus AN51 and transfers it to the annealing apparatus AN43.

[0180] Next, the annealing device AN43 performs heat treatment on the overlapped wafer T (step S206). As a result, the bonding strength between the lower wafer W1 and the upper wafer W2 is improved. The details of the heat treatment will be described later. Afterwards, the transport device AN61 takes out the overlapped wafer T from the annealing device AN43 and transports it to the transfer device AN51.

[0181] Next, the transfer apparatus AN22 takes out the overlapped wafer T from the conveyor apparatus AN51 and transfers it to the cassette C23 on the mounting table AN10 . Thus, a series of processes are completed.

[0182] (Joining device)

[0183] Reference Fig.17 An example of the bonding apparatus BN41 will be described. The bonding apparatus BN41 includes a lower holding unit 110 , an upper holding unit 120 , a lower imaging unit 130 , an upper imaging unit 150 , a moving unit 170 , and a control unit 200 .

[0184] The lower holding part 110 holds the lower wafer W1 from below with its bonding surface W1j facing upward, and the upper holding part 120 holds the upper wafer W2 from above with its bonding surface W2j facing downward.

[0185] The lower imaging unit 130 is provided at the lower holding unit 110 to image the upper wafer W2 held at the upper holding unit 120 . The upper imaging unit 150 is provided at the upper holding unit 120 to image the lower wafer W1 held at the lower holding unit 110 .

[0186] The moving part 170 moves the lower holding part 110 and the upper holding part 120 relatively in the horizontal direction and the vertical direction. In the present embodiment, the moving part 170 moves the lower holding part 110, but it may also move the upper holding part 120. The moving part 170 may also rotate the lower holding part 110 or the upper holding part 120 around the vertical axis.

[0187] The control unit 200 controls the operation of the bonding device BN41. The control unit 200 is, for example, a computer and has the same configuration as the control device BN90. The control unit 200 may be a part of the control device BN90.

[0188] The lower holding portion 110 is divided into a plurality of (for example, two) regions 110a and 110b. These regions 110a and 110b are arranged in the order of regions 110a and 110b from the center portion toward the peripheral portion of the lower holding portion 110. Moreover, the region 110a has a circular shape when viewed from above, and the region 110b has an annular shape when viewed from above.

[0189] Suction pipes 111a and 111b are independently provided in the regions 110a and 110b. Different vacuum pumps 112a and 112b are connected to the suction pipes 111a and 111b. The lower holding unit 110 can vacuum-absorb the lower wafer W1 in each of the regions 110a and 110b.

[0190] The lower holding portion 110 is provided with a plurality of holding pins 115 that can be raised and lowered in the vertical direction. The lower wafer W1 is placed on the upper ends of the plurality of holding pins 115. The lower wafer W1 may be vacuum-adsorbed on the upper ends of the plurality of holding pins 115.

[0191] The plurality of holding pins 115 protrude from the holding surface of the lower holding portion 110 by rising. In this state, the plurality of holding pins 115 receive the lower wafer W1 from the transfer device BN61. Thereafter, the plurality of holding pins 115 descend so that the lower wafer W1 contacts the holding surface of the lower holding portion 110. Next, the vacuum pumps 112a and 112b operate, and the lower holding portion 110 vacuum-absorbs the lower wafer W1 horizontally in each region 110a and 110b.

[0192] The upper holding portion 120 is divided into a plurality of (for example, three) regions 120a, 120b, and 120c. These regions 120a, 120b, and 120c are arranged in the order of regions 120a, 120b, and 120c from the center portion toward the periphery portion of the upper holding portion 120. The region 120a has a circular shape when viewed from above, and the regions 120b and 120c have an annular shape when viewed from above.

[0193] Suction pipes 121a, 121b, 121c are independently provided in each region 120a, 120b, 120c. Different vacuum pumps 122a, 122b, 122c are connected to each suction pipe 121a, 121b, 121c. The upper holding unit 120 can vacuum absorb the upper wafer W2 in each region 120a, 120b, 120c.

[0194] The upper holding portion 120 is provided with a plurality of holding pins 125 that can be lifted and lowered in the vertical direction. The plurality of holding pins 125 are connected to a vacuum pump 126, and the upper wafer W2 is vacuum-adsorbed by the operation of the vacuum pump 126. The upper wafer W2 is vacuum-adsorbed to the lower ends of the plurality of holding pins 125. An annular adsorption disk may also be used instead of the plurality of holding pins 125.

[0195] The plurality of holding pins 125 protrude from the holding surface of the upper holding part 120 by descending. In this state, the plurality of holding pins 125 vacuum adsorb the upper wafer W2 and receive the upper wafer W2 from the transfer device BN61. Thereafter, the plurality of holding pins 125 rise so that the upper wafer W2 contacts the holding surface of the upper holding part 120. Next, by operating the vacuum pumps 122a, 122b, and 122c, the upper holding part 120 vacuum adsorbs the upper wafer W2 horizontally in each area 120a, 120b, and 120c.

[0196] A through hole 123 is formed at the center of the upper holding part 120 so as to vertically penetrate the upper holding part 120. A pusher 190 described later passes through the through hole 123. The pusher 190 pushes the center of the upper wafer W2 spaced apart from the lower wafer W1 to make it contact with the lower wafer W1.

[0197] The pushing portion 190 includes a pushing pin 191 and an outer cylinder 192 serving as a lifting guide for the pushing pin 191. The pushing pin 191 passes through the through hole 123 via a driving portion (not shown) having a built-in motor, and protrudes from the holding surface of the upper holding portion 120 to push the center of the upper wafer W2.

[0198] Next, refer to Figures 18 to 20 An example of the operation of the bonding device BN41 is described below. First, the transport device BN61 carries in the lower wafer W1 and the upper wafer W2 relative to the bonding device BN41. The lower holding portion 110 holds the lower wafer W1 from below in a manner such that the bonding surface W1j of the lower wafer W1 faces upward. The upper holding portion 120 holds the upper wafer W2 from above in a manner such that the bonding surface W2j of the upper wafer W2 faces downward.

[0199] Next, the moving part 170 moves the lower holding part 110 and the upper holding part 120 relatively to align the positions of the lower wafer W1 and the upper wafer W2. Fig.17As shown, in the position alignment, the lower camera unit 130 and the upper camera unit 150 are used. The upper camera unit 150 is fixed to the upper holding unit 120 and is used to photograph the bonding surface W1j of the lower wafer W1 held by the lower holding unit 110. On the other hand, the lower camera unit 130 is fixed to the lower holding unit 110 and is used to photograph the bonding surface W2j of the upper wafer W2 held by the upper holding unit 120.

[0200] Then, if Fig.18 As shown, the vacuum pump 122a is stopped to release the vacuum adsorption of the upper wafer W2 in the area 120a. Then, the push pin 191 of the pusher 190 is lowered to push the center of the upper wafer W2 to make it contact with the lower wafer W1. As a result, the centers of the lower wafer W1 and the upper wafer W2 are bonded to each other.

[0201] Since the bonding surface W1j of the lower wafer W1 and the bonding surface W2j of the upper wafer W2 have been modified, van der Waals force (intermolecular force) is generated between the bonding surfaces W1j and W2j, and the bonding surfaces W1j and W2j are bonded to each other. In addition, since the bonding surfaces W1j and W2j have been hydrophilized, the hydrophilic groups (such as OH groups) are hydrogen bonded, and the bonding surfaces W1j and W2j are firmly bonded to each other.

[0202] Then, if Fig.19 As shown in FIG. 1 , the vacuum pump 122b is stopped to release the vacuum adsorption of the upper wafer W2 in the region 120b. Next, the vacuum pump 122c is stopped. Fig. 20 As shown, the vacuum suction on the upper wafer W2 in the region 120c is released.

[0203] In this way, the vacuum adsorption of the upper wafer W2 is released in stages from the center to the periphery of the upper wafer W2, and the upper wafer W2 falls in stages and abuts against the lower wafer W1. Moreover, the bonding of the lower wafer W1 and the upper wafer W2 progresses sequentially from the center to the periphery. As a result, the bonding surface W2j of the upper wafer W2 abuts against the bonding surface W1j of the lower wafer W1 with the entire surface, and the lower wafer W1 is bonded to the upper wafer W2 to obtain a superimposed wafer T. Afterwards, the push pin 191 rises to its original position.

[0204] Next, the moving part 170 lowers the lower holding part 110 to expand the interval between the lower holding part 110 and the upper holding part 120 in the vertical direction. After that, the conveying device BN61 carries out the overlapped wafer T with respect to the bonding device BN41. Specifically, first, the lower holding part 110 releases the holding of the overlapped wafer T. Next, the plurality of holding pins 115 rise to transfer the overlapped wafer T to the conveying device BN61. After that, the plurality of holding pins 115 descend to their original positions.

[0205] (Heat Treatment)

[0206] Details of the heat treatment (step S206 ) in the bonding method according to the second embodiment will be described.

[0207] In step S206, before the overlapped wafer T is heat-treated at a certain target temperature, the overlapped wafer T is heat-treated within a first temperature range lower than the target temperature. The lower the temperature, the slower the reaction rate of the dehydration condensation reaction. Therefore, by heat-treating the overlapped wafer T within a first temperature range lower than the target temperature before the overlapped wafer T is heat-treated at the target temperature, the heating rate of the overlapped wafer T is slowed down. Therefore, it is possible to suppress the amount of H2O generated by the dehydration condensation reaction from exceeding the amount of H2O absorbed by the oxidation reaction. As a result, it is possible to suppress the residual H2O at the bonding interface between the lower wafer W1 and the upper wafer W2, thereby suppressing the decrease in the bonding strength between the lower wafer W1 and the upper wafer W2.

[0208] The target temperature is a temperature at which a dehydration condensation reaction occurs and a covalent bond is generated. The target temperature is, for example, 350° C. or higher.

[0209] Performing heat treatment within the first temperature range may include maintaining the atmosphere in which the overlapping wafer T is provided in a temperature range of 100°C or more and less than 150°C. In the temperature range of 100°C or more and less than 150°C, a dehydration reaction is generated by the evaporation of water. Therefore, by maintaining the atmosphere in which the overlapping wafer T is provided in a temperature range of 100°C or more and less than 150°C, a dehydration reaction can be generated by the evaporation of water. Thus, H2O can be generated in advance before the atmosphere in which the overlapping wafer T is provided reaches the target temperature. As a result, it is possible to suppress a sharp increase in the amount of H2O generated when the overlapping wafer T is heat treated at the target temperature, thereby suppressing the amount of H2O generated from exceeding the amount of H2O absorbed. The time for maintaining the atmosphere in which the overlapping wafer T is provided in a temperature range of 100°C or more and less than 150°C can be longer than the time required for the temperature of the overlapping wafer T to reach 100°C or more and less than 150°C, for example, 5 minutes.

[0210] Performing heat treatment within the first temperature range may include maintaining the atmosphere in which the overlapping wafer T is provided in a temperature range of 300°C or more and less than 350°C. In the temperature range of 300°C or more and less than 350°C, a dehydration reaction is generated by the detachment of adsorbed water. Therefore, by maintaining the atmosphere in which the overlapping wafer T is provided in a temperature range of 300°C or more and less than 350°C, a dehydration reaction can be generated by the detachment of adsorbed water. Thus, H2O can be pre-generated before the atmosphere in which the overlapping wafer T is provided reaches the target temperature. As a result, it is possible to suppress a sharp increase in the amount of H2O generated when the overlapping wafer T is heat treated at the target temperature, thereby suppressing the amount of H2O generated from exceeding the amount of H2O absorbed. The time for maintaining the atmosphere in which the overlapping wafer T is provided in a temperature range of 300°C or more and less than 350°C can be longer than the time required for the temperature of the overlapping wafer T to reach 300°C or more and less than 350°C, for example, 5 minutes.

[0211] Next, an example of a method of heat-treating the overlapped wafer T in the annealing apparatus AN43 will be described. The annealing apparatus AN43 includes five annealing apparatuses AN43a to AN43e.

[0212] First, the annealing device AN43a performs heat treatment on the overlapped wafer T. The set temperature of the annealing device AN43a is 50°C. Therefore, the overlapped wafer T is heat treated in an atmosphere of 50°C. The time for heat treatment of the overlapped wafer T in the annealing device AN43a is, for example, 5 minutes. Thereafter, the transport device AN61 takes out the overlapped wafer T from the annealing device AN43a and transports it to the annealing device AN43b.

[0213] Next, the annealing device AN43b performs heat treatment on the overlapped wafer T. The set temperature of the annealing device AN43b is 100°C. Therefore, the overlapped wafer T is heat treated in an atmosphere of 100°C. The time for heat treatment of the overlapped wafer T in the annealing device AN43b is, for example, 5 minutes. Thereafter, the transport device AN61 takes out the overlapped wafer T from the annealing device AN43b and transports it to the annealing device AN43c.

[0214] Next, the annealing device AN43c performs heat treatment on the overlapped wafer T. The set temperature of the annealing device AN43c is 150°C. Therefore, the overlapped wafer T is heat treated in an atmosphere of 150°C. The time for heat treatment of the overlapped wafer T in the annealing device AN43c is, for example, 5 minutes. Thereafter, the transport device AN61 takes out the overlapped wafer T from the annealing device AN43c and transports it to the annealing device AN43d.

[0215] Next, the annealing device AN43d performs heat treatment on the overlapped wafer T. The set temperature of the annealing device AN43d is 200°C. Therefore, the overlapped wafer T is heat treated in an atmosphere of 200°C. The time for heat treatment of the overlapped wafer T in the annealing device AN43d is, for example, 5 minutes. Thereafter, the transport device AN61 takes out the overlapped wafer T from the annealing device AN43d and transports it to the annealing device AN43e.

[0216] Next, the annealing device AN43e performs heat treatment on the overlapped wafer T. The set temperature of the annealing device AN43e is 350°C (target temperature). Therefore, the overlapped wafer T is heat treated in an atmosphere of 350°C. As a result, the bonding strength between the lower wafer W1 and the upper wafer W2 is improved. The time for heat treatment of the overlapped wafer T in the annealing device AN43e is, for example, 60 minutes. Thereafter, the conveying device AN61 takes out the overlapped wafer T from the annealing device AN43e and conveys it to the conveying device AN51. Finally, the conveying device AN22 takes out the overlapped wafer T from the conveying device AN51 and stores it in the box C23. The overlapped wafer T is carried out from the annealing system AN1 in a state of being stored in the box C23.

[0217] As described above, according to the second embodiment, the overlapped wafer T is sequentially moved in the five annealing apparatuses AN43a to AN43e. Fig.12 As shown, the temperature of the atmosphere in which the overlapping wafer T is provided is increased in a stepwise manner. In this case, when the heat treatment of step S206 is performed, the heating rate of the overlapping wafer T is slowed down. Therefore, it is possible to suppress the amount of H2O generated by the dehydration condensation reaction from exceeding the amount of H2O absorbed by the oxidation reaction. As a result, it is possible to suppress the residual H2O at the bonding interface between the lower wafer W1 and the upper wafer W2, thereby suppressing the decrease in the bonding strength between the lower wafer W1 and the upper wafer W2. In addition, the set temperature of each annealing device AN43a~AN43e is not changed in the middle of the heat treatment. Therefore, the time required for the heating and cooling of each annealing device AN43a~AN43e is not required. In addition, the power consumption of each annealing device AN43a~AN43e can be reduced.

[0218] In addition, the amount of H2O generated during heat treatment varies depending on the type of film to be bonded, the activation conditions of the bonding surfaces W1j and W2j, the hydrophilic conditions of the bonding surfaces W1j and W2j, the waiting time from the time point when the bonding of step S205 is completed to the time point when the heat treatment of step S206 is started, etc. Therefore, it is preferred to determine the temperature rise conditions during heat treatment according to the type of film to be bonded, the activation conditions of the bonding surfaces W1j and W2j, the hydrophilic conditions of the bonding surfaces W1j and W2j, the waiting time, etc. In this case, H2O can be suppressed from remaining at the bonding interface between the lower wafer W1 and the upper wafer W2, and the time required for heat treatment can be shortened. The temperature rise conditions include, for example, the time for heat treatment of the overlapping wafer T in each annealing device AN43a~AN43e. The temperature rise conditions may also include the set temperature of each annealing device AN43a~AN43e.

[0219] In the second embodiment, the overlapped wafer T is sequentially moved through the five annealing apparatuses AN43a to AN43e, but the present invention is not limited thereto. For example, the temperature of the atmosphere in which the overlapped wafer T is placed may be increased stepwise by changing the set temperature of one annealing apparatus AN43.

[0220] In the second embodiment, the case where the temperature of the atmosphere in which the wafers T are stacked is increased in a stepwise manner is described, but the present invention is not limited thereto. Fig.13 As shown, the temperature of the atmosphere in which the overlapping wafers T are placed can also be continuously increased from room temperature to the target temperature. In this case, it is preferred to raise the set temperature from room temperature to the target temperature at a heating rate of less than 10°C / min. Thus, regardless of whether the types of the films to be bonded are different, the amount of H2O generated can be suppressed from exceeding the amount of H2O absorbed, thereby easily suppressing H2O from remaining at the bonding interface between the lower wafer W1 and the upper wafer W2.

[0221] In the second embodiment, the annealing system AN1 is provided separately from the bonding system BN1, but the present invention is not limited thereto. For example, the bonding system BN1 may include an annealing apparatus AN43.

[0222] The embodiments disclosed herein are to be considered in all respects as illustrative and non-restrictive. The embodiments described above may be omitted, replaced, or modified in various ways without departing from the appended claims and the gist thereof.

[0223] Description of Reference Numerals

[0224] CP: bare chip; W: substrate; CW: substrate with bare chip; W1: lower wafer; W2: upper wafer; T: overlapped wafer.

Claims

1. A joining method, comprising: preparing a first semiconductor substrate having a first surface and a second semiconductor substrate having a second surface; making the first surface of the first semiconductor substrate and the second surface of the second semiconductor substrate hydrophilic; After the hydrophilization, bonding the first surface of the first semiconductor substrate to the second surface of the second semiconductor substrate; as well as After the bonding, the first semiconductor substrate and the second semiconductor substrate are subjected to heat treatment to improve the bonding strength between the first semiconductor substrate and the second semiconductor substrate. Wherein, improving the bonding strength comprises: thermally treating the first semiconductor substrate and the second semiconductor substrate within a first temperature range; and After the heat treatment is performed within the first temperature range, the first semiconductor substrate and the second semiconductor substrate are heat treated at a target temperature. The first temperature range is a temperature range lower than the target temperature.

2. The bonding method according to claim 1, wherein: The target temperature is 350° C. or higher.

3. The bonding method according to claim 1, wherein: The heat treatment within the first temperature range includes stepwise increasing the temperature of an atmosphere in which the first semiconductor substrate and the second semiconductor substrate are disposed.

4. The bonding method according to claim 3, wherein: The heat treatment within the first temperature range includes maintaining the temperature of the atmosphere within a temperature range of 100° C. or more and less than 150° C. or less.

5. The bonding method according to claim 3, wherein: The heat treatment within the first temperature range includes maintaining the temperature of the atmosphere in a temperature range of 300° C. or more and less than 350° C. or less.

6. The bonding method according to claim 3, wherein: The heat treatment within the first temperature range includes: sequentially moving the first semiconductor substrate and the second semiconductor substrate in a plurality of annealing devices having different set temperatures.

7. The bonding method according to claim 1, wherein: Performing the heat treatment within the first temperature range includes continuously increasing the temperature of an atmosphere in which the first semiconductor substrate and the second semiconductor substrate are disposed.

8. The bonding method according to claim 7, wherein: The heat treatment within the first temperature range includes: placing the first semiconductor substrate and the second semiconductor substrate in an annealing device, and raising the set temperature of the annealing device to the target temperature at a heating rate of 10° C. / min or less.

9. The joining method according to any one of claims 1 to 8, wherein: The first semiconductor substrate is a semiconductor wafer. The second semiconductor substrate is a semiconductor wafer.

10. The bonding method according to any one of claims 1 to 8, wherein: The first semiconductor substrate is a semiconductor wafer. The second semiconductor substrate is a bare chip.

11. A joining system comprising: A first hydrophilizing device for hydrophilizing a first surface of a first semiconductor substrate; a second hydrophilizing device for hydrophilizing the second surface of the second semiconductor substrate; a bonding device for bonding the first surface of the first semiconductor substrate to the second surface of the second semiconductor substrate; as well as an annealing device for improving the bonding strength between the first semiconductor substrate and the second semiconductor substrate by performing a heat treatment on the first semiconductor substrate and the second semiconductor substrate, Wherein, the annealing device is configured to perform the following processing: thermally treating the first semiconductor substrate and the second semiconductor substrate within a first temperature range; and After the heat treatment is performed within the first temperature range, the first semiconductor substrate and the second semiconductor substrate are heat treated at a target temperature. The first temperature range is a temperature range lower than the target temperature.

12. The joining system of claim 11, wherein: The annealing device comprises: a first annealing device that performs heat treatment within the first temperature range; and A second annealing apparatus, which is provided separately from the first annealing apparatus, performs heat treatment at the target temperature.

13. The joining system of claim 12, wherein: The device further includes a substrate transfer arm configured to transfer the first semiconductor substrate and the second semiconductor substrate between the first annealing apparatus and the second annealing apparatus.

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