Self-adaption method and device of clock and data recovery circuit

Abstract

The invention discloses a self-adaption method and device for a clock and data recovery circuit, and relates to the technical field of communication, and the method comprises the following steps: judging the phase deviation and frequency deviation between a sending clock and a receiving clock, transmitting a phase error signal to a loop filter, and analyzing the frequency response of the loop filter; the method comprises the following steps: determining a parameter adjustment range and a relative relation, calculating statistical characteristics output by a loop filter in real time, judging the working state of a clock and data recovery circuit, realizing a clock and data recovery circuit state machine, and determining the state of the clock and data recovery circuit according to the statistical characteristics output by the loop filter and based on a threshold detection principle. And determining parameters and an output range for adjusting the loop filter. The working state of the clock and data recovery circuit is monitored, the design parameters of the loop filter are adjusted in real time according to the state change, the frequency capture range is guaranteed, meanwhile, the phase noise of the clock and data recovery circuit in the steady state is improved, and the stability of data collection is improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an adaptive method and device for a clock and data recovery circuit. Background Art

[0002] Clock and Data Recovery (CDR) is a core functional module of modern digital communication systems and is widely used in various wireless and wired communication systems. The goal of the clock and data recovery circuit is to track the clock drift and a certain range of clock jitter at the receiving end to ensure correct data sampling. The principle of CDR is to sample the data using the multi-phase clock generated locally at the receiving end, and to determine the edge of the data bit through the phase detector. The output of the phase detector is filtered and then controls the voltage-controlled oscillator or phase interpolator to form a loop, and adjusts the local sampling clock edge to align with the edge of the received data, thereby realizing the recovery of the clock with the same frequency and phase as the data.

[0003] Among the many components used in the clock and data recovery circuit, the loop filter is the most important component because it determines the system transfer function and dynamic range. The bandwidth, type and order of the loop filter need to balance the indicators of noise and frequency capture range, as well as the stability of the system. When there is a large frequency deviation between the transmission end clock and the receiving end clock, the CDR loop filter needs to provide sufficient bandwidth to achieve the recovery of the same frequency and phase clock. On the other hand, when the clock and data recovery circuit enters the steady state, an overly wide loop bandwidth will lead to a large output phase noise, affecting the stability of data sampling. Summary of the invention

[0004] The object of the present invention is to provide an adaptive method and device for a clock and data recovery circuit to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: an adaptive method for a clock and data recovery circuit, comprising the following steps: Step S1: receiving data sent by the sending device through a sampler, and processing and transmitting the data signal; Step S2: Receive the data signal transmitted by the sampler through the phase detector, determine the phase deviation and frequency deviation between the sending clock and the receiving clock, and output the phase error signal ; Step S3: By converting the phase error signal Transmit to the loop filter, eliminate noise and interference signals, first analyze the frequency response of the loop filter, and determine the range and relative relationship of parameter adjustment; Step S4: Secondly, the statistical characteristics of the Loop Filter output are calculated in real time to determine the working status of the CDR; Step S5: Finally, the CDR state machine is implemented to determine how to adjust the parameters and output range of the Loop Filter according to the statistical characteristics of the Loop Filter output and based on the principle of threshold detection; Step S6: The output signal of the loop filter enters the voltage-controlled oscillator to form a loop, and adjusts the local sampling clock edge to align with the edge of the received data, thereby realizing the recovery of the clock with the same frequency and phase as the data.

[0006] Preferably, the open-loop frequency response of the loop filter in step S3, taking a second-order loop filter as an example, is: ; Known , the system function of CDR is: ; The system function H(Z) has (N+1) poles and a single zero. In order to ensure the stability and causality of the system, the (N+1) poles of H(Z) must all be within the unit circle (|Z|=1), and the distribution of zeros and poles jointly affects the frequency response of the system. Given the system delay N, the system analysis determines the adjustment range and relative relationship of K, K1, and K2. In the formula, K is the common gain of the CDR loop, K1 and K2 are the gains of the first-order and second-order integrators respectively. The system analysis method is applicable to second-order loop filters and loop filters of any order.

[0007] Preferably, in step S4, The working state of CDR can be divided into the capture phase and the tracking phase. In the capture phase, In a wide range of changes, Follow Rapid changes require H(Z) to provide sufficient bandwidth. Under the condition of ensuring system stability, the increased K and the gains of each order integrator (K1, K2, ... K n ),ensure Quick Follow changes.

[0008] Preferably, in step S4, during the tracking phase, Will jitter around 0, at this time CDR avoids Follow The jitter will cause unnecessary changes, and it is necessary to reduce K and the gains of each order integrator (K1, K2, ...K n ).

[0009] Preferably, the CDR state machine in step S5 includes: The common gain of the clock and data recovery circuits and the gain of the loop filter integrator are all configurable in real time; The output of the clock and data recovery circuit includes a limiter, and the output amplitude of the limiter is configurable; For the non-limited phase output and frequency output of the loop filter, their statistical characteristics, including but not limited to mean and variance, are calculated in real time.

[0010] Preferably, the CDR state machine in step S5 includes two important design parameters: acq_th and track_th, which respectively correspond to the detection thresholds of the CDR tending to the capture state and the CDR tending to the tracking state. The main task is to calculate the statistical characteristics of the phase output and frequency output of the loop filter, and compare them with the set thresholds acq_th and track_th.

[0011] Preferably, the CDR state machine further includes: The CDR state machine determines the time and direction of adjusting K and the gain of each order integrator. When the CDR is in the capture state, it is necessary to maintain a high value of K and the gain of each order integrator. When the CDR state tends to converge, K and the gain of each order integrator can be gradually reduced. Given the system delay N, K, and the adjustment range and granularity of each order integrator gain are determined by the stability analysis and frequency response of the system function H(Z); No matter whether K and the gains of each order integrator are increased or decreased, the gain change value each time cannot exceed the set threshold to smooth the transient response caused by the gain change.

[0012] Preferably, the CDR state machine further includes: When the CDR tends to capture state, K and the gain of each order integrator are increased according to the pre-calculated granularity, and the output limit is adjusted accordingly. K and the gain of each order integrator need to be within the pre-set range. When the CDR tends to the tracking state, K and the gains of each order integrator are reduced according to the pre-calculated granularity, and the output limit is adjusted accordingly. K and the gains of each order integrator need to be within the pre-set range. During the CDR state adjustment process, the detection thresholds acq_th and track_th are also adjusted based on the corresponding design granularity: when K and the gains of each order integrator increase, as well as The range of change increases, so the detection thresholds acq_th and track_th based on the statistical characteristics of the two will also increase; when K and the gains of each order integrator decrease, as well as The variation range of is reduced, so the detection thresholds acq_th and track_th based on the statistical characteristics of the two will also be reduced; The state machine includes a wait state: when the parameters of the CDR change, the state machine enters the wait state, ignoring the unstable results caused by the transient response.

[0013] An adaptive device for a clock and data recovery circuit, comprising: A sampler, the sampler is used to receive data sent by the sending device; A phase detector is connected to the sampler, and is used to determine the phase deviation and frequency deviation between the sending clock and the receiving clock and output a phase error signal ; A loop filter, the loop filter is connected to the phase detector, and the loop filter is used to adjust the built-in gain and output range of the loop filter in real time according to the working state of the CDR; A voltage controlled oscillator is connected to the loop filter and the sampler.

[0014] Preferably, the loop filter comprises: A gainer, the gainer being used to adjust the strength of the phase detector output signal and adjust the gain of the amplifier to match the state of the clock and data recovery circuit; A delay device, wherein the delay device is used to adjust the response time of the gain device; A statistical characteristic analysis module, which is used to calculate the statistical characteristics of the Loop Filter output in real time and determine the working status of the CDR; A CDR state machine, wherein the CDR state machine is used to adjust the parameters and output range of the Loop Filter according to the statistical characteristics of the Loop Filter output and based on the principle of threshold detection; A limiter is provided for dynamic range control, peak protection and noise elimination.

[0015] Technical effects and advantages of the present invention: The present invention utilizes the setting mode of cooperating the statistical characteristics of the Loop Filter output and the CDR state machine, analyzes the frequency response of the loop filter, determines the range and relative relationship of parameter adjustment, and then calculates the statistical characteristics of the Loop Filter output in real time to determine the working state of the CDR, and implements the CDR state machine. According to the statistical characteristics of the Loop Filter output and based on the principle of threshold detection, it is determined to adjust the parameters and output range of the Loop Filter, so as to achieve the purpose of monitoring the working state of the CDR circuit, adjust the design parameters of the Loop Filter in real time according to the state change, and improve the phase noise of the CDR in the steady state while ensuring a sufficient frequency capture range, thereby improving the stability of data acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the CDR adaptive filtering principle of the present invention.

[0017] Figure 2 It is a schematic diagram of the CDR state machine flow of the present invention.

[0018] Figure 3 It is a schematic diagram of the structure of the CDR adaptive device of the present invention.

[0019] Figure 4 It is a schematic diagram of the structure of the two-loop filter of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The present invention provides Figure 1-2 The self-adaptive method of a clock and data recovery circuit shown comprises the following steps: Step S1: receiving data sent by the sending device through a sampler, and processing and transmitting the data signal; Step S2: Receive the data signal transmitted by the sampler through the phase detector, determine the phase deviation and frequency deviation between the sending clock and the receiving clock, and output the phase error signal ; Step S3: By converting the phase error signal Transmit to the loop filter, eliminate noise and interference signals, first analyze the frequency response of the loop filter, and determine the range and relative relationship of parameter adjustment; Step S4: Secondly, the statistical characteristics of the Loop Filter output are calculated in real time to determine the working status of the CDR; Step S5: Finally, the CDR state machine is implemented to determine how to adjust the parameters and output range of the Loop Filter according to the statistical characteristics of the Loop Filter output and based on the principle of threshold detection; Step S6: The output signal of the loop filter enters the voltage-controlled oscillator to form a loop, and adjusts the local sampling clock edge to align with the edge of the received data, thereby realizing the recovery of the clock with the same frequency and phase as the data.

[0022] In step S3, the open-loop frequency response of the loop filter is calculated by taking a second-order loop filter as an example. The formula is: ; Known , the system function of CDR is: ; The system function H(Z) has (N+1) poles and a single zero. . In order to ensure the stability and causality of the system, the (N+1) poles of H(Z) must all be within the unit circle (|Z|=1), and the distribution of zeros and poles jointly affects the frequency response of the system. Given the system delay N, the system analysis determines the adjustment range and relative relationship of K, K1, and K2. Z / (Z-1) is the Z transformation of the integration circuit, and K1 and K2 are the gains of the first-order and second-order integrators, respectively. It should be noted that delays are inevitably introduced in the system implementation, so the delay logic Z must be included in the transfer function for phase output and frequency output. -N ,The second-order loop filter is the most commonly used loop filter in CDR, but it can be extended to loop filters of any order.

[0023] In step S4, according to The working state of CDR can be divided into the capture phase and the tracking phase. In the capture phase, In a wide range of changes, Follow Rapid changes require H(Z) to provide sufficient bandwidth. Under the condition of ensuring system stability, the gains of integrators of various orders (K1, K2, ...K n ),ensure Quick Follow changes, in the tracking phase, Will jitter around 0, at this time CDR avoids Follow The jitter will cause unnecessary changes, and the gains of each order integrator (K1, K2, ...K n), when CDR starts, due to the unknown frequency deviation and phase deviation between the sending clock and the receiving clock, The range of variation is large, especially when the frequency deviation is large. Oscillations may occur as Gradually locked changes, The absolute value of gradually decreases, and finally achieves dynamic balance. ≈ ,| |≈0, in the capture and tracking phases, The value range of the former will also be different. In the former, the system design hopes to speed up changes so as to be able to catch up quickly changes, so I don't want to limit | |, but in the latter state, the system design hopes to avoid occasional abnormal events causing drastic changes, so it is necessary to Within a certain range, while adaptively adjusting the Loop Filter parameters, it will also adjust in real time The output range of

[0024] In step S5, the CDR state machine includes: The common gain of the clock and data recovery circuits and the gain of the loop filter integrator are all configurable in real time; The output of the clock and data recovery circuit includes a limiter, and the output amplitude of the limiter is configurable; For the non-limited phase output and frequency output of the loop filter, their statistical characteristics, including but not limited to mean and variance, are calculated in real time.

[0025] The CDR state machine in step S5 includes two important design parameters: acq_th and track_th, which correspond to the detection thresholds of the CDR tending to the capture state and the CDR tending to the tracking state respectively. The main task is to calculate the statistical characteristics of the phase output and frequency output of the loop filter and compare them with the set thresholds acq_th and track_th.

[0026] The CDR state machine also includes: The CDR state machine determines the time and direction of adjusting K and the gain of each order integrator. When the CDR is in the capture state, it is necessary to maintain a high value of K and the gain of each order integrator. When the CDR state tends to converge, K and the gain of each order integrator can be gradually reduced. Given the system delay N, K, and the adjustment range and granularity of each order integrator gain are determined by the stability analysis and frequency response of the system function H(Z); No matter whether K and the gains of each order integrator are increased or decreased, the gain change value each time cannot exceed the set threshold to smooth the transient response caused by the gain change.

[0027] The CDR state machine also includes: When the CDR tends to capture state, K and the gain of each order integrator are increased according to the pre-calculated granularity, and the output limit is adjusted accordingly. K and the gain of each order integrator need to be within the pre-set range. When the CDR tends to the tracking state, K and the gains of each order integrator are reduced according to the pre-calculated granularity, and the output limit is adjusted accordingly. K and the gains of each order integrator need to be within the pre-set range. During the CDR state adjustment process, the detection thresholds acq_th and track_th are also adjusted based on the corresponding design granularity: when K and the gains of each order integrator increase, as well as The range of change increases, so the detection thresholds acq_th and track_th based on the statistical characteristics of the two will also increase; when K and the gains of each order integrator decrease, as well as The variation range of is reduced, so the detection thresholds acq_th and track_th based on the statistical characteristics of the two will also be reduced; The state machine includes a wait state: when the parameters of the CDR change, the state machine enters the wait state, ignoring the unstable results caused by the transient response.

[0028] The present invention provides Figure 3-4 The adaptive device of a clock and data recovery circuit shown in the figure includes a sampler, a phase detector, a loop filter and a voltage-controlled oscillator. The sampler is used to receive data sent by a sending device. The phase detector is connected to the sampler. The phase detector is used to determine the phase deviation and frequency deviation between the sending clock and the receiving clock and output a phase error signal The loop filter is connected to the phase detector. The loop filter is used to adjust the built-in gain and output range of the loop filter in real time according to the working status of the CDR. The loop filter is composed of a first-order or multi-order integrator. The voltage-controlled oscillator is connected to the loop filter and the sampler. Based on the flip characteristics of the digital signal after sampling, the phase detector can determine the phase deviation and frequency deviation between the sending clock and the receiving clock. Assuming that the receiving sampling clock is unchanged and excluding the influence of noise and channel, when the sending clock and the receiving clock are of the same frequency but different phase, the error signal is a constant that does not change with time. When there is a deviation in the frequency of the sending clock and the receiving clock, It changes linearly with time, and its slope is the normalized frequency deviation, so in theory, the receiving device can analyze The time domain characteristics of the transmission channel and the analog front end cause the ideal transmission clock to be restored. Contains significant linear and nonlinear interference, as well as noise, which masks the true phase deviation and frequency deviation, so The local clock can only be reconstructed after the noise and interference signals are eliminated through the loop filter.

[0029] The loop filter includes an amplifier, a delay device, a statistical characteristic analysis module, a CDR state machine and a limiter. The amplifier is used to adjust the strength of the phase detector output signal and adjust the gain of the amplifier to match the state of the clock and data recovery circuit. The delay device is used to adjust the response time of the amplifier. The statistical characteristic analysis module is used to calculate the statistical characteristics of the LoopFilter output in real time and determine the working state of the CDR. The CDR state machine is used to adjust the parameters and output range of the LoopFilter according to the statistical characteristics of the LoopFilter output and based on the principle of threshold detection. The limiter is used for dynamic range control, peak protection and noise elimination.

[0030] Principle of the present invention: By analyzing the frequency response of the loop filter, the range and relative relationship of parameter adjustment are determined, and then the statistical characteristics of the Loop Filter output are calculated in real time to determine the working state of the CDR, and the CDR state machine is implemented. According to the statistical characteristics of the LoopFilter output and based on the principle of threshold detection, it is decided to adjust the parameters and output range of the Loop Filter to achieve the purpose of monitoring the working state of the CDR circuit. The design parameters of the Loop Filter are adjusted in real time according to the state changes. While ensuring sufficient frequency capture range, the phase noise in the CDR steady state is improved, thereby improving the stability of data acquisition.

[0031] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An adaptive method for a clock and data recovery circuit, characterized in that: The following steps are involved: Step S1: receiving data sent by the sending device through a sampler, and processing and transmitting the data signal; Step S2: Receive the data signal transmitted by the sampler through the phase detector, determine the phase deviation and frequency deviation between the sending clock and the receiving clock, and output the phase error signal ; Step S3: By converting the phase error signal Transmit to the loop filter, eliminate noise and interference signals, first analyze the frequency response of the loop filter, and determine the range and relative relationship of parameter adjustment; Step S4: Secondly, the statistical characteristics of the loop filter output are calculated in real time to determine the working state of the CDR; Step S5: Finally, the CDR state machine is implemented to determine how to adjust the parameters and output range of the Loop Filter according to the statistical characteristics of the Loop Filter output and based on the principle of threshold detection; Step S6: The output signal of the loop filter enters the voltage-controlled oscillator to form a loop, and adjusts the local sampling clock edge to align with the edge of the received data, thereby realizing the recovery of the clock with the same frequency and phase as the data.

2. The adaptive method of a clock and data recovery circuit according to claim 1, characterized in that: The open-loop frequency response of the loop filter in step S3, taking a second-order loop filter as an example, is: ； Known (Z)= (Z)- (Z), the system function of CDR is: ； The system function H(Z) has (N+1) poles and a single zero. To ensure the stability and causality of the system, the (N+1) poles of H(Z) must all be within the unit circle (|Z|=1), and the distribution of zeros and poles jointly affects the frequency response of the system. Given the system delay N, the system analysis determines K, 1. As well as the adjustment range and relative relationship of K2, K in the formula is the common gain of the CDR loop, K1 and K2 are the gains of the first-order and second-order integrators respectively, and the system analysis method is applicable to second-order loop filters and loop filters of any order.

3. The adaptive method of a clock and data recovery circuit according to claim 2, characterized in that: In step S4, according to The working state of CDR can be divided into the capture phase and the tracking phase. In the capture phase, In a wide range of changes, Follow Rapid changes require H(Z) to provide sufficient bandwidth. Under the condition of ensuring system stability, the increased K and the gains of each order integrator (K1, K2, ...K n ),ensure Quick Follow changes.

4. The adaptive method of a clock and data recovery circuit according to claim 3, characterized in that: The step S4 is in the tracking stage, Will jitter around 0, at this time CDR avoids Follow To prevent unnecessary changes due to jitter, it is necessary to reduce K and the gains of integrators of each order.

5. The adaptive method of a clock and data recovery circuit according to claim 4, characterized in that: The CDR state machine in step S5 includes: The common gain of the clock and data recovery circuits and the gain of the loop filter integrator are all configurable in real time; The output of the clock and data recovery circuit includes a limiter, and the output amplitude of the limiter is configurable; For the non-limited phase output and frequency output of the loop filter, their statistical characteristics, including but not limited to mean and variance, are calculated in real time.

6. The adaptive method of a clock and data recovery circuit according to claim 5, characterized in that: The CDR state machine in step S5 includes two important design parameters: acq_th and track_th, which correspond to the detection thresholds of the CDR tending to the capture state and the CDR tending to the tracking state respectively. The main task is to calculate the statistical characteristics of the phase output and frequency output of the loop filter, and compare them with the set thresholds acq_th and track_th.

7. The adaptive method of a clock and data recovery circuit according to claim 5, characterized in that: The CDR state machine also includes: The CDR state machine determines the time and direction of adjusting K and the gain of each order integrator. When the CDR is in the capture state, it is necessary to maintain a high value of K and the gain of each order integrator. When the CDR state tends to converge, K and the gain of each order integrator can be gradually reduced. Given the system delay N, K, and the adjustment range and granularity of each order integrator gain are determined by the stability analysis and frequency response of the system function H(Z); No matter whether K and the gains of each order integrator are increased or decreased, the gain change value each time cannot exceed the set threshold to smooth the transient response caused by the gain change.

8. The adaptive method of a clock and data recovery circuit according to claim 6, characterized in that: The CDR state machine also includes: When the CDR tends to capture state, K and the gain of each order integrator are increased according to the pre-calculated granularity, and the output limit is adjusted accordingly. K and the gain of each order integrator need to be within the pre-set range. When the CDR tends to the tracking state, K and the gains of each order integrator are reduced according to the pre-calculated granularity, and the output limit is adjusted accordingly. K and the gains of each order integrator need to be within the pre-set range. During the CDR state adjustment process, the detection thresholds acq_th and track_th are also adjusted based on the corresponding design granularity: when K and the gains of each order integrator increase, as well as The range of change increases, so the detection thresholds acq_th and track_th based on the statistical characteristics of the two will also increase; when K and the gains of each order integrator decrease, as well as The variation range of is reduced, so the detection thresholds acq_th and track_th based on the statistical characteristics of the two will also be reduced; The state machine includes a wait state: when the parameters of the CDR change, the state machine enters the wait state, ignoring the unstable results caused by the transient response.

9. An adaptive device for a clock and data recovery circuit, characterized in that: include: A sampler, the sampler is used to receive data sent by the sending device; A phase detector is connected to the sampler, and is used to determine the phase deviation and frequency deviation between the sending clock and the receiving clock and output a phase error signal ; A loop filter, the loop filter is connected to the phase detector, and the loop filter is used to adjust the built-in gain and output range of the loop filter in real time according to the working state of the CDR; A voltage controlled oscillator is connected to the loop filter and the sampler.

10. The adaptive device of a clock and data recovery circuit according to claim 9, characterized in that: The loop filter comprises: A gainer, the gainer being used to adjust the strength of the phase detector output signal and adjust the gain of the amplifier to match the state of the clock and data recovery circuit; A delay device, wherein the delay device is used to adjust the response time of the gain device; A statistical characteristic analysis module, which is used to calculate the statistical characteristics of the Loop Filter output in real time and determine the working status of the CDR; A CDR state machine, wherein the CDR state machine is used to adjust the parameters and output range of the Loop Filter according to the statistical characteristics of the Loop Filter output and based on the principle of threshold detection; A limiter is provided for dynamic range control, peak protection and noise elimination.

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