Polishing pad trimmer, polishing pad and silicon wafer

Abstract

The invention provides a polishing pad trimmer, a polishing pad and a silicon wafer, the polishing pad trimmer comprises a trimmer body, the trimmer body is provided with a trimming surface used for trimming the surface of the polishing pad, the trimming surface is provided with a trimming area, and the trimming area is constructed to be provided with abrasive particles; wherein the finishing area comprises a plurality of sub-finishing areas, the plurality of sub-finishing areas are sequentially distributed at intervals in the circumferential direction of the finishing surface, and the total area of the finishing area on the finishing surface accounts for 10-30%. According to the polishing pad trimmer, the polishing pad and the silicon wafer provided by the invention, the uniformity and the smoothness of the trimmed polishing pad can be improved, so that the force applied to the silicon wafer by the polishing pad in the polishing process of the silicon wafer is more uniform, and the edge flatness of the silicon wafer is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor processing, and in particular to a polishing pad dresser, a polishing pad and a silicon wafer. Background Art

[0002] Chemical Mechanical Polishing (CMP) is a technology that combines chemical and mechanical actions. It is a means to achieve global flatness in the semiconductor process. During the CMP process, the surface material of the silicon wafer to be processed first reacts chemically with the oxidant, catalyst, etc. in the polishing liquid to form a relatively easy-to-remove soft layer. Then, the soft layer is removed under the mechanical action of the abrasive and polishing pad in the polishing liquid, so that the surface of the silicon wafer to be processed is exposed again. Then a chemical reaction is carried out, so that the surface polishing of the silicon wafer to be processed is completed in the alternation of the chemical and mechanical processes. The polishing pad has an important influence on the quality of the surface formed by chemical mechanical polishing.

[0003] In chemical mechanical polishing equipment, a polishing pad dresser is usually used to dress the surface of the polishing pad to remove the glaze layer and restore the surface roughness of the polishing pad.

[0004] Edge flatness is a very important parameter in silicon wafer flatness. However, in the prior art, the edge flatness of silicon wafers after CMP process needs to be improved. Summary of the invention

[0005] In order to solve at least one technical problem in the above-mentioned prior art, an embodiment of the present disclosure provides a polishing pad conditioner, a polishing pad and a silicon wafer.

[0006] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0007] In the first aspect, an embodiment of the present disclosure provides a polishing pad conditioner, comprising a conditioner body, the conditioner body having a dressing surface for conditioning the surface of the polishing pad, the dressing surface having a dressing area, the dressing area being configured to have abrasive particles; wherein the dressing area comprises a plurality of sub-dressing areas, and the plurality of sub-dressing areas are distributed in sequence at intervals along the circumference of the dressing surface, and the total area of ​​the dressing areas on the dressing surface accounts for 10 to 30%.

[0008] Exemplarily, the sub-trimming regions are circular in shape, and the areas of the sub-trimming regions are the same.

[0009] Exemplarily, the plurality of sub-trimming areas are evenly distributed along the circumference of the trimming surface, and the central angles corresponding to any two adjacent sub-trimming areas are the same.

[0010] Exemplarily, the central angle between any two adjacent sub-trimming areas ranges from 60° to 120°.

[0011] Exemplarily, the mesh size of the abrasive particles in the dressing area is greater than or equal to 200 meshes.

[0012] Exemplarily, the trimming surface further includes a supporting area, and the plurality of sub-trimming areas surround the periphery of the supporting area.

[0013] In a second aspect, an embodiment of the present disclosure further provides a polishing pad having a surface trimmed by the polishing pad dresser as described above.

[0014] Exemplarily, the material hardness of the polishing pad is greater than or equal to 80 JIS-A.

[0015] Exemplarily, the material of the polishing pad includes polyurethane.

[0016] In a third aspect, an embodiment of the present disclosure further provides a silicon wafer obtained by grinding with the polishing pad as described above, wherein the front side reference least square range ESFQR value of the edge portion of the silicon wafer is in the range of 20 to 40 nanometers.

[0017] The beneficial effects brought by the embodiments of the present disclosure are as follows:

[0018] In the polishing pad conditioner, polishing pad and silicon wafer provided in the embodiments of the present disclosure, a trimming area is provided on the trimming surface of the polishing pad conditioner, and the trimming area is constructed to include a plurality of sub-trimming areas, the plurality of sub-trimming areas are sequentially spaced along the circumference of the trimming surface, and the total area ratio of all sub-trimming areas on the trimming surface is 10-30%. In this way, by optimizing the design of the trimming area on the polishing pad conditioner and increasing the total area ratio of the trimming area on the trimming surface, the contact area between the trimming area and the polishing pad is increased, so as to improve the uniformity and flatness of the polishing pad after trimming, thereby making the force exerted on the silicon wafer by the polishing pad during the polishing process of the silicon wafer more uniform, so as to improve the flatness of the edge of the silicon wafer; at the same time, the trimming area is designed to be a plurality of sub-trimming areas sequentially spaced along the circumference of the trimming surface, so as to increase the total area ratio of the trimming area on the trimming surface while avoiding excessive coverage of the trimming area, which causes excessive trimming of the polishing pad, thereby ensuring the expected polishing pad trimming effect to improve the flatness of the edge of the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram showing the structure of a polishing pad conditioner provided in an embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram showing the surface of a polishing pad after being trimmed by a polishing pad trimmer in the prior art;

[0021] Figure 3 A schematic diagram showing the surface of a polishing pad after being trimmed by a polishing pad dresser in an embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram showing the processing state of a silicon wafer when the hardness of the polishing pad itself is low;

[0023] Figure 5 Schematic diagram showing the processing status of a silicon wafer when the polishing pad itself has a high hardness. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0026] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present disclosure include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances associated with the measurement of specific quantities (e.g., the limitations of the measurement system), and represent the acceptable deviation range for a specific value determined by ordinary technicians in the field. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0027] In addition, in this document, unless otherwise defined, the terms "substantially", "substantially", "approximately" and "about" are used to describe and explain small changes. When used with an event or situation, these terms can cover situations where the event or situation occurs exactly, and can also cover situations where the event or situation occurs approximately. For example, when used with a numerical value, these terms can include a range of variation of less than or equal to 10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces being arranged along the same plane in the micrometer range, for example, arranged along the same plane within 40μm, 30μm, 20μm, 10μm or 1μm.

[0028] During the CMP (Chemical Mechanical Polishing) planarization process, a chemical film is first formed on the surface of the silicon wafer under the action of the chemical components of the polishing liquid, and then the chemical film is removed by the mechanical wear of the abrasive particles. Therefore, the CMP planarization process is essentially achieved by the combined action of the chemical film generation and chemical film removal modes.

[0029] Polishing pads play an important role in the CMP process. They carry polishing liquid, replenish new polishing liquid, and remove polishing products. In order to ensure the stability and uniformity of CMP processing quality, the surface structure of the polishing pad must remain stable and consistent.

[0030] However, in the actual CMP process, the micro-pits on the surface of the polishing pad are attached by the polishing products, resulting in glazing of the surface of the polishing pad, which makes it impossible for the polishing liquid to stay on its surface, thereby reducing the processing efficiency and quality of the silicon wafer.

[0031] In order to solve the glazing problem of the polishing pad, a polishing pad dresser (Disk) is used to dress the surface of the polishing pad. The dresser plows the surface of the polishing pad through abrasive structures such as artificial diamonds embedded on the surface to achieve the dressing of the polishing pad.

[0032] Edge flatness is a very important parameter in silicon wafer flatness. However, in the prior art, the edge flatness of silicon wafers after CMP process needs to be improved.

[0033] After research, the applicant of the present disclosure found that during the dressing process of the polishing pad, due to factors such as the contact area and mesh size between the dressing area with abrasive particles in the polishing pad dresser and the polishing pad, the polishing pad after dressing is uneven and non-uniform, which causes the extrusion force on the silicon wafer to be dispersed at various locations during the polishing process, resulting in uncontrollable wafer flatness.

[0034] Based on this, an embodiment of the present disclosure provides a polishing pad conditioner that can improve the flatness of a silicon wafer.

[0035] like Figure 1 As shown, the polishing pad conditioner provided by the embodiment of the present disclosure includes a conditioner body 100, wherein the conditioner body 100 has a conditioning surface 110 for conditioning the surface of the polishing pad, wherein the conditioning surface 110 has a conditioning area 200, and the conditioning area 200 is constructed to have abrasive particles; wherein the conditioning area 200 includes a plurality of sub-conditioning areas 210, and the plurality of sub-conditioning areas 210 are distributed in sequence along the circumference of the conditioning surface 110, and the total area of ​​the conditioning area 200 on the conditioning surface 110 accounts for 10 to 30%.

[0036] In the above scheme, the trimming area 200 is set on the trimming surface 110 of the polishing pad dresser, and the trimming area 200 is constructed to include a plurality of sub-trimming areas 210, and the plurality of sub-trimming areas 210 are sequentially spaced along the circumference of the trimming surface 110, and the total area of ​​all the sub-trimming areas 210 on the trimming surface 110 accounts for 10-30%. In this way, by optimizing the design of the trimming area 200 on the polishing pad dresser and increasing the total area of ​​the trimming area 200 on the trimming surface 110, the contact area between the trimming area 200 and the polishing pad is increased, so as to improve the uniformity and flatness of the polishing pad after trimming, so that the force applied to the silicon wafer by the polishing pad during the polishing process of the silicon wafer is more uniform, so as to improve the flatness of the edge of the silicon wafer.

[0037] At the same time, there are many ways to increase the area of ​​the trimming zone 200. For example, the trimming zone 200 can be designed as an annular area arranged around the middle area of ​​the trimming surface 110, and the area proportion of the trimming zone 200 can be increased by increasing the width of the annular area.

[0038] However, compared with directly designing the trimming area 200 as an annular area arranged around the middle area of ​​the trimming surface 110, designing the trimming area 200 as a plurality of sub-trimming areas 210 that are sequentially spaced along the circumference of the trimming surface 110 can increase the total area proportion of the trimming area 200 on the trimming surface 110 while avoiding excessive coverage of the trimming area 200 to cause excessive trimming of the polishing pad, thereby ensuring that the expected polishing pad trimming effect is achieved to improve the flatness of the silicon wafer edge.

[0039] It should be noted that the trimming area 200 has abrasive grains, for example, the abrasive grains may include diamond abrasive grains.

[0040] For example, in some embodiments, the dresser body 100 may include a dresser base and a grinding sheet, etc. The material of the dresser base may be diamond abrasive stainless steel or PC engineering plastic.

[0041] The stainless steel substrate is made by mechanical precision machining, and the PC engineering plastic substrate is made by mechanical precision machining or injection molding.

[0042] The trimmer base may include a mounting hole, a positioning hole, and a grinding plate mounting groove. The grinding plate may include a grinding plate base, a connecting layer, abrasive particles, etc. The grinding plate is formed as the sub-dressing area 210. The grinding plate base is installed in the grinding plate mounting groove.

[0043] The grinding disc substrate can be a stainless steel original disc substrate and a ceramic substrate. The grinding disc substrate and the inner wall of the grinding disc mounting groove are connected by a fixing material. The fixing material can be epoxy resin, PU polyurethane glue or silica gel. The abrasive particles can include: diamond, cubic boron nitride or a combination of the two.

[0044] The arrangement of abrasive particles on the surface of the grinding disc substrate includes spiral, horizontal, vertical and radial arrangements.

[0045] The methods of fixing abrasive particles include: electroplating process, brazing process, and resin curing process.

[0046] The electroplating process is to fix the abrasive by electroplating a nickel-chromium composite coating; the brazing process is to fix the abrasive by vacuum sintering nickel-chromium alloy materials; and the resin curing process is to fix the abrasive by curing the resin.

[0047] The connection layer can be brazing material, epoxy resin or nickel-chromium composite plating, etc.

[0048] In addition, in some exemplary embodiments of the present disclosure, Figure 1 As shown, the dressing surface 110 further includes a support area 120, and a plurality of sub-dressing areas 210 surround the periphery of the support area 120. The support area 120 can be in contact with the polishing pad when dressing the polishing pad.

[0049] It should be understood that the above is only an example, and the specific structures of the trimmer body 100 and the trimming area 200 are not limited thereto.

[0050] In some exemplary embodiments, Figure 1 As shown, the sub-trimming area 210 may be circular in shape, and the areas of the sub-trimming areas 210 are the same.

[0051] By adopting the above solution, the sub-dressing area 210 is constructed as a circular area. When the polishing pad is dressed by the polishing pad dresser, the circular sub-dressing area 210 has a smooth edge and no sharp corners, which can avoid damage to the polishing pad. The areas of the sub-dressing areas 210 can be the same, so that the force can be uniform during the polishing pad dressing process, thereby improving the uniformity and flatness of the polishing pad after dressing.

[0052] Of course, it is understandable that the shape of the sub-trimming area 210 is not limited to a circle, as long as the sub-trimming area 210 has no sharp corners or edges on its outline, for example, the sub-trimming area 210 can also be an ellipse.

[0053] Furthermore, in some exemplary embodiments, Figure 1 As shown, the plurality of sub-trimming areas 210 are evenly distributed along the circumference of the trimming surface 110, and the corresponding central angles between any two adjacent sub-trimming areas 210 are the same. In this way, the polishing pad can be subjected to uniform force during the trimming process, further improving the uniformity and flatness of the trimmed polishing pad.

[0054] Exemplarily, the value range of the central angle between any two adjacent sub-trimming areas 210 is 60 to 120°. In other words, the number of the sub-trimming areas 210 can be 3 to 6, but this is not limiting.

[0055] For example, in one embodiment, the number of the sub-trimming areas 210 is 6, and the corresponding central angle between any two adjacent sub-trimming areas 210 is 60°; in another embodiment, the number of the sub-trimming areas 210 is 3, and the corresponding central angle between any two adjacent sub-trimming areas 210 is 120°.

[0056] In addition, in the embodiment of the present disclosure, the uniformity and flatness of the polishing pad dressing can be further improved by increasing the mesh size of the abrasive grains in the dressing area 200 to improve the flatness of the silicon wafer after polishing. For example, the mesh size of the abrasive grains in the dressing area 200 is greater than or equal to 200 meshes.

[0057] Figure 2 The figure is a schematic diagram of the polishing pad surface after being trimmed by the polishing pad dresser in the prior art; Figure 3 Shown is a schematic diagram of the surface of the polishing pad after being trimmed by the polishing pad dresser in an embodiment of the present disclosure.

[0058] from Figure 2 and Figure 3 It can be seen that the polishing pad conditioner in the embodiment of the present disclosure can improve the surface flatness of the polishing pad 10 .

[0059] In addition, an embodiment of the present disclosure further provides a polishing pad having a surface trimmed by the polishing pad dresser provided by an embodiment of the present disclosure.

[0060] After research, the applicant of the present disclosure found that during the polishing process, the edge of the silicon wafer is squeezed in different directions, resulting in pressure dispersion at the edge, causing unstable removal rate at the edge of the silicon wafer, and further causing the morphology of the edge of the silicon wafer to be uncontrollable, affecting the flatness level of the silicon wafer and reducing product competitiveness.

[0061] Based on this, in order to improve the edge flatness of the silicon wafer, in some embodiments of the present disclosure, the edge flatness of the silicon wafer can also be improved by increasing the hardness of the polishing pad.

[0062] For detailed principles, please refer to Figure 4 and Figure 5 shown. Figure 4 The figure shows a schematic diagram of the processing state of a silicon wafer when the hardness of the polishing pad itself is low; Figure 5 The figure is a schematic diagram of the processing state of a silicon wafer when the hardness of the polishing pad itself is relatively high.

[0063] from Figure 4 It can be seen that during the polishing process, when the hardness of the polishing pad 10 itself is low and the strength is low, when it is subjected to a large external pressure, it will deform, such as Figure 4 The dotted frame A shows the deformed position of the polishing pad 10 .

[0064] like Figure 5 As shown, after the hardness of the polishing pad 10 is increased, during the polishing process, the polishing pad 10 can withstand a large part of the pressure from the outside due to its high hardness, so that the deformation of the polishing pad 10 during the polishing process is reduced, as shown in FIG. Figure 5 The dotted box B in the middle shows the deformation position of the polishing pad 10. In this way, after the hardness of the polishing pad 10 is improved, the unstable factor of the edge of the silicon wafer 20 can be reduced, so that the edge position of the silicon wafer 20 can be controlled during the entire polishing process, thereby stabilizing the removal rate of the silicon wafer edge and improving the flatness of the silicon wafer edge.

[0065] In some exemplary embodiments, the hardness of the polishing pad may be greater than or equal to 80 JIS-A. For example, the hardness of the polishing pad is 80 JIS-A.

[0066] Materials with a hardness of 80JIS-A generally have good flexibility and strength, and are suitable for applications that require a certain degree of hardness but do not want the material to be too rigid. In other words, the hardness of 80JIS-A provides a good balance of performance, which can withstand a certain amount of pressure while maintaining a certain degree of flexibility.

[0067] Therefore, the hardness of the material of the polishing pad is selected to be greater than or equal to 80JIS-A, and can have a certain hardness, which can not only reduce the deformation of the polishing pad during the polishing process to improve the flatness of the silicon wafer edge, but also avoid adverse damage to the silicon wafer caused by excessive hardness; and the relatively high hardness makes the material perform better in terms of wear and aging, thereby extending the service life.

[0068] Exemplarily, the material of the polishing pad includes, but is not limited to, polyurethane having a hardness greater than or equal to 80 JIS-A. For example, the polishing pad may be made by foaming and curing a polyurethane solution to form a block-shaped polyurethane block, and then cutting the polyurethane block to form a polyurethane polishing pad. However, this is not limited thereto.

[0069] ESFQR (Edge Site Front Quotient Range) indicates the amount of change in the roll-up and roll-off of the edge of the silicon wafer relative to the reference plane. The edge morphology of the substrate silicon wafer can be intuitively characterized by the "+" or "-" change relative to the reference plane. ESFQR represents the range of thickness variation in radial length, which is the range of variation of the edge area of ​​the silicon wafer relative to the least squares reference plane. Generally speaking, after a certain amount of silicon wafer edge is removed, the entire silicon wafer edge area is divided into several sector-shaped areas, and the value of ESFQR is the change value of each sector edge area relative to the least squares reference plane. ESFQR is equal to the sum of the absolute values ​​of ESFQD (+) and ESFQD (-), and the ESFQR value is always greater than 0.

[0070] The smaller the edge collapse of the silicon wafer, the smaller the ESFQR value, and the better the flatness of the silicon wafer edge.

[0071] In the prior art, the ESFQR value of the polished silicon wafer is 80-120 nanometers. In the embodiment disclosed herein, on the one hand, the area of ​​the dressing area 200 of the polishing pad dresser and the number of abrasive particles are increased, and on the other hand, the polishing pad is selected from a material with a hardness greater than 80 JIS-A to improve the flatness of the silicon wafer edge.

[0072] Specifically, taking a silicon wafer with an initial thickness of 787 microns as an example, it was polished with the polishing pad of the embodiment of the present invention, and the removal amount was 8 to 12 microns, and the obtained silicon wafer ESFQR value was 20 to 40 nanometers; taking a silicon wafer with an initial thickness of 783 microns as an example, it was polished with the polishing pad of the embodiment of the present invention, and the removal amount was 8 to 12 microns, and the obtained silicon wafer ESFQR value was 20 to 40 nanometers.

[0073] The disclosed embodiment also provides a silicon wafer obtained by grinding according to the polishing pad in the disclosed embodiment, wherein the front side reference least square range ESFQR value of the edge portion of the silicon wafer ranges from 20 to 40 nanometers.

[0074] There are a few points to note:

[0075] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0076] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0077] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0078] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A polishing pad conditioner, characterized in that: The invention comprises a dresser body, wherein the dresser body has a dressing surface for dressing the surface of the polishing pad, the dressing surface has a dressing area, and the dressing area is constructed to have abrasive particles; wherein the dressing area includes a plurality of sub-dressing areas, and the plurality of sub-dressing areas are distributed in sequence along the circumference of the dressing surface, and the total area of ​​the dressing areas on the dressing surface accounts for 10 to 30%.

2. The polishing pad conditioner according to claim 1, characterized in that: The sub-trimming regions are circular in shape, and the areas of the sub-trimming regions are the same.

3. The polishing pad conditioner according to claim 1, characterized in that: The plurality of sub-trimming areas are evenly distributed along the circumference of the trimming surface, and the central angles corresponding to any two adjacent sub-trimming areas are the same.

4. The polishing pad conditioner according to claim 3, characterized in that: The value range of the central angle between any two adjacent sub-trimming areas is 60-120°.

5. The polishing pad conditioner according to claim 1, wherein: The mesh size of the abrasive particles in the dressing area is greater than or equal to 200 meshes.

6. The polishing pad conditioner according to claim 1, wherein: The trimming surface further includes a support area, and a plurality of the trimming sub-areas surround the periphery of the support area.

7. A polishing pad, characterized in that: The polishing pad has a surface dressed by the polishing pad dresser according to any one of claims 1 to 6.

8. The polishing pad according to claim 7, characterized in that The material hardness of the polishing pad is greater than or equal to 80 JIS-A.

9. The polishing pad according to claim 8, characterized in that The polishing pad is made of polyurethane.

10. A silicon wafer obtained by grinding with the polishing pad according to any one of claims 1 to 9, characterized in that: The front side reference least square range ESFQR value of the edge of the silicon wafer ranges from 20 to 40 nanometers.

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