A DRAM array circuit and module for reducing the influence of bit line coupling capacitance

Abstract

The present invention relates to the technical field of DRAM circuit design, and in particular to a DRAM array circuit and module for reducing the influence of bit line coupling capacitance. The present invention comprises: a target array, a reference array, an odd-row sensitive amplifier SA k , even line sensitive amplifier SA j 、Odd row pre-charge circuit PRE k , odd switch S bl,k , odd switch S blb,k . The present invention divides the bit lines of the DRAM array circuit into odd and even rows, and implements odd and even reading by adding an additional precharge circuit to the odd row bit lines and connecting or disconnecting the odd row bit lines and odd row sensitive amplifiers; the odd and even reading of the present invention can greatly reduce the influence of the DRAM array coupling capacitance and significantly improve the accuracy of the DRAM array reading results compared to the traditional DRAM array reading. The present invention solves the problem that the traditional DRAM array circuit is greatly affected by the bit line coupling capacitance when reading.

Description

Technical Field

[0001] The present invention relates to the technical field of DRAM circuit design, and more specifically to: 1. A DRAM array circuit for reducing the influence of bit line coupling capacitance; 2. A DRAM array module for reducing the influence of bit line coupling capacitance. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Compared with static random access memory (SRAM), DRAM has the advantage of a simple structure - each bit of data only requires one capacitor and one transistor to process.

[0003] In order to obtain the maximum cell density, DRAM arrays use an open bitline structure. However, the open bitline structure is more sensitive to bitline-bitline noise because: in the open bitline structure, the switch bitlines are very close. And as the scale of the DRAM array increases, the coupling capacitance between the open bitlines also gradually increases (if the adjacent bitlines read opposite values, the coupling capacitance is the most affected at this time), further aggravating the impact of bitline-bitline noise on the open bitline structure - when the bitline coupling capacitance exceeds the allowable margin, it may cause crosstalk to cause failures and read errors. Summary of the invention

[0004] Based on this, it is necessary to provide a DRAM array circuit and module that reduce the influence of bit line coupling capacitance in order to solve the problem that the traditional DRAM array circuit is greatly affected by the bit line coupling capacitance when reading.

[0005] The present invention is implemented by the following technical solutions:

[0006] In a first aspect, the present invention provides a DRAM array circuit for reducing the influence of bit line coupling capacitance, comprising: a target array, a reference array, an odd-row sense amplifier SA k , even line sensitive amplifier SA j 、Odd row pre-charge circuit PRE k , odd switch S bl,k , odd switch S blb,k .

[0007] Among them, N is an even number; k represents an odd number, k∈[1,3,…,N-1]; j represents an even number, j∈[2,4,…,N].

[0008] The target array includes DRAM target storage cells arranged in N rows and M columns. In the target array, the nth row shares the bit line BL <n>, the mth column common word line WL <m>, bit line BL BL<p+1> There is a coupling capacitor C c1,p ; n∈[1,N], m∈[1,M]; p∈[1,N-1].

[0009] The reference array includes DRAM reference memory cells arranged in N rows and M columns. In the reference array, the nth row shares the bit line BLB. <n>, the mth column common word line WLB <m>, BLB< / m> < / n> ,BLB<p+1> There is a coupling capacitor C c2,p .

[0010] SA j With BL <j>、BLB <j>Connection for amplifying bit line BL <j>、BLB <j>voltage difference.

[0011] S bl,k For controlling BL <k>with SA k On or off; S blb,k For controlling BLB <k>with SA k On or off; SA k For turning on BL <k>、BLB <k>BL <k>、BLB <k>voltage difference.

[0012] PRE k For BL <k>、BLB <k>Precharge.

[0013] The implementation of the DRAM array circuit for reducing the influence of bit line coupling capacitance is based on the method or process of the embodiment of the present disclosure.

[0014] In a second aspect, the present invention discloses a DRAM array module for reducing the influence of bit line coupling capacitance, which adopts the layout of a DRAM array circuit for reducing the influence of bit line coupling capacitance as disclosed in the first aspect.

[0015] The implementation of the DRAM array module that reduces the influence of bit line coupling capacitance is based on the method or process of the embodiment of the present disclosure.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention divides the bit lines of the DRAM array circuit into odd and even rows, and implements odd-even reading by adding an extra precharging circuit to the odd-row bit lines and connecting or disconnecting the odd-row bit lines and odd-row sensitive amplifiers. Compared with traditional DRAM array reading, the odd-even reading of the present invention can greatly reduce the influence of the DRAM array coupling capacitance and significantly improve the accuracy of the DRAM array reading results. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A circuit structure diagram of a DRAM array circuit for reducing the influence of bit line coupling capacitance provided in Embodiment 1 of the present invention;

[0020] Figure 2 for Figure 1 The circuit structure diagram of the DRAM target storage unit and the DRAM reference storage unit;

[0021] Figure 3 for Figure 1 Even-line sense amplifier SA j Circuit diagram of

[0022] Figure 4 for Figure 1 Zhongqixing Sense Amplifier SA k Circuit diagram of

[0023] Figure 5 for Figure 1 Zhongqixing pre-charge circuit PRE k Circuit diagram of

[0024] Figure 6 This is a timing comparison diagram provided for Example 2 of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more related listed items.

[0028] Example 1

[0029] See also Figure 1 , Figure 1 The circuit structure diagram of a DRAM array circuit for reducing the influence of bit line coupling capacitance provided by this embodiment 1 is shown, which includes: a target array, a reference array, an even-row sensitive amplifier SA j , odd-line sensitive amplifier SA k 、Odd row pre-charge circuit PRE k , odd switch S bl,k , odd switch S blb,k .

[0030] It should be noted that k represents an odd number, k∈[1,3,…,N-1]; j represents an even number, j∈[2,4,…,N]. N is an even number.

[0031] That is to say, the even-row sensitive amplifiers SA2~SA N A total of N / 2;

[0032] Odd-line sensitive amplifier SA1~SA N-1 Total N / 2; odd row pre-charge circuit PRE1~PRE N-1 Total N / 2; odd row switches S bl,1 ~S bl,N-1 Total N / 2; odd row switches S blb,1 ~S blb,N A total of N / 2.

[0033] like Figure 1 As shown:

[0034] 1. The target array includes DRAM target storage cells distributed in N rows and M columns.

[0035] In the target array, the nth row shares the bit line BL <n>, the mth column common word line WL <m> , bit line BL< / m> < / n> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / j> < / j> < / j> < / j> BL<p+1> There is a coupling capacitor C c1,p ; n∈[1,N], m∈[1,M]; p∈[1,N-1].

[0036] In addition, BL <n>There is a parasitic capacitance C between the ground VSS bl,n .

[0037] In this embodiment 1, see Figure 2 The DRAM target storage unit in the nth row and the mth column is a 1T1C structure, including: 1 MOS tube N o,n,m , 1 storage capacitor C o,n,m .

[0038] N o,n,m The drain and bit line BL <n>connected, the gate is connected to the word line WL <m>connected, source and C o,n,m One end of C o,n,m The other end is grounded to VSS.

[0039] 2. The reference array includes DRAM reference storage cells distributed in N rows and M columns.

[0040] In the reference array, the nth row shares the bit line BLB <n>, the mth column common word line WLB <m> , BLB< / m> < / n> < / m> < / n> < / n> ,BLB<p+1> There is a coupling capacitor C c2,p .

[0041] In addition, BLB <n>There is a parasitic capacitance C between the ground VSS blb,n .

[0042] In this embodiment 1, see Figure 2 The DRAM reference storage unit in the nth row and the mth column is a 1T1C structure, including: 1 MOS tube N r,n,m , 1 storage capacitor C r,n,m .

[0043] N r,n,m The drain and bit line BLB <n>connected, gate and word line WLB <m>connected, source and C r,n,m One end of C r,n,m The other end is grounded to VSS.

[0044] 3. SA j With BL <j>、BLB <j>Connection for amplifying bit line BL <j>、BLB <j>voltage difference.

[0045] See also Figure 3 , S.A. j The first end (which serves as both an input and an output) of the bit line BL <j>The second terminal (as another input terminal and also as another output terminal) is connected to the bit line BLB <j>connection. Specifically, SA j Includes: 9 NMOS tubes N j,0 ~N j,8 , 2 PMOS tubes P j,0 ~P j,1 .

[0046] P j,0 , P j,1 The source is connected to a control signal SAP1;

[0047] N j,0 The source is connected to the control signal SAN1, and the drain is connected to P j,0 The drain and gate are connected to P j,0 The gate of

[0048] N j,1 The source is connected to SAN1, and the drain is connected to P j,1 The drain and gate are connected to P j,1 The gate of

[0049] N j,2 The gate is connected to the control signal OC1, and the drain is connected to P j,0 The gate and source are connected to P j,0 The drain;

[0050] N j,3 The gate is connected to OC1 and the drain is connected to P j,1 The gate and source are connected to P j,1 The drain;

[0051] N j,4 The gate is connected to the control signal ISO1, and the drain (i.e. the first end) is connected to BL <j>, source connected to P j,0 The drain;

[0052] N j,5 The gate is connected to ISO1, and the drain (i.e. the second end) is connected to BLB <j>, source connected to P j,1 The drain;

[0053] N j,6 The gate is connected to the control signal PRE-SA, and the drain is connected to BLB <j>, source connected to BL <j>;

[0054] N j,7 The gate is connected to PRE-SA, the drain is connected to the control signal VEQ, and the source is connected to BL <j>;

[0055] N j,8 The gate is connected to PRE-SA, the drain is connected to VEQ, and the source is connected to BLB <j>.

[0056] 4. S bl,k For controlling BL <k>with SA k On or off; S blb,k For controlling BLB <k>with SA k Connect or disconnect.

[0057] See also Figure 1 , S.A. k The first end (which serves as both an input and an output) is connected to S bl,k The first end is connected to S blb,k The first end of the connection; S bl,k The second end of the bit line BL <k>Connection; S blb,k The second end of the bit line BLB <k>connect.

[0058] For easy control, S bl,k , S blb,k Connect control signal S0 to achieve synchronous opening or closing.

[0059] 5. SA k For turning on BL <k>、BLB <k>BL <k>、BLB <k>voltage difference.

[0060] See also Figure 4 ,Specifically,SA k Includes: 9 NMOS tubes N k,0 ~N k,8 , 2 PMOS tubes P k,0 ~P k,1 .

[0061] P k,0 , P k,1 The source of is connected to the control signal SAP0;

[0062] N k,0 The source is connected to the control signal SAN0, and the drain is connected to P k,0 The drain and gate are connected to P k,0 The gate of

[0063] N k,1 The source is connected to SAN0, and the drain is connected to P k,1 The drain and gate are connected to P k,1 The gate of

[0064] N k,2 The gate is connected to the control signal OC0, and the drain is connected to P k,0 The gate and source are connected to P k,0 The drain;

[0065] N k,3 The gate is connected to OC0 and the drain is connected to P k,1 The gate and source are connected to P k,1 The drain;

[0066] N k,4 The gate is connected to the control signal ISO0, and the drain (i.e. the first end) is connected to BL <k>, source connected to P k,0 The drain;

[0067] N k,5 The gate is connected to ISO0, and the drain (i.e. the second end) is connected to BLB <k>, source connected to P k,1 The drain;

[0068] N k,6 The gate is connected to the control signal PRE-SA, and the drain is connected to BLB <k>, source connected to BL <k>;

[0069] N k,7 The gate is connected to PRE-SA, the drain is connected to the control signal VEQ, and the source is connected to BL <k>;

[0070] N k,8 The gate is connected to PRE-SA, the drain is connected to VEQ, and the source is connected to BLB <k>.

[0071] 6. PRE k For BL <k>、BLB <k>Precharge.

[0072] See also Figure 1 , S bl,k The second end of the PRE k The output terminal of S blb,k The second end of the PRE k The output terminal two is connected.

[0073] See also Figure 5 ,Specifically,PRE k Includes: 3 NMOS tubes NO k,0 ~NO k,2 .

[0074] NO k,0 The drain (i.e. output terminal 2) is connected to BLB <k>, the source (i.e. output terminal 1) is connected to BL <k>, gate connection control signal PRE0;

[0075] NO k,1 The drain is connected to the control signal VEQ, and the source is connected to BL <k>, the gate is connected to PRE0;

[0076] NO k,2 The drain is connected to VEQ and the source is connected to BLB <k>, gate connected to PRE0.

[0077] The DRAM array circuit for reducing the influence of bit line coupling capacitance based on the above structure divides the bit lines into odd and even rows, first precharges all the bit lines, then performs offset calibration on all the sensitive amplifiers, then turns on the odd row sensitive amplifiers to compare and amplify the odd row bit lines, and stores the odd row results in the cross-coupling structure of the odd row sensitive amplifiers, then disconnects the odd row sensitive amplifiers from the odd row bit lines, performs secondary precharge on the odd row bit lines, then turns on the even row sensitive amplifiers to compare and amplify the even row bit lines, and stores the even row results in the cross-coupling structure of the even row sensitive amplifiers; finally, the results stored in the even row sensitive amplifiers are transferred to the even row bit lines, and the results stored in the odd row sensitive amplifiers are transferred to the odd row bit lines.

[0078] Specifically, this embodiment 1 also simultaneously discloses the parity reading timing control process:

[0079] Taking the mth column in the target array as an example, it will go through ① initial precharge stage, ② offset calibration stage, ③ charge sharing stage, ④ SA k Opening stage, ⑤ Secondary pre-charge stage, ⑥ SA j Open phase for parity read.

[0080] Specific:

[0081] ① Initial pre-charging stage:

[0082] Closed S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 (SA k With BL <k>、BLB <k>is turned on), PRE0 is set to low level (NO k,0 ~NO k,2 Shutdown, PRE k does not work), PRE-SA is set to high level (NO j,6 ~NO j,8 Connect, NO k,6 ~NO k,8 VEQ is set to VDD / 2, ISO0, ISO1, OC0, OC1 are set to high level (NO k,2 ~NO k,5 Connect, NO j,2 ~NO j,5 SAN0, SAN1, SAP0, and SAP1 are set to VDD / 2 to turn BL <1> ~BL <n>、BLB<1>~BLB <n>Both are precharged to VDD / 2 (VEQ is directly connected to BL <1> ~BL <n>、BLB<1>~BLB <n>connected).

[0083] ② Offset calibration stage:

[0084] S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep closed (SA k With BL <k>、BLB <k>is turned on), PRE0 is set to low level (NO k,0 ~NO k,2 Shutdown, PRE k Not working), PRE-SA is set to low level (NO j,6 ~NO j,8 Shutdown, NO k,6 ~NO k,8 Off), ISO0, ISO1 set to low level (NO k,4 ~NO k,5 Shutdown, NO j,4 ~NO j,5 Shutdown), OC0, OC1 set to high level (NO k,2 ~NO k,3 Connect, NO j,2 ~NO j,3 SAN0 and SAN1 are set to low level, and SAP0 and SAP1 are set to high level to eliminate the N Offset voltage in: SA1~SA N The cross coupling in the circuit becomes a state where the two inputs and outputs are short-circuited and independent of each other, thus <1> ~BL <n>、BLB<1>~BLB <n>Pull to their respective flip points to achieve calibrated offset.

[0085] ③ Charge sharing stage:

[0086] S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep closed (SA k With BL <k>、BLB <k>is turned on), PRE0 is set to low level (NO k,0 ~NO k,2 Shutdown, PRE k Not working), PRE-SA is set to low level (NO j,6 ~NO j,8 Shutdown, NO k,6 ~NO k,8 shutdown), ISO0, ISO1, OC0, OC1 are set to low level (NO k,2 ~NO k,5 Shutdown, NO j,2 ~NO j,5 Shutdown), SAN0, SAN1, SAP0, SAP1 set to VDD / 2; WL <m>Set to high level, C o,n,m and bit line BL <n>Charge sharing (if C o,n,m Store "0", then BL <n>To C o,n,m Discharge; if C o,n,m Store "1", then C o,n,m To BL <n>Charging); WLB <1> ~WLB <m>Set low to disable the reference array.

[0087] ④ SA k Start-up phase:

[0088] S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep closed (SA k With BL <k>、BLB <k>is turned on), PRE0 is set to low level (NO k,0 ~NO k,2 Shutdown, PRE k Not working), PRE-SA is set to low level (NO j,6 ~NO j,8 Shutdown, NO k,6 ~NO k,8 Shutdown), ISO1, OC1 set to low level (NO j,2 ~NO j,5 Shutdown), SAN1, SAP1 set to VDD / 2, SA j In the off state; ISO0 is set to high level (NO k,4 ~NO k,5 conduction), OC0 is set to low level (NO k,2 ~NO k,3 Shutdown), SAN0 is set to low level, SAP0 is set to high level, SA k Open;SA k About BL <k>、BLB <k>Comparative amplification is performed to obtain the odd-row amplification results and store them; the even-row still remains in charge sharing.

[0089] ⑤ Secondary pre-charge stage:

[0090] Disconnect S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 (SA k With BL <k>、BLB <k>disconnect); PRE0 is set to high level (NO k,0 ~NO k,2 Conductivity, PRE k work), the BL <k>、BLB <k>Precharge to VDD / 2 to reduce the effect of coupling capacitance on even-row charge sharing: Even-row charge sharing will cause BL <j>、BLB <j>The voltage of BL changes by <k>、BLB <k>Precharge to VDD / 2 to reduce the voltage difference between adjacent bit lines, thereby avoiding the coupling capacitor to transmit voltage fluctuations to reduce the impact.

[0091] ⑥ SA j Start-up phase:

[0092] S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep disconnected (SA k With BL <k>、BLB <k>disconnected), ISO1 is set to high level (NO j,4 ~NO j,5 conduction), OC1 is set to low level (NO j,2 ~NO j,3 Shutdown), SAN1 is set to low level, SAP1 is set to high level, SA j Open;SA j About BL <j>、BLB <j>Compare and amplify to obtain the even-row amplification result and store it, SA j The even-row amplification result stored in is passed to BL <j>、BLB <j>; Close S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 (SA k With BL <k>、BLB <k>is turned on), PRE0 is set to low level (NO k,0 ~NO k,2 Shutdown, PRE k Not working), SA k The odd row amplification results stored in are passed to BL <k>、BLB <k>.

[0093] BL can be used later <k>、BLB <k>、BL <j>、BLB <j>The voltage is analyzed to locate the value stored in a certain DRAM target storage cell. For example, a value to be output is selected by a multiplexer using a column address to complete reading of a specific DRAM target storage cell.

[0094] Example 2

[0095] The second embodiment is intended to perform simulation verification on the first embodiment.

[0096] Since the coupling capacitance has the greatest influence on the reading of opposite values ​​of adjacent bit lines, the case where odd rows in the target array store "1" and even rows store "0" is taken, and the conventional DRAM array reading is introduced for comparison with Example 1 (both columns in the target array are turned on). The comparison results are shown in FIG. Figure 6 .

[0097] Among them, in the circuit basis 3 of embodiment 1, S is removed bl,k , S blb,k 、PRE k , S.A. j ,SA k When turned on at the same time, a DRAM array circuit corresponding to a conventional DRAM array reading is obtained.

[0098] 1. Look first Figure 6 Part (a) shows the waveform of a traditional DRAM array read:

[0099] Ⅰ: Precharge stage: PRE-SA is set to high level, VEQ is set to VDD / 2, ISO0, ISO1, OC0, OC1 are set to high level, SAN0, SAN1, SAP0, SAP1 are set to VDD / 2, so as to set BL <1> ~BL <n>、BLB<1>~BLB <n>Both are precharged to VDD / 2.

[0100] Ⅱ: Offset calibration stage: PRE-SA is set to low level, ISO0 and ISO1 are set to low level, OC0 and OC1 are set to high level, SAN0 and SAN1 are set to low level, SAP0 and SAP1 are set to high level to eliminate SA1~SA N The offset voltage in

[0101] III: Charge sharing stage: PRE-SA is set to low level, ISO0, ISO1, OC0, OC1 are set to low level, SAN0, SAN1, SAP0, SAP1 are set to VDD / 2; WL <m>Set to high level, C o,n,m and bit line BL <n>Charge sharing; WLB <1> ~WLB <m>Set low to disable the reference array.

[0102] IV: Sensing amplification stage: ISO0 and ISO1 are set to high level, OC0 and OC1 are set to low level, SAN0 and SAN1 are set to low level, SAP0 and SAP1 are set to high level, then SA k ,SA j Open at the same time;

[0103] SA k About BL <k>、BLB <k>Compare and amplify to obtain the odd-row amplification results and store them, SA k The odd row amplification results stored in are passed to BL <k>、BLB <k>;SA j About BL <j>、BLB <j>Compare and amplify to obtain the even-row amplification result and store it, SA j The even-row amplification result stored in is passed to BL <j>、BLB <j>.

[0104] like Figure 6 As shown in part (a) of the figure, due to the influence of the coupling capacitor, the amount of charge shared to the bit line in the charge sharing stage is reduced, resulting in a decrease in the subsequent sensing amplification stage SA k ,SA j Failed to zoom in correctly, resulting in read errors:

[0105] In the latter part of the sensing amplification stage, BL <j>Displayed as low level, BLB <j>Displayed as high level, but actually BL <j>Should be high level, BLB <j>Should be low level; BL <k>Displayed as high level, BLB <k>Displayed as low level, but actually BL <k>Should be low level, BLB <k>Should be high.

[0106] (II) Look Again Figure 6 Part (b) of the figure shows the waveform diagram of the DRAM array circuit for reducing the influence of the bit line coupling capacitance of Example 1 when reading, which is consistent with the 6 stages described in Example 1. Figure 6 From part (b) of the above, we can see that in SA j In the opening phase, SA k ,SA j Both are correctly amplified and read correctly:

[0107] in SA j In the latter part of the opening phase, BL <j>Displayed as high level, BLB <j>Displayed as low level, but in fact BL <j>Should be high level, BLB <j>Should be low level; BL <k>Displayed as low level, BLB <k>Displayed as high level, but in fact BL <k>Should be low level, BLB <k>Should be high.

[0108] In summary, the effectiveness and accuracy of Example 1 are verified.

[0109] Example 3

[0110] This embodiment 3 discloses a DRAM array module that reduces the influence of bit line coupling capacitance, which adopts the layout of a DRAM array circuit that reduces the influence of bit line coupling capacitance as disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0111] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.< / k> < / k> < / k> < / k> < / j> < / j> < / j> < / j> < / k> < / k> < / k> < / k> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / k> < / k> < / k> < / k> < / m> < / n> < / m> < / n> < / n> < / j> < / j> < / k> < / k> < / k> < / k> < / k> < / k> < / j> < / j> < / j> < / j> < / k> < / k> < / k> < / k> < / j> < / j> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / m> < / n> < / n> < / n> < / m> < / k> < / k> < / n> < / n> < / k> < / k> < / n> < / n> < / n> < / n> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / m> < / n> < / n> < / m> < / n>

Claims

1. A DRAM array circuit for reducing the influence of bit line coupling capacitance, comprising: array, reference array; The target array includes DRAM target storage cells distributed in N rows and M columns; N is an even number; In the target array, the nth row shares the bit line BL <n>, the mth column common word line WL <m>, bit line BL BL<p+1> There is a coupling capacitor C c1,p ; n∈[1,N], m∈[1,M]; p∈[1,N-1]; < / m> < / n> The reference array includes DRAM reference storage cells distributed in N rows and M columns; In the reference array, the nth row shares the bit line BLB <n>, the mth column common word line WLB <m>,BLB ,BLB<p+1> There is a coupling capacitor C c2,p ; < / m> < / n> It is characterized in that it also includes: an even-row sensitive amplifier SA j , odd-line sensitive amplifier SA k 、Odd row pre-charge circuit PRE k , odd switch S bl,k , odd switch S blb,k ; Where k represents an odd number, k∈[1,3,…,N-1]; j represents an even number, j∈[2,4,…,N]; SA j BL <j>、BLB <j>Connection for amplifying bit line BL <j>、BLB <j> The voltage difference;< / j> < / j> < / j> < / j> S bl,k For controlling BL <k>with SA k On or off; S blb,k For controlling BLB <k>with SA k On or off; SA k For turning on BL <k>、BLB <k>BL <k>、BLB <k> The voltage difference;< / k> < / k> < / k> < / k> < / k> < / k> PRE k For BL <k>、BLB <k> Precharge.< / k> < / k> 2. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 1, characterized in that: SA j The first end of the bit line BL <j>Connect, the second end and the bit line BLB <j> connect;< / j> < / j> SA k The first end and S bl,k The first end is connected to S blb,k A first end is connected; S bl,k The second end of the bit line BL <k>、PRE k The output terminal of is connected;< / k> S blb,k The second end of the bit line BLB <k>、PRE k The output terminal two is connected.< / k> 3. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 1, characterized in that: In the target array, BL <n>There is a parasitic capacitance C between the ground VSS bl,n ;< / n> In the reference array, BLB <n>There is a parasitic capacitance C between the ground VSS blb,n .< / n> 4. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 1, characterized in that: S bl,k , S blb,k Connect control signal S0.

5. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to any one of claims 1 to 4, characterized in that: In the target array, the DRAM target storage unit in the nth row and the mth column includes: 1 MOS tube N o,n,m , 1 storage capacitor C o,n,m ; N o,n,m The drain and bit line BL <n>connected, the gate is connected to the word line WL <m>connected, source and C o,n,m One end of C o,n,m The other end is grounded to VSS;< / m> < / n> In the reference array, the DRAM reference storage unit in the nth row and the mth column includes: 1 MOS tube N r,n,m , 1 storage capacitor C r,n,m ; N r,n,m The drain and bit line BLB <n>connected, gate and word line WLB <m>connected, source and C r,n,m One end of C r,n,m The other end is grounded to VSS.< / m> < / n> 6. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 5, characterized in that: PRE k Includes: 3 NMOS tubes NO k,0 ~NO k,2 ; NO k,0 The drain of BLB is connected <k>, source connected to BL <k> , gate connection control signal PRE0;< / k> < / k> NO k,1 The drain is connected to the control signal VEQ, and the source is connected to BL <k> , the gate is connected to PRE0;< / k> NO k,2 The drain is connected to VEQ and the source is connected to BLB <k> , gate connected to PRE0.< / k> 7. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 6, characterized in that: SA j Includes: 9 NMOS tubes N j,0 ~N j,8 , 2 PMOS tubes P j,0 ~P j,1 ; P j,0 , P j,1 The source is connected to a control signal SAP1; N j,0 The source is connected to the control signal SAN1, and the drain is connected to P j,0 The drain and gate are connected to P j,0 The gate of N j,1 The source is connected to SAN1, and the drain is connected to P j,1 The drain and gate are connected to P j,1 The gate of N j,2 The gate is connected to the control signal OC1, and the drain is connected to P j,0 The gate and source are connected to P j,0 The drain; N j,3 The gate is connected to OC1 and the drain is connected to P j,1 The gate and source are connected to P j,1 The drain; N j,4 The gate is connected to the control signal ISO1, and the drain is connected to BL <j>, source connected to P j,0 The drain;< / j> N j,5 The gate is connected to ISO1 and the drain is connected to BLB <j>, source connected to P j,1 The drain;< / j> N j,6 The gate is connected to the control signal PRE-SA, and the drain is connected to BLB <j>, source connected to BL <j> ；< / j> < / j> N j,7 The gate is connected to PRE-SA, the drain is connected to the control signal VEQ, and the source is connected to BL <j> ；< / j> N j,8 The gate is connected to PRE-SA, the drain is connected to VEQ, and the source is connected to BLB <j> ；< / j> SA k Includes: 9 NMOS tubes N k,0 ~N k,8 , 2 PMOS tubes P k,0 ~P k,1 ; P k,0 , P k,1 The source of is connected to the control signal SAP0; N k,0 The source is connected to the control signal SAN0, and the drain is connected to P k,0 The drain and gate are connected to P k,0 The gate of N k,1 The source is connected to SAN0, and the drain is connected to P k,1 The drain and gate are connected to P k,1 The gate of N k,2 The gate is connected to the control signal OC0, and the drain is connected to P k,0 The gate and source are connected to P k,0 The drain; N k,3 The gate is connected to OC0 and the drain is connected to P k,1 The gate and source are connected to P k,1 The drain; N k,4 The gate is connected to the control signal ISO0, and the drain is connected to BL <k>, source connected to P k,0 The drain;< / k> N k,5 The gate is connected to ISO0 and the drain is connected to BLB <k>, source connected to P k,1 The drain;< / k> N k,6 The gate is connected to the control signal PRE-SA, and the drain is connected to BLB <k>, source connected to BL <k> ；< / k> < / k> N k,7 The gate is connected to PRE-SA, the drain is connected to the control signal VEQ, and the source is connected to BL <k> ；< / k> N k,8 The gate is connected to PRE-SA, the drain is connected to VEQ, and the source is connected to BLB <k> 。< / k> 8. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 7, characterized in that: When the mth column in the target array is turned on, it goes through the initial precharge phase, offset calibration phase, charge sharing phase, SA k Start-up phase, secondary pre-charge phase, SA j Open phase for parity read.

9. A DRAM array circuit for reducing the influence of bit line coupling capacitance according to claim 8, characterized in that: During the initial pre-charge phase: Closed S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 , PRE0 is set to low level, PRE-SA is set to high level, VEQ is set to VDD / 2, ISO0, ISO1, OC0, OC1 are set to high level, SAN0, SAN1, SAP0, SAP1 are set to VDD / 2, so as to set BL <1> ~BL <n>、BLB<1>~BLB <n> All are precharged to VDD / 2;< / n> < / n> During the offset calibration phase: S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep closed, set PRE0 to low level, set PRE-SA to low level, set ISO0 and ISO1 to low level, set OC0 and OC1 to high level, set SAN0 and SAN1 to low level, and set SAP0 and SAP1 to high level to eliminate SA1~SA N The offset voltage in During the charge sharing phase: S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep closed, PRE0 is set to low level, PRE-SA is set to low level, ISO0, ISO1, OC0, OC1 are set to low level, SAN0, SAN1, SAP0, SAP1 are set to VDD / 2; WL <m>Set to high level, C o,n,m and bit line BL <n>Charge sharing; WLB <1> ~WLB <m> Set to low level and do not turn on the reference array;< / m> < / n> < / m> in SA k Start-up phase: S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep closed, PRE0 is set to low level, PRE-SA is set to low level, ISO1 and OC1 are set to low level, SAN1 and SAP1 are set to VDD / 2, SA j In the off state; ISO0 is set to high level, OC0 is set to low level, SAN0 is set to low level, SAP0 is set to high level, SA k Open;SA k About BL <k>、BLB <k> Compare and amplify to obtain the odd-row amplification result and store it; the even-row is still in charge sharing;< / k> < / k> In the secondary pre-charge stage: Disconnect S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 ; Set PRE0 to high level, and BL <k>、BLB <k> Precharge to VDD / 2 to reduce the effect of coupling capacitance on dual row charge sharing;< / k> < / k> in SA j Start-up phase: S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 Keep disconnected, ISO1 is set to high level, OC1 is set to low level, SAN1 is set to low level, SAP1 is set to high level, SA j Open;SA j About BL <j>、BLB <j>Compare and amplify to obtain the even-row amplification result and store it, SA j The even-row amplification result stored in is passed to BL <j>、BLB <j>; Close S bl,1 ~S bl,N-1 , S blb,1 ~S blb,N-1 , PRE0 is set to low level, SA k The odd row amplification results stored in are passed to BL <k>、BLB <k> 。< / k> < / k> < / j> < / j> < / j> < / j> 10. A DRAM array module for reducing the influence of bit line coupling capacitance, characterized in that: The invention adopts a layout of a DRAM array circuit for reducing the influence of bit line coupling capacitance as claimed in any one of claims 1 to 9.

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