Chip manufacturing method, chip splice plate, chip strip, chip and consumable

Abstract

The invention relates to a chip manufacturing method, a chip splice plate, a chip strip, a chip and a consumable. The chip manufacturing method comprises the steps that a plurality of peripheral elements are attached to one side of a circuit board, the peripheral elements are electrically connected with a circuit pattern layer of the circuit board, the circuit board comprises a substrate, the circuit pattern layer and a contact layer, the circuit pattern layer and the contact layer are located on the two sides of the substrate respectively, and the circuit pattern layer is electrically connected with the contact layer; the peripheral element is positioned on one side, provided with the circuit pattern layer, of the substrate; arranging a plurality of wafers on one side of the circuit board, wherein at least one wafer and at least one peripheral element which correspond to each other are located in the same chip area in the circuit board; a binding line is formed, and the corresponding wafer is electrically connected with the circuit pattern layer through the binding line; forming an encapsulation layer covering the plurality of wafers and the plurality of peripheral elements; and any two adjacent chip areas of the circuit board are cut. According to the method, the stability of the circuit board can be well ensured, and the risk that the binding wire is damaged is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a chip manufacturing method, a chip splicing board, a chip bar, a chip and consumables. Background Art

[0002] With the development and progress of society, people's pursuit of quality life is also constantly improving. Printers have become an indispensable tool and assistant in daily life and work. People use printers to print important documents, materials, reports or wonderful moments into text or pictures for recording, storage or other purposes.

[0003] The printer consists of a host and printing consumables. The host is responsible for information processing, communication, and issuing printing instructions; the printing consumables are composed of chips (ICs) and ink cartridges / toner cartridges. The chip is used to communicate with the printer and record information such as printing data, and the ink cartridges / toner cartridges are used to store ink / toner. Usually, the manufactured chips are packaged to protect the core circuit structure. The packaging process includes COB (chip on board) process.

[0004] In the COB process, in order to improve production efficiency, manufacturers rarely use a single chip when designing PCB boards, but use a continuous sheet form, in which the double-sided V-cut process is used between the sheets. This process is conducive to the end customer to manually break off the chips one by one before installation. In addition, in order to meet the functional requirements and actual needs of printing consumables chips, many chips are equipped with peripheral components. Such peripheral components are of standard size, such as resistors, capacitors, diodes, etc., and need to be installed on the PCB board through the SMT process. The SMT process includes a reflow soldering step, and the reflow soldering equipment is a welding furnace with a high-temperature heating function. The furnace is set with a corresponding heating curve (commonly known as the furnace temperature curve) according to the characteristics of the solder (generally referring to solder paste). When the chip passes through the track of the reflow soldering equipment, it will automatically heat up, and the solder completes the welding of the peripheral components and the PCB board through this process to achieve electrical connection. However, since most PCB boards are made of epoxy resin, the most common ones are FR-4, CEM-3, etc., and the PCB boards with a connected design use a double-sided V-cut process between the sheets, the connected PCB boards will undergo a certain curvature deformation during reflow soldering, becoming concave or arched.

[0005] After the SMT production is completed, the printing consumables chip with PCB as the carrier flows into the COB process. The COB process requires that the PCB surface is on the same horizontal plane during the production process, otherwise the production will not be possible. If the PCB has been deformed into an arch or concave shape at this time, in order to solve this problem, general manufacturers will flatten the PCB on the COB production equipment in the following ways: use a pressure cover to flatten the deformed PCB; use the negative pressure of vacuum suction to flatten the deformed PCB. Since the COB process includes many independently set equipment such as die bonding, wire bonding and glue dispensing, the chip will go through the following process in the step of transferring from the wire bonding equipment to the glue dispensing equipment: PCB deformation-PCB flattening-PCB deformation. This process will cause slight pulling on the bonded wires, such as arching up, concave down, etc. This pulling will cause hidden dangers to the bond wires, causing changes in the bond wire tension, and in severe cases, it will cause the bond wire solder joints to fall off. Summary of the invention

[0006] Based on this, it is necessary to provide a chip manufacturing method, chip splicing board, chip strip, chip and consumables to address the problem of deformation of the entire board during chip production.

[0007] The disclosed embodiment provides a chip manufacturing method, which includes: mounting a plurality of peripheral components on one side of a circuit board, and electrically connecting the peripheral components to a circuit graphic layer of the circuit board, wherein the circuit board includes a substrate and a circuit graphic layer and a contact layer respectively located on both sides of the substrate, the circuit graphic layer and the contact layer are electrically connected, and the peripheral components are located on the side of the substrate where the circuit graphic layer is provided; arranging a plurality of chips on one side of the circuit board, wherein at least one corresponding chip and at least one peripheral component are both located in the same chip area of ​​the circuit board; forming binding wires, wherein the binding wires electrically connect the corresponding chips to the circuit graphic layer; forming a packaging layer covering the plurality of chips and the plurality of peripheral components; and cutting between any two adjacent chip areas of the circuit board.

[0008] The chip manufacturing method provided in the embodiment of the present disclosure can better ensure the stability of the circuit board and reduce the risk of damage to the binding wire. By forming the packaging layer and cutting, the chip can be well formed and the chip can be separated. The process route of the method provided by the present disclosure is simple, the overall packaging process has a good response speed, and the construction period can be short.

[0009] In addition, the method provided by the present disclosure has low cost, simplified process route and can separate multiple chips of standard size. The chip manufactured by the method provided by the present disclosure has high reliability, good working performance and is easy to use.

[0010] In some embodiments, the cutting step includes: forming a first cutting opening that cuts off the encapsulation layer and extends into the substrate; and forming a second cutting opening that extends into the substrate, with a residual portion based on the substrate between the second cutting opening and the first cutting opening.

[0011] With such an arrangement, the connection between two adjacent chip regions can be maintained, the connection strength can be ensured based on the residual portion of the substrate, and the two chip regions can be easily separated at the residual portion.

[0012] In some embodiments, the thinnest dimension of the residual portion is 0.2 mm to 0.3 mm.

[0013] Such an arrangement can easily separate adjacent chip areas by hand while ensuring the connection strength.

[0014] In some embodiments, the chip manufacturing method further includes: forming a circuit board, the step of forming the circuit board including: forming a cutting mark line for dividing the chip area; forming a mounting mark for marking one side of the circuit board; and forming a positioning mark for positioning the circuit board.

[0015] With such a configuration, the chip manufacturing method provided by the embodiment of the present disclosure can be implemented more accurately and conveniently, and is helpful in preventing errors and facilitating a good cutting process to separate chips of better quality.

[0016] In some embodiments, the circuit board includes a plurality of chip areas in an array, and auxiliary fixing areas located at both ends of any column of chip areas; the method also includes: forming a circuit board, the step of forming the circuit board includes: forming auxiliary fixing holes located in the auxiliary fixing areas; the step of cutting includes: forming a plurality of chip strips, each chip strip includes a column of chip areas.

[0017] By providing auxiliary positioning holes, each chip strip can be fixed when the chip strips are divided, thereby ensuring cutting accuracy.

[0018] In some embodiments, the chip manufacturing method further includes: polishing the packaging layer so that the end surface of the packaging layer facing away from the circuit board is formed into a flat surface.

[0019] In this way, the encapsulation layer can be polished to a desired thickness and can be polished as a whole, with high production efficiency and good dimensional consistency. In addition, the encapsulation layer polished to a flat surface can be used as a mounting surface for the manufactured chip, which helps to achieve stable matching.

[0020] In some embodiments, the binding wire is an aluminum wire, the material of the packaging layer includes epoxy resin, and the circuit board is a printed circuit board.

[0021] With such an arrangement, a chip with excellent performance can be realized at a relatively low cost, and the execution process of the method is reliable.

[0022] On the other hand, the embodiment of the present disclosure provides a chip splicing board, which includes: a circuit board, including a substrate and a circuit graphic layer and a contact layer respectively located on both sides of the substrate, the circuit graphic layer being electrically connected to the contact layer; a plurality of chips located on a side of the substrate provided with the circuit graphic layer; a plurality of binding wires, each chip being electrically connected to the circuit graphic layer through the binding wires; a plurality of peripheral components located on one side of the substrate and electrically connected to the circuit graphic layer, wherein at least one corresponding peripheral component and at least one chip are located in the same chip area of ​​the circuit board; and a packaging layer covering the plurality of chips, the plurality of binding wires and the plurality of peripheral components; wherein the chip splicing board can be formed according to the steps of the aforementioned chip manufacturing method.

[0023] The chip splicing board provided by the embodiment of the present disclosure has good structural strength, high reliability of the binding wire, and can ensure the processing quality and performance of each chip. The chip splicing board has good processing performance and usage performance.

[0024] Exemplarily, the packaging layer has a plurality of discrete packaging parts, each of which is located in a corresponding chip region.

[0025] The chip splicing plate has good processing performance and usage performance and is easy to separate different chips.

[0026] The disclosed embodiment also provides a chip bar, which includes: a strip circuit board, including a base strip and a circuit pattern strip and a contact strip respectively located on both sides of the base strip, the circuit pattern strip and the contact strip being electrically connected, and the strip circuit board having a plurality of chip areas arranged in a row; a plurality of chips located on a side of the base strip provided with the circuit pattern strip; a plurality of binding wires, each chip being electrically connected to the circuit pattern strip through a binding wire; a plurality of peripheral components located on one side of the base strip and electrically connected to the circuit pattern strip, wherein at least one corresponding peripheral component and at least one chip are both located in the same chip area of ​​the strip circuit board; and a packaging strip, wherein the packaging strip has a plurality of discrete packaging parts, each packaging part being located in a corresponding chip area and covering at least one corresponding peripheral component, binding wire and at least one chip, wherein the chip bar can be formed according to the steps of the aforementioned chip manufacturing method, the chip bar having a first cutting opening separating the packaging parts, and the first cutting opening extending into the base strip.

[0027] The chip bar provided by the embodiment of the present disclosure is easy to transport, store, use, and separate the chips. In addition, the reliability of the binding wires in the chip bar is high, which can ensure the processing quality and performance of each chip.

[0028] The disclosed embodiment also provides a chip, which includes: a chip circuit board, including chip contacts, a chip substrate and a chip circuit stacked in sequence, the chip circuit being electrically connected to the chip contacts; a chip, located on a side of the chip substrate where the chip circuit is provided; binding wires, the chip being electrically connected to the chip circuit through the binding wires; peripheral components, located on one side of the chip substrate and electrically connected to the chip circuit; and a packaging part, covering the chip, the binding wires and the peripheral components; wherein the chip can be formed according to the steps of the aforementioned chip manufacturing method.

[0029] The chip binding wires provided by the embodiments of the present disclosure have high reliability, good electrical performance and usability, and low cost.

[0030] Exemplarily, the packaging portion and the substrate have a same cutting surface, and the substrate includes a residual portion at the cutting surface.

[0031] The embodiment of the present disclosure provides a consumable, which may include a box body; and the aforementioned chip installed in the box body.

[0032] The consumables provided in the embodiments of the present disclosure are manufactured as a whole locally, and the chip can be installed in the box body relatively stably and accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic flowchart of a chip manufacturing method provided in an embodiment of the present disclosure;

[0034] Figure 2 A schematic top view of a circuit board provided for an embodiment of the present disclosure;

[0035] Figure 3 for Figure 1 The enlarged view of point A in the middle;

[0036] Figure 4 A schematic bottom view of a circuit board provided for an embodiment of the present disclosure;

[0037] Figure 5 A schematic cross-sectional view of a chip splicing board provided for an embodiment of the present disclosure;

[0038] Figure 6 A schematic cross-sectional view of a polished chip splicing plate provided for an embodiment of the present disclosure;

[0039] Figure 7 A schematic diagram of the structure of a chip bar provided in an embodiment of the present disclosure;

[0040] Figure 8 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure;

[0041] Fig. 9A schematic block diagram of a printing system provided in accordance with an embodiment of the present disclosure.

[0042] Description of reference numerals: 1, substrate; 11, first base strip; 100, chip substrate; 111, first chip substrate; 1101, residual portion; 1001, mounting mark area;

[0043] 2. Circuit pattern layer; 21. First circuit pattern strip; 211. First chip circuit; 3. First ink layer;

[0044] 4. contact layer; 41. first contact strip; 400. chip contact; 411. first chip contact; 4004. auxiliary mark;

[0045] 5. Wafer; 6. Peripheral components; 7. Binding wire; 8. Packaging layer; 81. First packaging strip; 800. Packaging part; 811. First packaging part; 901. First cutting opening; 902. Second cutting opening;

[0046] 2000, circuit board; 2010, first strip circuit board; 2001, positioning mark; 2002, auxiliary fixing hole; 2003, cutting mark line; 2004, mounting mark; 3000, chip splicing board; 4000, chip strip; 5000, chip; 5011, first chip; 5012, second chip; 5013, third chip; 6000, box body; 7000, consumables; 8000, printer. DETAILED DESCRIPTION

[0047] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the specific implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure. However, the embodiments of the present disclosure can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the embodiments of the present disclosure, so the embodiments of the present disclosure are not limited by the specific examples of the embodiments disclosed below.

[0048] In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.

[0049] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0050] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. Exemplarily, the first chip may also be referred to as the second chip, and the second chip may also be referred to as the first chip. In the description of the embodiments of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0051] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or directly connected with the presence of an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. The terms "installed", "set", "fixed", etc. can be broadly understood as connection. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0052] As used herein, the terms "layer" and "region" refer to a portion of a material including an area having a certain thickness. A layer can extend horizontally, vertically and / or along a tapered surface. A layer can be an area of ​​a uniform or non-uniform continuous structure, and its thickness perpendicular to the extension direction may not be greater than the thickness of the continuous structure. A layer can include multiple layers. The shapes of various areas and layers in the drawings and their relative sizes and positional relationships are only exemplary, and may actually deviate due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.

[0053] See also Figure 1 , Figure 1The flowchart of the chip manufacturing method in the embodiment of the present disclosure is shown. The embodiment of the present disclosure provides a chip manufacturing method 1000, and the chip manufacturing method 1000 may include steps S101 to S105.

[0054] In an exemplary embodiment, the chip manufacturing method 1000 may include the step of forming a circuit board. Figures 2 to 4 As shown, Figure 2 The front side of the circuit board in the embodiment of the present disclosure is shown. Figure 3 yes Figure 2 A partial enlarged view of Figure 4 The back side of the circuit board is shown. Exemplarily, the circuit board 2000 may include a substrate 1 and a circuit pattern layer 2 and a contact layer 4 respectively located on both sides of the substrate 1. The circuit pattern layer 2 is electrically connected to the contact layer 4, and the substrate 1 may include a conductive path.

[0055] Exemplarily, the contact layer 4, the substrate 1 and the circuit pattern layer 2 are stacked in sequence along the Z-axis direction. The circuit board 2000 may have an auxiliary area and a plurality of chip areas divided in the XY plane. The circuit pattern layer 2 may include a plurality of groups of circuit patterns, each group of circuit patterns being located in a corresponding chip area; the contact layer 4 may include a plurality of groups of contacts, each group of contacts being located in a corresponding chip area. The corresponding circuit patterns and contacts are electrically connected.

[0056] Step S101 includes: mounting a plurality of peripheral components on one side of the circuit board, and electrically connecting the peripheral components to the circuit pattern layer of the circuit board. Figure 5 As shown, Figure 5 Shows Figure 3 Schematic cross-sectional view at AA in FIG. By way of example, the peripheral component 6 is located on the side of the substrate 1 provided with the circuit pattern layer 2. The peripheral component 6 can be soldered to the corresponding position in the circuit pattern layer 2 by a process such as reflow soldering.

[0057] Step S102 includes: arranging a plurality of chips on one side of the circuit board. Exemplarily, the chip 5 is located on the side of the substrate 1 where the circuit pattern layer 2 is provided. At least one chip 5 can be provided in each chip area. Exemplarily, different chips 5 or different numbers of chips 5 can be provided in different chip areas. The chip 5 can be at least partially stacked on the circuit pattern layer 2, and can also be at least partially stacked outside the circuit pattern layer 2 body on the substrate 1. Exemplarily, the corresponding at least one chip 5 and at least one peripheral component 6 are both located in the same chip area in the circuit board 2000.

[0058] Step S103 includes: forming a binding wire. Exemplarily, the binding wire 7 electrically connects the corresponding chip 5 with the circuit pattern layer 2. Exemplarily, each binding wire 7 is located in a corresponding chip region.

[0059] Step S104 includes: forming a packaging layer covering multiple chips, bonding wires and multiple peripheral components. Figure 5 , forming an integrated packaging layer 8, the packaging layer 8 can cover the entire chip area, but may not completely cover the auxiliary area. The circuit board 2000 has a first chip area C11, a second chip area C12, and a third chip area C13 arranged several times along the Y-axis direction. Exemplarily, the first chip area C11 has a first chip contact 411, a first chip substrate 111, and a first chip circuit 211 stacked in sequence, and also has a chip 5, a peripheral component 6, a binding wire 7, and a first packaging part 811. The structure in the first chip area C11 can also be called a first chip 5011. The structure in the second chip area C12 can be called a second chip 5012, and the structure in the third chip area C13 can be called a third chip 5013.

[0060] In an exemplary embodiment, the chip manufacturing method 1000 further includes: polishing the packaging layer, which helps to flatten and correct the packaging layer 8 and reduce the thickness of the packaging layer 8 .

[0061] Step S105 includes: cutting between any two adjacent chip regions of the circuit board. Figure 2 and Figure 4 The circuit board 2000 can be cut or grooved. For example, when cutting along the X-axis direction, a groove can be cut between two adjacent chip areas. For example, when cutting along the Y-axis direction, the chip strips 4000 can be cut between two adjacent chips.

[0062] In the chip manufacturing method 1000 provided in the embodiment of the present disclosure, the circuit board 2000 can be designed in an integrated compact manner. Compared with the traditional binding process in which a continuous gap is set between two strip circuit boards in order to prefabricate chip strips, the continuous gap between each strip circuit board in the present disclosure is eliminated, thereby reducing the area of ​​the circuit board 2000 or improving the space efficiency of the circuit board 2000, thereby reducing costs.

[0063] The process steps of this method are coherent and concise. The circuit board 2000 is used as the carrier of the packaging layer 8. Compared with the IC packaging process of first packaging the bare chip and then soldering it to the PCB board through SMT technology, the structure is simplified, and a series of IC packaging processes are saved, which reduces the problem of warping and deformation of the circuit board 2000 caused by complicated processes. In addition, compared with the method of connecting the contacts on the bare chip to the pins of the packaging shell with wires, and these pins are connected to other devices through wires on the printed circuit board, the present invention can reduce the manufacturing cost. This is mainly because the complex circuit structure of the IC process requires the use of precious metal wires such as gold wires or alloy wires as wires to ensure the signal transmission effect and the structural design is complex, while the simple circuit structure formed by the present invention can use ordinary metal wires.

[0064] The chip manufacturing method 1000 provided in the embodiment of the present disclosure can cut the circuit board 2000 by cutting the packaging layer 8, which can eliminate the double-sided V-shaped cut design of the traditional circuit board, improve the strength of the circuit board 2000, and reduce the process cost.

[0065] The chip manufacturing method provided by the embodiments of the present disclosure has high production efficiency and good overall benefits.

[0066] In an exemplary embodiment, the steps of forming the circuit board 2000 include: forming a cutting mark line 2003 for dividing the chip area; forming a mounting mark 2004 for marking one side of the circuit board 2000; and forming a positioning mark 2001 for positioning the circuit board 2000. Such a configuration is helpful for the subsequent processing and use of the circuit board 2000, and the circuit board 2000 is easy to be manufactured. A cutting mark line 2003 can be set at the boundary of each chip area. Exemplarily, an auxiliary mark 4004 can be set on the other side of the circuit board 2000, that is, the side where the contact layer 4 is located. The style of the auxiliary mark 4004 can be the same as the style of the mounting mark 2004, and the layout of the auxiliary mark 4004 relative to the substrate 1 can be different from the layout of the mounting mark 2004.

[0067] refer to Figure 2 , Figure 3 and Figure 4 , the circuit board 2000 may include a first ink layer 3 and a second ink layer. The first ink layer 3 may be formed by, for example, a screen printing process, and may cover a portion of the circuit pattern layer 2 and may expose a pre-designed area. The second ink layer may cover a portion of the contact layer 4 and expose a pre-designed area. The positioning mark 2001 and the cutting mark line 2003 may be an exposed area of ​​the first ink layer 3, or may be an exposed area processed later. The mounting mark 2004 may be a separate portion of the circuit pattern layer 2, such as a circle; and a portion of the first ink layer 3 is removed around the mounting mark 2004 to expose a portion of the substrate 1 as a mounting mark area 1001, and the mounting mark area 1001 may be a ring. Exemplarily, the circuit board 2000 may be a printed circuit board, the material of the circuit pattern layer 2 may include copper, and the first ink layer 3 may be a solder resist ink layer.

[0068] Positioning marks 2001 may be provided at the edges and corners of the circuit board 2000 to ensure positioning accuracy, and the positioning marks 2001 may be in the shape of a cross. The centers of the plurality of positioning marks 2001 may be on the same straight line. The layout of the mounting marks 2004 on the front of the circuit board 2000 is different from the layout of the mounting marks 2004 on the back, and the circuit board 2000 can identify the front and back. Exemplarily, the width of the cutting mark line 2003 may be the same as the thickness of the cutting knife to be used to ensure that the cutting position and the cutting width are accurate, and also help avoid losses during cutting. In the embodiments of the present disclosure, an optical recognition and positioning device may be used to realize the identification and positioning of the circuit board 2000, and other devices such as devices with positioning pins may also be used.

[0069] The circuit board 2000 includes a plurality of chip areas in an array, and auxiliary fixing areas B1 located at both ends of any column of chip areas. Figure 2 , the chip regions arranged along the Y-axis direction may be referred to as a column of chip regions. For example, each chip region may be rectangular, such as a rectangle or a square. Figure 4 For example, the circuit board 2000 may have a label area B2, which can be used to mark and read the label information of the circuit board 2000 to ensure accurate material collection and traceability of the production process.

[0070] Exemplarily, the step of forming the circuit board 2000 may include: forming the auxiliary fixing hole 2002 located in the auxiliary fixing area B1. Figure 2 and Figure 4 As shown, the auxiliary fixing hole 2002 may penetrate the body of the circuit board 2000. In the embodiment of the present disclosure, the step of cutting may include: forming a plurality of chip strips 4000, each chip strip 4000 including a row of chip areas. The center of each installed chip may be located on the same straight line as the center point of the auxiliary fixing hole 2002. Figure 2 , Figure 3 and Figure 5 As shown, the chip strip 4000 may be a first chip strip, and may include, for example, ten chip regions. Auxiliary fixing holes 2002 may be provided at both ends of each column of chip regions, which may fix the chip splicing board 3000 when forming the chip splicing board 3000, and may fix the corresponding chip strip 4000 when cutting the chip strip 4000. Exemplarily, the step of forming the chip strip 4000 may include cutting off the auxiliary fixing region B1.

[0071] After the encapsulation layer 8 is formed, it can be considered that the chip splicing board 3000 is obtained. If there is a subsequent process, the chip splicing board 3000 of the previous step can be called a prefabricated chip splicing board in each step. Exemplarily, there is only a cutting opening between two adjacent chip areas. The chip splicing board 3000 formed by the method provided in the embodiment of the present disclosure may include densely distributed chips 5000, the chip splicing board 3000 has little deformation, and the performance of the chips 5000 is reliable.

[0072] Exemplarily, before forming the encapsulation layer 8 and after forming the bonding wires 7, the formed integrated circuit can be tested, and then defective products can be repaired. Exemplarily, the peripheral components 6 are mounted first, and then the wafer 5 is set and wired, which can prevent the strain caused by the mounting process from affecting the bonding wires 7. After forming the bonding wires 7, the encapsulation layer 8 can be directly formed on the integrated circuit without other processing, which helps to protect the bonding wires 7.

[0073] Exemplarily, the binding wire 7 is an aluminum wire. In the embodiment of the present disclosure, the process constraints are relatively loose, and a relatively low-cost aluminum wire can be used to achieve a better signal response speed. Exemplarily, the peripheral component 6 includes one or more of a resistor, a capacitor, and a diode.

[0074] The material of the encapsulation layer 8 may include epoxy resin. The steps of forming the encapsulation layer 8 may include: dispensing, in which the epoxy resin glue may be used to seal the plurality of chip regions as a whole; and curing, in which the epoxy resin glue may be cured. Exemplarily, the encapsulation layer 8 may be polished using a high-precision grinder.

[0075] During the polishing step, the end surface of the packaging layer 8 facing away from the circuit board 2000 may be polished. Figure 5 The top surface of the grinding is flat, and the Figure 6 The structure shown. The flat surface may refer to a plane with a certain flatness. When the manufactured chip 5000 is installed in the box body 6000 ( Fig. 9 ), this end face of the encapsulation layer 8 can be used as a mounting surface.

[0076] In an exemplary embodiment, the chip manufacturing method 1000 may further include a marking step. A laser marking machine may be used to mark the surface of the packaging layer 8 , which may be used to mark the traceability information of each chip 5000 .

[0077] In an exemplary embodiment, the step of cutting includes: forming a first cutting opening 901 that cuts through the encapsulation layer 8 and extends into the substrate 1; and forming a second cutting opening 902 that extends into the substrate 1, with a residual portion 1101 based on the substrate 1 between the second cutting opening 902 and the first cutting opening 901. Exemplarily, after cutting off adjacent chip strips 4000, the following may be formed: Figure 7The individual chip strips 4000 shown. The first chip 5011 and the second chip 5012 can be connected by a residual portion 1101, and the residual portion 1101 can be manually broken off. A chip strip 4000 can include, for example, ten chips 5000, or other numbers. When in use, the required number of chips 5000 can be broken off as needed.

[0078] Exemplarily, the first cutting opening 901 and the second cutting opening 902 are formed by a cutting knife. Figure 7 With respect to the illustrated chip strip 4000 , the individual chips 5000 may be considered to have been formed.

[0079] The first packaging strip 81 can be divided into a plurality of packaging portions 800 ( Figure 8 ), ensuring that the integrated packaging strip is reliably divided, and then the integrated packaging layer 8 is reliably divided. For example, the first chip 5011 includes a first packaging part 811, and the first packaging part 811 and the second packaging part of the second chip 5012 are completely separated by the first cutting opening 901.

[0080] The first contact strip 41 may include a plurality of chip contacts 400, and the first chip 5011 includes a first chip contact 411. It is understandable that when the contact layer 4 is formed, the contacts in each chip region may be separated from each other. The chip contact may include a plurality of contacts.

[0081] The first base strip 11 is almost cut off by the cut, but is connected via the residual portion 1101 . The first chip 5011 may include a first chip substrate 111 , and the first chip substrate 111 is connected to the second chip 5012 via the residual portion 1101 .

[0082] The thinnest part of the residual part 1101 is 0.2mm to 0.3mm. The cutting edge of the cutting knife is roughly flat, but it can also have an arc. The second cutting opening 902 can be aligned with the first cutting opening 901, and then the size of the residual part 1101 along the Z-axis direction can be within 0.2mm to 0.3mm. In other embodiments, the second cutting opening is staggered with the first cutting opening. The chip manufacturing method 1000 provided in the embodiment of the present disclosure can form a residual part 1101 with controllable size, ensure the connection strength between adjacent chips 5000, and ensure the transportation and storage of the chip strip 4000; at the same time, it is suitable for manually tearing off the chip 5000 from the chip strip 4000. In addition, the size of each chip 5000 is cut accurately and the identity is good.

[0083] Exemplarily, the chip manufacturing method 1000 includes the steps of testing the performance of the chip 5000 and writing data, and also includes laser marking the end surface of the chip substrate 100 where the chip contacts 400 are provided. The mark can match the written data.

[0084] Illustratively, the chip manufacturing method 1000 includes a step of performing data verification on the chip 5000 to ensure that the written data is correct.

[0085] Figure 5 The chip splicing board provided by the present disclosure is shown. The embodiment of the present disclosure provides a chip splicing board 3000 , which may include a circuit board 2000 , a wafer 5 , a bonding wire 7 , a peripheral component 6 and a packaging layer 8 .

[0086] The circuit board 2000 includes a substrate 1 and a circuit pattern layer 2 and a contact layer 4 respectively located on both sides of the substrate 1, and the circuit pattern layer 2 is electrically connected to the contact layer 4. The chip splicing board 3000 may include a plurality of chips 5, which are located on the side of the substrate 1 provided with the circuit pattern layer 2 and can be fixed to the circuit board 2000. Each chip is electrically connected to the circuit pattern layer 2 through at least one binding wire 7. The chip splicing board 3000 may include a plurality of peripheral components 6, which are located on the same side of the substrate 1 as the chip 5, and which are electrically connected to the circuit pattern layer 2, such as by welding. The packaging layer 8 covers these chips 5, the binding wires 7 and the peripheral components 6. The corresponding at least one peripheral component 6 and at least one chip 5 are both located in the same chip area of ​​the circuit board 2000. The binding wires 7 are also located in the corresponding chip area.

[0087] The chip splicing board provided in the embodiment of the present disclosure has firm binding lines, wherein the working performance of the chip is good, and the process performance of the chip splicing board is good.

[0088] For example, the chip splicing plate 3000 may include a plurality of parallel chip strips 4000, and these chip strips 4000 may be cut and separated. Figure 5 As shown, the chip bar 4000 may be a first chip bar, which includes a first strip circuit board 2010 and a chip 5, a peripheral component 6, a bonding wire 7 and a first package bar 81 arranged on the first strip circuit board 2010. The first strip circuit board 2010 includes a first contact bar 41, a first base bar 11 and a first circuit pattern bar 21 stacked in sequence, and the first package bar 81 covers the first strip circuit board 2010 along the Z axis projection. The first contact bar 41 includes a plurality of chip contacts 400 arranged along the Y axis direction, the first base bar 11 includes a plurality of chip substrates 100 arranged along the Y axis direction, and the first circuit pattern bar 21 includes a plurality of chip circuits arranged along the Y axis direction. In other words, the chip bar 4000 includes a plurality of chips 5000 arranged along the Y axis direction.

[0089] refer to Figure 5 and Figure 7 The embodiment of the present disclosure provides a chip bar 4000, which may include a strip-shaped circuit board, a chip 5, a binding wire 7, a peripheral component 6, and a packaging bar.

[0090] The strip-shaped circuit board includes a base strip and a circuit pattern strip and a contact strip respectively located on both sides of the base strip. The circuit pattern strip and the contact strip are electrically connected, and the strip-shaped circuit board has a plurality of chip areas arranged in a row. The chip strip 4000 may include a plurality of chips 5, and the chips 5 are located on the side of the base strip where the circuit pattern strip is provided, and may be fixedly connected to the base strip. Each chip 5 is electrically connected to the circuit pattern strip through at least one binding wire 7. The peripheral components 6 and the chips 5 are located on the same side of the base strip, and the peripheral components 6 are electrically connected to the circuit pattern strip, for example, by welding. The packaging strip covers these chips 5, the binding wires 7 and the peripheral components 6. The packaging strip has a plurality of discrete packaging parts 800, and the chip strip 4000 has a first cutting opening 901 separating the packaging parts 800, and the first cutting opening 901 extends into the base strip. Each packaging part 800 is located in a corresponding chip area and covers a corresponding at least one peripheral component 6, a binding wire 7 and at least one chip 5. The corresponding at least one peripheral component 6 and at least one chip 5 are both located in the same chip area of ​​the circuit board 2000. The binding wire 7 is also located in the corresponding chip area. The bonding wires 7 are also located in the corresponding chip area.

[0091] The chip bar provided by the embodiments of the present disclosure has good process performance, low cost and reliable circuit performance.

[0092] refer to Figure 5 and Figure 8 The embodiment of the present disclosure provides a chip 5000 , which may include a chip circuit board, a wafer 5 , a binding wire 7 , a peripheral component 6 and a packaging part 800 .

[0093] The chip circuit board includes a chip contact 400, a chip substrate 100 and a chip circuit stacked in sequence, and the chip circuit is electrically connected to the chip contact 400. The peripheral component 6 and the chip 5 are arranged on the same side of the chip substrate 100, specifically, the side of the chip substrate 100 where the chip circuit is arranged. The peripheral component 6 is electrically connected to the chip circuit, for example, by welding. The chip 5 is electrically connected to the chip circuit through a bonding wire 7. The packaging unit 800 covers the chip 5, the bonding wire 7 and the peripheral component 6.

[0094] The chip circuit provided by the embodiment of the present disclosure has good performance and low cost.

[0095] Illustratively, the chip splicing board, chip strip, and chip provided in the embodiments of the present disclosure may be formed according to the aforementioned chip manufacturing method.

[0096] refer to Fig. 9 The embodiment of the present disclosure provides a consumable 7000, which may include a chip 5000 and a box body 6000. The box body 6000 may be an ink cartridge, a toner cartridge, or a color box, etc. The data written in the chip 5000 may be used to reflect various parameters of the box body 6000.

[0097] Printing consumables are consumable products. Due to their own consumable characteristics, they are mostly disposable. The consumables provided by the embodiments of the present disclosure achieve stable and reliable performance at a relatively low cost. The consumables have good market prospects and economic benefits.

[0098] Chip 5000 can be pasted to the ink cartridge; it can be configured in a square shape and then stuffed or inserted into the slot of the ink cartridge according to its thickness; the shape of chip 5000 can also be designed, for example, including positioning holes or U-shaped grooves, and then positioned to the ink cartridge using the geometry of the shape.

[0099] Exemplarily, after the consumables 7000 are installed in the printer 8000 to form a printing system, the chip 5000 can be connected to the printer 8000 for communication. The printer 8000 can read the data stored in the chip 5000. The technical features of the above-disclosed embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-disclosed embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] In the embodiments disclosed above, unless otherwise clearly specified and limited, the execution order of each step is not limited, for example, it can be executed in parallel, or it can be executed successively in different orders. The sub-steps of each step can also be executed alternately. The above-mentioned various forms of processes can be used, and steps can be reordered, added or deleted, as long as the desired results of the technical solution provided in the embodiment of the present disclosure can be achieved, and this document does not limit it here.

[0101] The embodiments disclosed above only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection of the invention. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the scope of patent protection required by the present invention. Therefore, the scope of patent protection of the present invention shall be subject to the attached claims.

Claims

1. A chip manufacturing method, characterized in that: include: Mounting a plurality of peripheral components on one side of a circuit board, and electrically connecting the peripheral components to a circuit pattern layer of the circuit board, wherein the circuit board comprises a substrate and the circuit pattern layer and a contact layer respectively located on two sides of the substrate, the circuit pattern layer is electrically connected to the contact layer, and the peripheral components are located on a side of the substrate where the circuit pattern layer is provided; Arrange a plurality of chips on the one side of the circuit board, and the corresponding at least one chip and at least one peripheral component are located in the same chip area of ​​the circuit board; forming a binding wire, wherein the binding wire electrically connects the corresponding chip to the circuit pattern layer; forming a packaging layer covering the plurality of chips, the bonding wires and the plurality of peripheral components; and Cutting is performed between any two adjacent chip areas of the circuit board.

2. The chip manufacturing method according to claim 1, wherein: The cutting step includes: forming a first cutting opening that cuts off the packaging layer and extends into the substrate; and forming a second cutting opening that extends into the substrate, wherein a residual portion based on the substrate is between the second cutting opening and the first cutting opening.

3. The chip manufacturing method according to claim 2, wherein: The thinnest dimension of the residual portion is 0.2 mm to 0.3 mm.

4. The chip manufacturing method according to claim 1, wherein: It also includes: forming the circuit board, and the steps of forming the circuit board include: forming a cutting mark line for dividing the chip area; forming a mounting mark for marking the one side of the circuit board; and forming a positioning mark for positioning the circuit board.

5. The chip manufacturing method according to claim 1, wherein: The circuit board includes a plurality of chip areas in an array, and auxiliary fixing areas located at both ends of any column of the chip areas; The method further comprises: forming the circuit board, wherein the step of forming the circuit board comprises: forming an auxiliary fixing hole located in the auxiliary fixing area; The cutting step includes: forming a plurality of chip strips, each of the chip strips including a column of the chip regions.

6. The chip manufacturing method according to claim 1, wherein: Also includes: The packaging layer is polished so that the end surface of the packaging layer facing away from the circuit board is formed into a flat surface.

7. The chip manufacturing method according to any one of claims 1 to 6, wherein: The binding wire is an aluminum wire, the material of the packaging layer includes epoxy resin, and the circuit board is a printed circuit board.

8. A chip splicing board, characterized in that: include: A circuit board, comprising a substrate and a circuit pattern layer and a contact layer respectively located on two sides of the substrate, wherein the circuit pattern layer is electrically connected to the contact layer; A plurality of chips are located on a side of the substrate where the circuit pattern layer is provided; A plurality of binding wires, each of the chips is electrically connected to the circuit pattern layer through the binding wires; A plurality of peripheral components are located on the one side of the substrate and are electrically connected to the circuit pattern layer, and at least one of the corresponding peripheral components and at least one of the chips are located in the same chip area of ​​the circuit board; as well as A packaging layer, covering the plurality of chips, the plurality of binding wires and the plurality of peripheral components; Wherein, the chip splicing board is formed according to the steps of the chip manufacturing method according to any one of claims 1 to 7.

9. A chip strip, characterized in that include: A strip-shaped circuit board, comprising a base strip and a circuit pattern strip and a contact strip respectively located on both sides of the base strip, wherein the circuit pattern strip and the contact strip are electrically connected, and the strip-shaped circuit board has a plurality of chip areas arranged in a row; A plurality of chips are located on one side of the base strip where the circuit pattern strip is provided; A plurality of binding wires, each of the chips is electrically connected to the circuit pattern strips through the binding wires; A plurality of peripheral components are located on the one side of the base strip and are electrically connected to the circuit pattern strip, and at least one of the corresponding peripheral components and at least one of the chips are located in the same chip area in the strip-shaped circuit board; as well as A packaging strip, the packaging strip having a plurality of discrete packaging parts, each of the packaging parts is located in a corresponding chip area and covers a corresponding at least one peripheral component, the binding wire and at least one chip, The chip strip is formed according to the steps of the chip manufacturing method according to any one of claims 1 to 7, and the chip strip has a first cutting opening that separates the packaging parts, and the first cutting opening extends into the base strip.

10. A chip, characterized in that include: A chip circuit board, comprising a chip contact, a chip substrate and a chip circuit stacked in sequence, wherein the chip circuit is electrically connected to the chip contact; A wafer, located on a side of the chip substrate where the chip circuit is provided; A bonding wire, through which the wafer is electrically connected to the chip circuit; a peripheral component, located on the one side of the chip substrate and electrically connected to the chip circuit; and A packaging part, covering the chip, the binding wires and the peripheral components; Wherein, the chip is formed according to the steps of the chip manufacturing method according to any one of claims 1 to 7.

11. Consumables, characterized in that, include: Box body; and The chip as claimed in claim 10, mounted in the box body.

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