Flexible silicon wafer and preparation method thereof, and flexible solar cell prepared by adopting flexible silicon wafer

Abstract

The invention discloses a flexible silicon wafer and a preparation method thereof, and a flexible solar cell prepared by using the flexible silicon wafer. The preparation method of the flexible silicon wafer comprises the following steps: polishing the front surface and the back surface of the silicon wafer by adopting a polishing solution; depositing a thick dielectric film on the back area of the silicon wafer by adopting an ALD (Atomic Layer Deposition) method or a PECVD (Plasma Enhanced Chemical Vapor Deposition) method, plating the thick dielectric film on the side area and the front edge area of the silicon wafer in a winding manner, and forming a thin dielectric film on a transition area between the thick dielectric film on the front edge area of the silicon wafer and a middle non-mask area; and texturing the middle area of the silicon wafer and the transition area covered by the thin dielectric film by adopting an alkaline solution, then removing the thick dielectric film in other areas by adopting an HF-containing acidic solution, and cleaning the silicon wafer. According to the method, the bending strength of the silicon wafer can be improved, the flexibility of the HJT battery is improved, and the application range of the thin HJT battery is expanded.

Description

Technical Field

[0001] The present invention relates to the technical field of batteries, and in particular to a flexible silicon wafer and a preparation method thereof, and a flexible solar cell prepared by using the flexible silicon wafer. Background Art

[0002] Crystalline silicon solar cells are the most widely used solar cells in today's society and can be seen everywhere in daily life. In addition to the large-scale application of conventional solar cells in ground photovoltaic power stations and distributed photovoltaics, flexible solar cells also have huge development space in the fields of wearable electronics, mobile communications, mobile energy for vehicles, photovoltaic building integration, aerospace, etc. However, the limitations of conventional crystalline silicon solar cells, such as the inability to be bent and high brittleness, restrict the flexible application scenarios of crystalline silicon solar cells.

[0003] A certain degree of bendability can be achieved by reducing the thickness of silicon wafers. However, since crystalline silicon is an indirect bandgap semiconductor, reducing the thickness of silicon wafers will cause the current density of the battery to decrease significantly, which in turn greatly reduces the photoelectric conversion efficiency. Among existing crystalline silicon cells, the high-temperature processes of PERC and TOPCon are prone to cause silicon wafer warping, which limits the thinning of silicon wafers. Compared with PERC and TOPCon, HJT has the lowest preparation process temperature. The HJT low-temperature process is suitable for silicon wafer thinning. A certain degree of flexibility can be achieved by using HJT cells combined with thin silicon wafers. However, for conventional thin HJT cells, they are still prone to breakage under mechanical shock and vibration conditions, especially in areas of stress concentration.

[0004] Chinese patent application number CN116435403A proposes stacking textured silicon wafers and performing plasma edge etching of silicon to achieve smooth textured surfaces in the edge area. This method easily generates new surface undulations during the process of etching the pyramids at the edge of the silicon wafer, introducing new stress concentration points, resulting in a decrease in the bending strength of the silicon wafer instead of an increase.

[0005] Chinese patent application number CN116230787A proposes to apply glue to the edge of a polished silicon wafer, use it as a mask after drying, texture the middle of the silicon wafer, and then remove the glue to form a silicon wafer with polished edges and textured middle. This method is complicated, and the cost of coating the glue film and treating organic wastewater is high, which is not suitable for mass production.

[0006] Therefore, it is necessary to develop new methods for preparing edge-smoothed silicon wafers, improve the bending strength of silicon wafers, improve the flexibility of HJT cells, and expand the application scope of thin HJT cells. Summary of the invention

[0007] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and to provide a flexible silicon wafer and a preparation method thereof, and a flexible solar cell prepared using the flexible silicon wafer.

[0008] The present invention provides a flexible silicon wafer, the front side of which comprises three parts: a middle area, a transition area extending from the boundary of the middle area to the center of the middle area with a preset width, and a front side edge area remaining except the middle area and the transition area, wherein: the middle area and the transition area on the front side of the silicon wafer have a pyramid velvet surface, the pyramid size of the middle area is larger than the pyramid size of the transition area, and the front side edge area is a polished surface.

[0009] The present invention also provides a method for preparing the above-mentioned flexible silicon wafer, which includes: polishing the front and back sides of the silicon wafer; coating a thick dielectric film around the edge area of ​​the front side of the silicon wafer, and forming a thin dielectric film in the transition area between the thick dielectric film in the edge area of ​​the front side of the silicon wafer and the middle non-mask area; using the dielectric film as a mask, texturing the middle area and the transition area of ​​the silicon wafer to form pyramid velvet surfaces of different sizes; then removing the thick dielectric film in the edge area of ​​the front side of the silicon wafer to form a polished surface, and cleaning the surface of the silicon wafer.

[0010] The present invention also provides a flexible solar cell, which comprises the flexible silicon wafer.

[0011] The present invention also provides a method for preparing a silicon heterojunction battery, comprising the following steps: (1) Polishing the front and back sides of the silicon wafer using a polishing solution; (2) A thick dielectric film is deposited on the back side of the silicon wafer using the ALD method or the PECVD method, and a thick dielectric film is plated around the side area and the front edge area of ​​the silicon wafer, and a thin dielectric film is formed in the transition area between the thick dielectric film in the front edge area of ​​the silicon wafer and the non-mask area in the middle; (3) Use an alkaline solution to texturize the middle area of ​​the silicon wafer and the transition area covered by the thin dielectric film, then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer; (4) using a CVD method, sequentially depositing a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer on the front side of the silicon wafer; and depositing a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer on the back side of the silicon wafer; (5) depositing a first transparent conductive film layer on the first doped amorphous silicon layer and depositing a second transparent conductive film layer on the second doped amorphous silicon layer by using a PECVD method; (6) Using a printing process, a low-temperature conductive metal paste is printed on the front and back sides of the silicon wafer, and the paste is solidified to form a first metal electrode and a second metal electrode.

[0012] The present invention has the following beneficial effects: The present invention provides a flexible silicon wafer and a preparation method thereof, and a flexible solar cell prepared by using the flexible silicon wafer. The present invention provides a flexible silicon wafer, the front side of the silicon wafer includes three parts: a middle area, a transition area, and a front edge area, wherein: the middle area and the transition area have pyramid velvet surfaces, and the pyramid size of the middle area is larger than the pyramid size of the transition area, and the front edge area is a polished surface. In the silicon wafer provided above, the front edge area of ​​the silicon wafer is a polished surface, which consumes more energy during the fracture process, avoids stress concentration at the bottom of the edge pyramid when the silicon wafer is bent, causing the silicon wafer to break, and greatly improves the bending strength of the silicon wafer. In addition, there is a pyramid velvet structure with a smaller size than the middle area in the transition area on the front side of the silicon wafer, which can further prevent stress concentration on the pyramid velvet surface and improve the bending strength of the silicon wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of the HJT cell structure provided for comparative example 1, numbered as follows: 1-N-type single crystal silicon wafer; 2-first intrinsic amorphous silicon layer; 3-first doped amorphous silicon layer; 4-first transparent conductive film layer; 5-first metal electrode; 6-second intrinsic amorphous silicon layer; 7-second doped amorphous silicon layer; 8-second transparent conductive film layer; 9-second metal electrode; Figure 2 A process flow chart of HJT battery preparation provided for comparative example 1; Figure 3 Schematic diagram of the flexible silicon wafer provided in Example 1, numbered as follows: 1-1-middle area; 1-3-transition area; 1-2-front edge area; Figure 4 Schematic diagram of the silicon heterojunction cell structure provided in Example 2, numbered as follows: 1-N-type single crystal silicon wafer; 2-first intrinsic amorphous silicon layer; 3-first doped amorphous silicon layer; 4-first transparent conductive film layer; 5-first metal electrode; 6-second intrinsic amorphous silicon layer; 7-second doped amorphous silicon layer; 8-second transparent conductive film layer; 9-second metal electrode; Figure 5 This is a process flow chart for preparing a silicon heterojunction cell provided in Example 2. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0016] A flexible silicon wafer and a method for preparing the same, as well as a flexible solar cell prepared using the flexible silicon wafer provided in an embodiment of the present invention are described in detail below.

[0017] In a first aspect, an embodiment of the present invention provides a flexible silicon wafer, the front side of which includes three parts: a middle area, a transition area of ​​a preset width extending from the boundary of the middle area toward the center of the middle area, and a front edge area remaining except the middle area and the transition area, wherein: the middle area and the transition area have a pyramid velvet surface, and the pyramid size of the middle area is larger than the pyramid size of the transition area, and the front edge area is a polished surface.

[0018] The edge surfaces and sides of the silicon wafers of the HJT cells currently manufactured have pyramid velvet surfaces, which makes it easy for stress to concentrate at the bottom of the edge pyramids during the bending process of the cell, causing cracks and leading to cell rupture.

[0019] In order to improve the bending strength of silicon wafers, improve the flexibility of solar cells, and expand the application of thin solar cells, an embodiment of the present invention provides a flexible silicon wafer, the front side of which includes three parts: a middle area, a transition area, and a front edge area, and the middle area and the transition area between the middle area and the front edge area have a pyramid velvet surface, and the front edge area is a polished structure without a pyramid velvet surface. The smooth edge area consumes more energy during the fracture process, which prevents the stress from concentrating on the bottom of the edge pyramid when the silicon wafer is bent, causing the silicon wafer to break, and greatly improves the bending strength of the silicon wafer. The transition area has a pyramid velvet surface of a smaller size than the middle area, which can further prevent the stress concentration of the straight velvet surface and improve the bending strength of the silicon wafer. Thus, the thin crystalline silicon wafer has a flexible structural feature, significantly improves the flexibility of the crystalline silicon wafer, and can be widely used in silicon heterojunction (HJT, SHJ, HIT) solar cells, tunneling oxide passivation contact (TOPCon) solar cells, passivated emitter and back (PERC), interdigitated back contact (IBC) solar cells, etc., and has a wide range of application prospects and practical value.

[0020] In some optional embodiments, the backside region and the side regions of the flexible silicon wafer are also polished surfaces.

[0021] The embodiment of the present invention provides a flexible silicon wafer, the front edge area, side area, and back area of ​​the flexible silicon wafer are all polished surfaces, and the pyramid velvet surface is only in the middle area and transition area of ​​the front side of the silicon wafer. The flexible silicon wafer with the above structure can make the crystalline silicon wafer flexible without changing the surface reflectivity, thereby improving the mechanical properties. The smooth edge area will consume more energy during the fracture process, greatly improving the bending strength of the silicon wafer; and the back side adopts a polished surface, the surface passivation is significantly improved compared to the velvet surface, and the battery Voc is improved; the internal reflection of long-wave light is further enhanced, and the short-circuit current Jsc is improved; therefore, the battery efficiency is further improved. In addition, the polished surface on the back side has a lower surface area than the pyramid velvet surface, which can reduce the amount of ITO used and reduce the cost of the battery.

[0022] In some optional embodiments, the width of the front edge region is 0.5 mm-3 mm, the width of the transition region is 20 μm-200 μm, the pyramid size of the middle region is 1 μm-3 μm, and the pyramid size of the transition region is 0.7 μm-1.5 μm.

[0023] In a second aspect, an embodiment of the present invention also provides a method for preparing the above-mentioned flexible silicon wafer, which includes: polishing the front and back sides of the silicon wafer; coating a thick dielectric film around the edge area of ​​the front side of the silicon wafer, and forming a thin dielectric film in the transition area between the thick dielectric film in the edge area of ​​the front side of the silicon wafer and the middle non-mask area; using the dielectric film as a mask, texturing the middle area and transition area of ​​the silicon wafer to form pyramid texturing surfaces of different sizes; then removing the thick dielectric film in the edge area of ​​the front side of the silicon wafer to form a polished surface, and cleaning the surface of the silicon wafer.

[0024] In some optional embodiments, the steps include: (1) Polishing the front and back sides of the silicon wafer using a polishing solution; (2) A thick dielectric film is deposited on the back side of the silicon wafer using the ALD method or the PECVD method, and a thick dielectric film is plated around the side area and the front edge area of ​​the silicon wafer, and a thin dielectric film is formed in the transition area between the thick dielectric film in the front edge area of ​​the silicon wafer and the non-mask area in the middle; (3) Use an alkaline solution to texturize the middle area of ​​the silicon wafer and the transition area covered by the thin dielectric film, and then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer.

[0025] In some optional embodiments, in step (2), the deposition temperature is controlled to be 300-400° C., and the deposited dielectric film is composed of SiO x 、SiN x 、SiO x N yAt least one of the following: the thickness of the thick dielectric film deposited in the front edge area, side area, and back area of ​​the silicon wafer is 20nm~150nm, and the thickness of the thin dielectric film in the transition area is 1nm-20nm.

[0026] In some optional embodiments, in step (3), an alkaline solution is used to texture the unmasked area and transition area in the middle of the silicon wafer to form a 1-3um pyramid texture surface in the middle area and a 0.7μm-1.5μm pyramid texture surface in the transition area; the alkaline solution contains NaOH, a texturing additive, and water, and the temperature of the alkaline solution is controlled at 70°C-85°C; the back area, side area, and front edge area of ​​the silicon wafer are blocked by the dielectric film to retain the polished surface.

[0027] In a third aspect, an embodiment of the present invention further provides a flexible solar cell, and the flexible solar cell includes the above-mentioned flexible silicon wafer.

[0028] In some optional embodiments, the flexible solar cell includes a silicon heterojunction solar cell, a tunneling oxide layer passivation contact solar cell or a back contact solar cell.

[0029] In some optional embodiments, the structure of the silicon heterojunction solar cell is as follows: a flexible silicon wafer is used as a substrate, and a first intrinsic amorphous silicon layer, a first doped amorphous silicon layer, a first transparent conductive film layer, and a first metal electrode are sequentially arranged on the front side thereof; a second intrinsic amorphous silicon layer, a second doped amorphous silicon layer, a second transparent conductive film layer, and a second metal electrode are sequentially arranged on the back side of the silicon wafer, wherein: Flexible silicon wafers, which are Czochralski single crystals or cast single crystals, including n-type doped or p-type doped single crystal silicon wafers; The first intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films; The first doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer, including one or a combination of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor films; The first transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide; The first metal electrode is a composite layer of one or more of Ag, Cu, Al, and Ni; The second intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor thin films; The second doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer, including one or a combination of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor thin films; the second doped amorphous silicon layer is opposite to the first doped amorphous silicon layer in conductivity type; The second transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide; The second metal electrode is a composite layer of one or more of Ag, Cu, Al and Ni.

[0030] In some optional embodiments, the thickness of the flexible silicon sheet is 50 μm-150 μm; The first intrinsic amorphous silicon layer has a thickness of 4nm-10nm and is prepared by PECVD or Cat-CVD deposition; The first doped amorphous silicon layer has a thickness of 5nm-30nm and is prepared by PECVD or Cat-CVD deposition; The thickness of the first transparent conductive film layer is 60nm-120nm; it is deposited by magnetron sputtering or RPD; The first metal electrode has a thickness of 10 μm-50 μm and a width of 5 μm-50 μm; it is prepared by screen printing, inkjet printing, laser transfer or electroplating; The second intrinsic amorphous silicon layer has a thickness of 4nm-10nm and is prepared by PECVD or Cat-CVD deposition; The second doped amorphous silicon layer has a thickness of 5nm-30nm; it is prepared by PECVD or Cat-CVD deposition; the second doped amorphous silicon layer has a conductivity type opposite to that of the first doped amorphous silicon layer; The thickness of the second transparent conductive film layer is 60nm-120nm; it is deposited by magnetron sputtering or RPD; The second metal electrode has a thickness of 10 μm-50 μm and a width of 5 μm-50 μm; it is prepared by screen printing, inkjet printing, laser transfer or electroplating.

[0031] In a fourth aspect, an embodiment of the present invention further provides a method for preparing a silicon heterojunction battery, comprising the following steps: (1) Polishing the front and back sides of the silicon wafer using a polishing solution; (2) A thick dielectric film is deposited on the back side of the silicon wafer using the ALD method or the PECVD method, and a thick dielectric film is plated around the side area and the front edge area of ​​the silicon wafer, and a thin dielectric film is formed in the transition area between the thick dielectric film in the front edge area of ​​the silicon wafer and the non-mask area in the middle; (3) Use an alkaline solution to texturize the middle area of ​​the silicon wafer and the transition area covered by the thin dielectric film, then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer; (4) using a CVD method, sequentially depositing a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer on the front side of the silicon wafer; and depositing a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer on the back side of the silicon wafer; (5) depositing a first transparent conductive layer on the first doped amorphous silicon layer and depositing a second transparent conductive layer on the second doped amorphous silicon layer by using a PECVD method; (6) Using a printing process, a low-temperature conductive metal paste is printed on the front and back sides of the silicon wafer, and the paste is solidified to form a first metal electrode and a second metal electrode.

[0032] The present invention will be further described below in conjunction with the embodiments.

[0033] Example 1 A method for preparing a flexible silicon wafer comprises the following steps: (1) Polishing the front and back sides of the silicon wafer using a polishing solution; (2) Using the PECVD method, a thick dielectric film is deposited on the back side of the silicon wafer, and a thick dielectric film is plated around the side and front edge areas of the silicon wafer, and a thin dielectric film is formed in the transition area between the thick dielectric film in the front edge area of ​​the silicon wafer and the non-mask area in the middle; (3) Using an alkaline solution, the thin dielectric film in the unmasked area and transition area in the middle of the silicon wafer is etched to form pyramid velvet surfaces of different sizes. The dielectric film is used as a mask in other areas to retain the polished surface. (4) Use HF solution to remove the thick dielectric film on the front edge area, side area, and back area of ​​the silicon wafer, and clean the surface of the silicon wafer.

[0034] In step (1), a polishing solution is used to perform surface polishing on the silicon wafer; the alkaline solution is composed of NaOH, a polishing additive, and water, and the temperature of the alkaline solution is 60° C.-80° C.

[0035] In step (2), the deposition temperature is controlled to be 300°C to 400°C, and the composition of the deposited dielectric film is SiO x The thickness of the thick dielectric film deposited in the front edge area, side area, and back area of ​​the silicon wafer is 50nm~80nm, and the average thickness of the thin dielectric film in the transition area is 10nm~20nm.

[0036] In step (3), an alkaline solution is used to texture the unmasked area and transition area in the middle of the silicon wafer to form a 2μm~3μm pyramid texture surface in the middle area and a 1μm~2μm pyramid texture surface in the transition area; the alkaline solution contains NaOH, a texture-making additive, and water, and the temperature of the alkaline solution is controlled at 70°C-85°C; the back area, side area, and front edge area of ​​the silicon wafer are blocked by a thick dielectric film to retain a polished surface.

[0037] In step (4), a hydrofluoric acid solution is used to remove the thick dielectric film in other areas, and an acid-base solution is used to clean the surface of the silicon wafer.

[0038] The structure of the flexible silicon wafer prepared by the above preparation method is shown in Figure 3 The flexible silicon wafer has a front side, a back side opposite to the front side, and a side side, wherein: the front side of the flexible silicon wafer has three parts: a middle area 1-1, a transition area 1-3 extending from the boundary of the middle area to the center of the middle area 1-1 with a preset width, and a front edge area 1-2 remaining except the middle area 1-1 and the transition area 1-3, wherein: the middle area 1-1 and the transition area 1-3 on the front side of the silicon wafer have a pyramid velvet surface, and the pyramid size of the middle area 1-1 is larger than the pyramid size of the transition area 1-3, and the back area (not shown), the side area (not shown) and the front edge area 1-2 are all polished surfaces.

[0039] Example 2 like Figure 3 and 4 As shown, a silicon heterojunction battery is based on an N-type single crystal silicon wafer 1 with a thickness of 80 μm and a resistivity of 1.0 Ω·cm-1.2 Ω·cm. A first intrinsic amorphous silicon layer 2, a first doped amorphous silicon layer 3, a first transparent conductive film layer 4 and a first metal electrode 5 are sequentially arranged on the front side of the N-type single crystal silicon wafer 1; a second intrinsic amorphous silicon layer 6, a second doped amorphous silicon layer 7, a second transparent conductive layer 8 and a second metal electrode 9 are sequentially arranged on the back side, wherein: the N-type single crystal silicon wafer 1 is a flexible silicon wafer, having a front side, a back side opposite to the front side and a side surface, and Middle: The front side of the flexible silicon wafer has three parts: a middle area 1-1, a transition area 1-3 extending from the boundary of the middle area to the center of the middle area 1-1 with a preset width, and a front edge area 1-2 remaining except the middle area 1-1 and the transition area 1-3, wherein: the middle area 1-1 and the transition area 1-3 on the front side of the silicon wafer have a pyramid velvet surface, and the pyramid size of the middle area 1-1 is larger than the pyramid size of the transition area 1-3, and the back area (not shown), the side area (not shown) and the front edge area 1-2 are all polished surfaces.

[0040] like Figure 5 As shown, a method for preparing the above silicon heterojunction battery comprises the following steps: (1) Use a polishing solution to polish the surface (front and back) of the silicon wafer; the alkaline solution is composed of NaOH, polishing additives, and water, and the temperature is 60°C-80°C; (2) Using PECVD deposition method, SiH 4 and N 2 O is the reaction gas, and SiO is deposited on the back, side, and front edge areas of the silicon wafer. x Dielectric film, deposition temperature 300℃~400℃, SiO xThe thickness is 20nm~40nm; there is a transition area of ​​100μm~200μm between the front edge area and the middle texturing area. The dielectric film in the transition area is thinner, with an average thickness of 10nm~20nm; (3) Use an alkaline solution to texturize the unmasked area in the middle of the silicon wafer to form a 2μm-3μm pyramid texture surface; the alkaline solution contains NaOH, a texturizing additive, and water, and the temperature is 70℃-85℃; the back area, side area, and front edge area of ​​the silicon wafer retain the polished surface due to the blocking of the thick dielectric film; the transition area on the front side is protected by a thin dielectric film to form a smaller pyramid texture surface with a size of 1μm~1.5μm; (4) Use hydrofluoric acid solution to remove the thick dielectric film in other areas, and use acid and alkali solution to clean the surface of the silicon wafer; (5) The first intrinsic amorphous silicon layer 2 and the first doped amorphous silicon layer 3 are deposited by PECVD to form a 4nm-6nm first intrinsic amorphous silicon layer 2 and a 5nm-10nm first doped amorphous silicon layer 3 on the front side of the silicon wafer; and a 5nm-7nm second intrinsic amorphous silicon layer 6 and a 8nm-15nm second doped amorphous silicon layer 7 are formed on the back side of the silicon wafer; (6) A 75 nm first transparent conductive film layer 4 is deposited on the first doped amorphous silicon layer 3 by a PVD method, and a 75 nm second transparent conductive film layer 8 is deposited on the second doped amorphous silicon layer 7. The mass percentage of indium in the transparent conductive film layer ITO is 90%, and the mass percentage of tin is 10%. Ar and O are filled in the PVD equipment. 2 , O 2 The Ar flow ratio was 0.025, the pressure was 0.5 Pa, and the substrate temperature was room temperature.

[0041] (7) A printing process is adopted to print low-temperature conductive metal paste on the front and back sides of the silicon wafer respectively. The low-temperature metal paste on the front and back sides is one of the low-temperature metal pastes containing silver Ag and silver-coated copper Ag@Cu. The low-temperature paste is then treated by a low-temperature hot air curing method to form an ohmic contact low-temperature metal paste electrode, that is, a first metal electrode 5 is formed on the front side of the silicon wafer and a second metal electrode 9 is formed on the back side.

[0042] Comparative Example 1 like Figure 1 and Figure 2 As shown, a HJT battery and a method for preparing the same include the following steps: S1 Texturing and Cleaning: Use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of silicon wafers, and form a surface pyramid texture on the surface of single crystal silicon wafers to increase the absorption of sunlight and reduce reflection; the single crystal silicon wafer is a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 0.1Ω·cm-10Ω·cm and a thickness of 100μm-200μm; then, use the RCA standard cleaning method to clean the surface of the silicon wafer to remove surface contamination impurities. Finally, use 2% hydrofluoric acid solution to remove the surface oxide layer.

[0043] S2: PECVD deposition of front and back intrinsic amorphous silicon layers and doped amorphous silicon layers: using PECVD deposition, a 4nm-6nm first intrinsic amorphous silicon layer 2 and a 5nm-10nm first doped amorphous silicon layer 3 are formed on the front side of the silicon wafer; a 5nm-7nm second intrinsic amorphous silicon layer 6 and a 8nm-15nm second doped amorphous silicon layer 7 are formed on the back side of the silicon wafer; S3: PVD deposition of transparent conductive film layers on the front and back: PVD method is used to deposit a 75nm first transparent conductive film layer 4 on the first doped amorphous silicon layer 3, and a 75nm second transparent conductive film layer 8 on the second doped amorphous silicon layer 7. The mass percentage of indium in the transparent conductive film layer ITO is 90%, and the mass percentage of tin is 10%. Ar and O are filled in the PVD equipment. 2 , O 2 The Ar flow ratio was 0.025, the pressure was 0.5 Pa, and the substrate temperature was room temperature.

[0044] S4: Screen printing / curing low-temperature metal paste on the front and back sides: Finally, low-temperature metal electrodes are formed on the front and back transparent conductive film layers by low-temperature curing using screen printing, that is, a first metal electrode 5 is formed on the front side of the silicon wafer and a second metal electrode 9 is formed on the back side.

[0045] Comparative Example 2 A plasma edge-etched velvet sheet, HJT battery and preparation method thereof: S1 Texturing and Cleaning: Use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of silicon wafers, and form a surface pyramid texture on the surface of single crystal silicon wafers to increase the absorption of sunlight and reduce reflection; the single crystal silicon wafer is a phosphorus-doped N-type single crystal silicon wafer with a resistivity of 0.1Ω·cm-10Ω·cm and a thickness of 100μm-200μm; S2: Place the silicon wafer stack in the ICP plasma etching chamber to CF 4 , O 2 For the reaction gas, the power and reaction time are controlled, and the pyramids at the edge of the silicon wafer are etched; S3: Then, the surface of the silicon wafer is cleaned using the RCA standard cleaning method to remove surface contamination impurities. Finally, a 2% hydrofluoric acid solution is used to remove the surface oxide layer.

[0046] S4: Prepare HJT cells using the above silicon wafers.

[0047] The performance of the batteries obtained in the embodiments and comparative examples was tested below. The parameters of the solar cell were measured using an IV tester, and the bending strength of the cell was measured using a three-point bending strength test method. The results are shown in the following table.

[0048]

[0049] From the above data, it can be seen that in Comparative Example 1, the HJT battery edge surface and side have pyramid velvet, which makes it easy for stress to concentrate at the bottom of the edge pyramid during the battery bending process, resulting in cracks and battery breakage. In Comparative Example 2, in the process of plasma etching the pyramid at the edge of the silicon wafer, new surface undulations are easily generated, introducing new stress concentration points, resulting in a decrease in the bending strength of the silicon wafer; at the same time, the new surface undulations introduced at the edge lead to edge composite loss, resulting in reduced battery efficiency.

[0050] The technical solution provided by the present invention, through the polishing of silicon wafers and the protection of edge masks, makes the velvet surface only formed in the middle area of ​​the front side of the silicon wafer during the velvet making process. The front edge area, side area, and back area of ​​the silicon wafer are all polished surfaces, which will consume more energy during the fracture process, avoiding the stress concentration at the bottom of the edge pyramid when the silicon wafer is bent, causing the silicon wafer to break, and greatly improving the bending strength of the silicon wafer. In addition, there are pyramids with smaller sizes than the middle velvet area in the transition area, which can further prevent stress concentration on the front velvet surface and improve the bending strength of the silicon wafer. The back side adopts a polished surface, and the surface passivation is significantly improved compared to the velvet surface, and the battery Voc is improved; the internal reflection of long-wave light is further enhanced, and the short-circuit current Jsc is improved; therefore, the battery efficiency is further improved.

[0051] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A flexible silicon wafer, characterized in that: The front side of the flexible silicon wafer includes three parts: a middle area, a transition area of ​​a preset width extending from the boundary of the middle area toward the center of the middle area, and a front edge area remaining except the middle area and the transition area, wherein: the middle area and the transition area on the front side of the silicon wafer have a pyramid velvet surface, and the pyramid size of the middle area is larger than the pyramid size of the transition area, and the front edge area is a polished surface.

2. The flexible silicon wafer according to claim 1, characterized in that: The back area and the side areas of the flexible silicon sheet are also polished surfaces.

3. The flexible silicon wafer according to claim 1, characterized in that: The width of the front edge area is 0.5 mm-3 mm, the width of the transition area is 20 μm-200 μm, the size of the pyramids in the middle area is 1 μm-3 μm, and the size of the pyramids in the transition area is 0.7 μm-1.5 μm.

4. A method for preparing a flexible silicon wafer according to any one of claims 1 to 3, characterized in that: It includes: Polishing the front and back sides of the silicon wafer; A thick dielectric film is plated around the edge region of the front side of the silicon wafer, and a thin dielectric film is formed in the transition region between the thick dielectric film in the edge region of the front side of the silicon wafer and the middle non-mask region; using the dielectric film as a mask, the middle region and the transition region of the silicon wafer are textured to form pyramid texture surfaces of different sizes; Then, the thick dielectric film in the front edge area of ​​the silicon wafer is removed to form a polished surface, and the surface of the silicon wafer is cleaned.

5. The preparation method according to claim 4, characterized in that: The following steps are involved: (1) Polishing the front and back sides of the silicon wafer using a polishing solution; (2) depositing a thick dielectric film on the back side of the silicon wafer by ALD or PECVD, and coating the thick dielectric film on the side and front edge regions of the silicon wafer, and forming a thin dielectric film in the transition region between the thick dielectric film on the front edge region of the silicon wafer and the middle non-mask region; (3) Use an alkaline solution to texturize the middle area of ​​the silicon wafer and the transition area covered by the thin dielectric film, and then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer.

6. The preparation method according to claim 5, characterized in that: In the step (2), the deposition temperature is controlled to be 300°C to 400°C, and the deposited dielectric film is composed of SiO x 、SiN x 、SiO x N y At least one of the above, the thickness of the thick dielectric film deposited in the front edge area, side area, and back area of ​​the silicon wafer is 20nm~150nm, and the thickness of the thin dielectric film in the transition area is 1nm-20nm.

7. The preparation method according to claim 5, characterized in that: In the step (3), an alkaline solution is used to texture the unmasked area and transition area in the middle of the silicon wafer to form a pyramid texture surface of 1μm-3μm in the middle area and a pyramid texture surface of 0.7μm-1.5μm in the transition area; the alkaline solution contains NaOH, a texture-making additive, and water, and the temperature of the alkaline solution is controlled at 70°C-85°C; the back area, side area, and front edge area of ​​the silicon wafer retain a polished surface under the blocking of the dielectric film.

8. A flexible solar cell, characterized in that: The flexible solar cell comprises a flexible silicon wafer according to any one of claims 1 to 3 or a flexible silicon wafer prepared by the preparation method according to any one of claims 4 to 7.

9. The flexible solar cell according to claim 8, characterized in that: The flexible solar cell includes a silicon heterojunction solar cell, a tunnel oxide layer passivation contact solar cell or a back contact solar cell; The structure of the silicon heterojunction solar cell is as follows: a flexible silicon wafer is used as a substrate, a first intrinsic amorphous silicon layer, a first doped amorphous silicon layer, a first transparent conductive film layer and a first metal electrode are sequentially arranged on the front side; a second intrinsic amorphous silicon layer, a second doped amorphous silicon layer, a second transparent conductive film layer and a second metal electrode are sequentially arranged on the back side, wherein: The flexible silicon wafer is a Czochralski single crystal or a cast single crystal, including an n-type doped or p-type doped single crystal silicon wafer; the thickness is 50 μm-150 μm; The first intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films; the thickness is 4nm-10nm; and it is prepared by PECVD or Cat-CVD deposition; The first doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer, including one or a combination of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor films; the thickness is in the range of 5nm-30nm; and it is prepared by PECVD or Cat-CVD deposition; The first transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide; the thickness is 60nm-120nm; and it is deposited by magnetron sputtering or RPD; The first metal electrode is a composite layer of one or more of Ag, Cu, Al, and Ni; the thickness is 10 μm-50 μm, the width is 5 μm-50 μm; and it is prepared by screen printing, inkjet printing, laser transfer or electroplating; The second intrinsic amorphous silicon layer is a composite film layer of one or more of undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films; the thickness is 4nm-10nm; and it is prepared by PECVD or Cat-CVD deposition; The second doped amorphous silicon layer is an n-type doped or p-type doped amorphous silicon layer, including one or a combination of amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor films; the thickness is 5nm-30nm; it is prepared by PECVD or Cat-CVD deposition; the second doped amorphous silicon layer is opposite to the first doped amorphous silicon layer in conductivity type; The second transparent conductive film layer is a composite layer of one or more of doped indium oxide, zinc oxide or tin oxide; the thickness is 60nm-120nm; and it is deposited by magnetron sputtering or RPD; The second metal electrode is a composite layer of one or more of Ag, Cu, Al, and Ni; the thickness is 10 μm-50 μm, the width is 5 μm-50 μm; and it is prepared by screen printing, inkjet printing, laser transfer or electroplating.

10. A method for preparing a silicon heterojunction battery, characterized in that: The following steps are involved: (1) Polishing the front and back sides of the silicon wafer using a polishing solution; (2) depositing a thick dielectric film on the back side of the silicon wafer by ALD or PECVD, and coating the thick dielectric film on the side and front edge regions of the silicon wafer, and forming a thin dielectric film in the transition region between the thick dielectric film on the front edge region of the silicon wafer and the middle non-mask region; (3) Use an alkaline solution to texturize the middle area of ​​the silicon wafer and the transition area covered by the thin dielectric film, then use an acidic solution containing HF to remove the thick dielectric film in other areas and clean the silicon wafer; (4) using a CVD method, sequentially depositing a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer on the front side of the silicon wafer; and depositing a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer on the back side of the silicon wafer; (5) depositing a first transparent conductive film layer on the first doped amorphous silicon layer and depositing a second transparent conductive film layer on the second doped amorphous silicon layer by using a PECVD method; (6) Using a printing process, a low-temperature conductive metal paste is printed on the front and back sides of the silicon wafer, and the paste is solidified to form a first metal electrode and a second metal electrode.

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