Circuit system for entering chip test mode

Abstract

The invention relates to a circuit system for entering a chip test mode, which comprises a negative pressure detection module, a sampling windowing module and a sampling latch module, and is characterized in that the output end of the negative pressure detection module is connected with the sampling windowing module, and the output end of the sampling windowing module is connected with the sampling latch module; the negative pressure detection module is used for detecting whether negative pressure is applied to a certain PIN; the sampling windowing module is used for delaying for a period of time and generating a sampling windowing signal after the chip power-on reset signal is released; and the sampling latch module is used for delaying and latching the result of the negative pressure detection module. By adopting the circuit system for entering the chip test mode, the test mode can be quickly and reliably entered only by multiplexing any PIN of a non-power ground and applying a negative pressure to the outside, so that the test time is effectively saved, the chip area is saved, and the circuit system has wide practical value.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, in particular to the field of chip testing, and specifically refers to a circuit system for realizing entry into a chip testing mode. Background Art

[0002] With the development of electronic information technology, electronic products are closely related to our lives, from electronic toys, mobile phones and televisions to cars, rockets and airplanes. The application of chips is becoming more and more common, which has greatly promoted the development and research and development of the chip industry.

[0003] Chip testability is an important key link in chip design. Due to process deviations, the reference voltage, clock frequency, bias current, etc. inside the chip need to be adjusted by entering the test mode. At the same time, some parameter indicators of the chip also need to enter the test mode for testing to ensure that the function and performance of each chip after testing can meet the requirements of the product specification.

[0004] A good chip testing method can save the chip cost and chip testing cost to the maximum extent. It has the characteristics of simple test circuit, small layout area, small PIN resource occupation, convenient test conditions, short test time, and reliable entry into test mode. It can enter the test mode immediately when it is needed, and must not enter the test mode when it is not needed, otherwise it will affect the normal operation of the chip. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a circuit system for entering a chip test mode which has the advantages of simple structure, high reliability and wide application range.

[0006] In order to achieve the above object, the circuit system of the present invention for entering the chip test mode is as follows:

[0007] The circuit system for entering the chip test mode has the following main features: the system includes a negative pressure detection module, a sampling window module and a sampling latch module; the output end of the negative pressure detection module is connected to the sampling window module, and the output end of the sampling window module is connected to the sampling latch module; the negative pressure detection module is used to detect whether negative pressure is applied to a certain PIN pin; the sampling window module is used to delay for a period of time and generate a sampling window signal after the power-on reset signal on the chip is released; the sampling latch module is used to delay and latch the result of the negative pressure detection module.

[0008] Preferably, the negative pressure detection module includes an NMOS tube, a pull-up resistor and a first inverter, the gate of the NMOS tube is grounded, the drain or source of the NMOS tube is connected to the PIN pin, the source or drain of the NMOS tube is connected to the pull-up resistor and serves as the input of the first inverter, and the output of the first inverter serves as an indication result signal of the negative pressure detection.

[0009] Preferably, if the system needs to enter a test mode, a certain PIN pin of the chip is connected to a negative pressure to enter the test mode, and the negative pressure detection module detects the negative pressure and outputs a high level indication signal.

[0010] Preferably, the sampling windowing module includes a second inverter, a third inverter, and an RC delay circuit. The input end of the second inverter is connected to a power-on reset signal, and the output end is connected to the RC delay circuit. The output end of the RC delay circuit is connected to the third inverter, and the output end of the third inverter is connected to the sampling latch module.

[0011] Preferably, the sampling latch module includes a D flip-flop, the data terminal of the D flip-flop is connected to the negative pressure indication signal output by the negative pressure detection module, the clock terminal of the D flip-flop is connected to the sampling windowing signal output by the sampling windowing module, and the reset terminal is connected to the power-on reset signal; the D flip-flop latches the result of the negative pressure detection module after the power-on reset rising edge arrives and delays for a period of time.

[0012] The circuit system for entering the chip test mode of the present invention adopts the condition of adding negative voltage to the PIN pin as the first condition for entering the test mode. At the same time, only the moment after the rising edge of the power-on reset signal is delayed for a period of time is used as a sampling window to observe whether the first condition is met, thereby avoiding the chip from mistakenly entering the test mode when it is working normally. There is no need to add other complex conditions such as inputting a password sequence or adding filtering to the input signal. The present invention only needs to reuse any PIN pin that is not the power ground and add a negative voltage externally to achieve rapid and reliable entry into the test mode, thereby effectively saving test time and chip area, and has a wide range of practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a flow chart of a method for implementing a circuit system for entering a chip test mode.

[0014] Figure 2 It is a structural diagram of the components of the circuit system for entering the chip test mode according to the present invention.

[0015] Figure 3 The negative pressure detection module circuit diagram of the circuit system for entering the chip test mode of the present invention.

[0016] Figure 4 The present invention is a sampling windowing circuit diagram of a circuit system for implementing a chip test mode.

[0017] Figure 5 The figure is an overall circuit diagram of the circuit system for entering the chip test mode according to the present invention.

[0018] Figure 6 The diagram is a schematic diagram of an application test embodiment of a circuit system for implementing a chip test mode according to the present invention. DETAILED DESCRIPTION

[0019] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0020] The circuit system for entering the chip test mode of the present invention includes a negative pressure detection module, a sampling window module and a sampling latch module, wherein the output end of the negative pressure detection module is connected to the sampling window module, and the output end of the sampling window module is connected to the sampling latch module; the negative pressure detection module is used to detect whether negative pressure is applied to a certain PIN pin; the sampling window module is used to delay for a period of time and generate a sampling window signal after the power-on reset signal on the chip is released; the sampling latch module is used to delay and latch the result of the negative pressure detection module.

[0021] As a preferred embodiment of the present invention, the negative pressure detection module includes an NMOS tube, a pull-up resistor and a first inverter, the gate of the NMOS tube is grounded, the drain or source of the NMOS tube is connected to the PIN pin, the source or drain of the NMOS tube is connected to the pull-up resistor and serves as the input of the first inverter, and the output of the first inverter serves as an indication result signal of negative pressure detection.

[0022] As a preferred embodiment of the present invention, if the system needs to enter the test mode, a PIN pin of the chip is connected to a negative pressure to enter the test mode. The negative pressure detection module detects the negative pressure and outputs a high level indication signal.

[0023] As a preferred embodiment of the present invention, the sampling windowing module includes a second inverter, a third inverter, and an RC delay circuit. The input end of the second inverter is connected to a power-on reset signal, and the output end is connected to the RC delay circuit. The output end of the RC delay circuit is connected to the third inverter, and the output end of the third inverter is connected to the sampling latch module.

[0024] As a preferred embodiment of the present invention, the sampling latch module includes a D flip-flop, the data terminal of the D flip-flop is connected to the negative pressure indication signal output by the negative pressure detection module, the clock terminal of the D flip-flop is connected to the sampling windowing signal output by the sampling windowing module, and the reset terminal is connected to the power-on reset signal; the D flip-flop latches the result of the negative pressure detection module after the power-on reset rising edge arrives and delays for a period of time.

[0025] In a specific embodiment of the present invention, a circuit and method for entering a chip test mode with a simple structure, high reliability and wide application range is proposed, thereby avoiding the risk of mistakenly entering the test mode during normal operation.

[0026] Figure 1 The present invention proposes a flow chart of a method for entering a test mode. In the first step, it is to detect whether any non-power ground PIN pin of the chip to be tested has a negative voltage; in the second step, the delay signal of the rising edge of the power-on reset signal given after the power is powered on is used to sample the result of the first step; in the third step, the result of the sampling in the second step is latched to obtain a decision signal for entering the test mode.

[0027] Accordingly, Figure 2 It is a component of the circuit for entering the test mode proposed in the present invention. It consists of three parts: a negative pressure detection module, a sampling window module, and a sampling latch module.

[0028] The negative pressure detection module is used to detect whether a negative pressure is applied to a certain PIN pin. Figure 3 As shown, it consists of an NMOS tube, a pull-up resistor and an inverter. The drain (or source) of the NMOS tube is connected to the PIN pin; the gate of the NMOS tube is grounded; the source (or drain) of the NMOS tube is connected to the pull-up resistor and serves as the input of the inverter; the output of the inverter serves as the negative voltage detection indication result signal. If the chip to be tested needs to enter the test mode, then during the test, you only need to connect a certain PIN pin of the chip to a negative voltage (for example: -0.7V), which means that you need to enter the test mode. At this time, the negative voltage detection module will detect the negative voltage and output a high-level indication signal. When most chips are working normally, the PIN pin will not be a negative voltage, so the possibility of entering the test mode under normal operation is greatly reduced.

[0029] The sampling window module, such as Figure 4 As shown, the input and output are connected in series with an inverter, and an RC delay is added in between, that is, after the power-on reset signal of the chip is released, a delay is made for a period of time to generate a sampling window signal. The power-on reset signal is part of the chip under test. Almost all chips have a power-on reset circuit or undervoltage lockout reset circuit. Its function is to give a high-level reset release signal after the chip power supply is powered on to a certain working voltage. Therefore, it does not belong to the added part of the test circuit.

[0030] The sampling latch module is a D flip-flop. The data terminal of the D flip-flop is connected to the negative pressure indication signal output by the negative pressure detection module. The clock terminal of the D flip-flop is connected to the sampling windowing signal output by the sampling windowing module. The reset terminal is connected to the power-on reset signal. After the rising edge of the power-on reset arrives and a delay period, the result of the negative pressure detection module will be latched. Ensure that after entering the test mode, even if the negative pressure on the PIN pin is removed, the state of entering the test mode can be maintained. The overall circuit scheme is as follows: Figure 5 shown.

[0031] The embodiments of the present application provide a circuit and method for a chip to enter a test mode, which enables the chip to be tested after packaging, thereby avoiding chip parameter deviations caused by parasitic factors introduced after packaging and wire bonding, as well as packaging stress factors.

[0032] like Figure 6 The diagram of an application test scenario proposed by the present invention shows that when a three-pin chip enters the test mode, it only needs to connect one PIN pin (VOUT pin) of the chip to -0.7V, and then the chip is powered on. After the chip is powered on, the negative voltage on the PIN pin is removed, and the chip enters the test mode. When the chip wants to exit the test, it only needs to power off and then power on again when the PIN pin is not connected to the negative voltage, and the test mode can be exited and the normal working mode can be entered.

[0033] Combination Figure 5 The specific working process of the circuit is described as follows: when the input PIN pin VOUT pin is connected to -0.7V, the VGS in the NMOS tube of the negative voltage detection circuit is greater than the MOS tube's turn-on threshold voltage VTH, which will pull the pull-up resistor end, that is, the input end of the inverter, down, so that the inverter outputs a high level, indicating that the PIN pin has a negative voltage. The first condition for entering the test mode is met.

[0034] When the chip is powered on, the reset module gives the rising edge of the reset signal. After a delay of a period of time (such as 100ns, 500ns, 1us and other times) through the sampling window module, a rising edge of the sampling window signal is generated, which acts on the sampling latch module to sample and latch the negative pressure indication signal generated by the negative pressure detection circuit. The sampling latch signal is high level, and the chip enters the test mode. Then the negative pressure signal on the PIN pin can be removed to test the chip.

[0035] When it is necessary to exit the test mode, the chip power is turned off and then powered on. After a period of time after the power-on reset signal is set high, because no negative voltage is applied to the PIN pin, the negative voltage indication signal sampled by the sampling latch module is a low level, so the chip enters the normal working mode. Even if a negative voltage is applied to the PIN pin during normal operation of the chip, since the sampling window no longer exists (it is only opened at a certain moment after the power is turned on), it will not enter the test mode by mistake, which illustrates the unique advantage of this patent.

[0036] The method provided in the embodiment of the present invention only needs to reuse any non-power ground PIN pin of the chip, and can be applied to chips with only three PIN pins. It can also be widely applied to chips with any functions with more than three PIN pins. The chips and methods of the above embodiments can be combined to provide more embodiments.

[0037] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0038] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0039] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0040] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0041] The circuit system for entering the chip test mode of the present invention adopts the condition of adding negative voltage to the PIN pin as the first condition for entering the test mode. At the same time, only the moment after the rising edge of the power-on reset signal is delayed for a period of time is used as a sampling window to observe whether the first condition is met, thereby avoiding the chip from mistakenly entering the test mode when it is working normally. There is no need to add other complex conditions such as inputting a password sequence or adding filtering to the input signal. The present invention only needs to reuse any PIN pin that is not the power ground and add a negative voltage externally to achieve rapid and reliable entry into the test mode, thereby effectively saving test time and chip area, and has a wide range of practical value.

[0042] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A circuit system for implementing a chip test mode, characterized in that: The system includes a negative pressure detection module, a sampling window module and a sampling latch module. The output end of the negative pressure detection module is connected to the sampling window module, and the output end of the sampling window module is connected to the sampling latch module. The negative pressure detection module is used to detect whether negative pressure is applied to a certain PIN pin; the sampling window module is used to delay for a period of time and generate a sampling window signal after the power-on reset signal on the chip is released; the sampling latch module is used to delay and latch the result of the negative pressure detection module.

2. The circuit system for implementing entering chip test mode according to claim 1, characterized in that: The negative pressure detection module includes an NMOS tube, a pull-up resistor and a first inverter. The gate of the NMOS tube is grounded, the drain or source of the NMOS tube is connected to the PIN pin, the source or drain of the NMOS tube is connected to the pull-up resistor and serves as the input of the first inverter, and the output of the first inverter serves as an indication result signal of the negative pressure detection.

3. The circuit system for implementing entering chip test mode according to claim 2, characterized in that: If the system needs to enter the test mode, a certain PIN pin of the chip is connected to a negative pressure to enter the test mode. The negative pressure detection module detects the negative pressure and outputs a high level indication signal.

4. The circuit system for implementing entering chip test mode according to claim 1, characterized in that: The sampling windowing module includes a second inverter, a third inverter, and an RC delay circuit. The input end of the second inverter is connected to a power-on reset signal, and the output end is connected to the RC delay circuit. The output end of the RC delay circuit is connected to the third inverter, and the output end of the third inverter is connected to the sampling latch module.

5. The circuit system for implementing entering chip test mode according to claim 1, characterized in that: The sampling latch module includes a D trigger, the data end of the D trigger is connected to the negative pressure indication signal output by the negative pressure detection module, the clock end of the D trigger is connected to the sampling windowing signal output by the sampling windowing module, and the reset end is connected to the power-on reset signal; the D trigger latches the result of the negative pressure detection module after the power-on reset rising edge arrives and delays for a period of time.

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