Branch prediction method, branch predictor and electronic equipment

Abstract

The invention provides a branch prediction method, a branch predictor and electronic equipment. The branch prediction method comprises the steps that a first branch instruction is read, an execution result of the first branch instruction is predicted according to a first prediction information index, a first prediction result is obtained, and the first prediction result comprises a prediction jump direction and a prediction jump address of the first branch instruction; reading a second branch instruction and predicting an execution result of the second branch instruction to obtain a second prediction result, the second prediction result comprising a predicted jump direction and a predicted jump address of the second branch instruction, and the second branch instruction being a next branch instruction of the first branch instruction; and updating the second prediction result according to the execution result of the first branch instruction. The method is used for improving the branch prediction efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a branch prediction method, a branch predictor and an electronic device. Background Art

[0002] With the continuous evolution of computer architecture, the performance and complexity of processors are increasing. Now the processor architecture uses pipeline technology to improve the execution efficiency and throughput of the processor. Branch prediction technology is the core technology of the processor to handle branch instructions. It predicts the branch instructions in the program execution path to better execute the control flow.

[0003] Among the existing branch strategies, there are methods that store the target address of branch instructions so that the target of the branch can be quickly retrieved and predicted when the program is executed; and the integration of branch predictors improves the accuracy of prediction, but also increases hardware costs, introduces additional delays in competition and selection logic, and requires more storage to maintain the state of multiple prediction periods. RAS (Return Address Stack) is mainly used to solve the branch prediction problem of function calls and returns, but its performance is limited by the depth of the call stack. For deep recursion or complex function nesting, the capacity of RAS may not be enough to effectively predict the return address, resulting in inaccurate branch prediction.

[0004] In addition, due to the diversity of various programs, the same branch prediction algorithm may show different accuracy in branch prediction results in different programs.

[0005] Therefore, with the increase of program complexity and the change of execution environment, the existing branch prediction strategies are facing challenges. Factors such as the complexity of branch instructions and frequent program calls and returns have led to the fact that the accuracy of branch prediction technology has been continuously limited. Summary of the invention

[0006] One purpose of the present application is to provide a branch prediction method, a branch predictor and an electronic device, so as to improve the efficiency of branch prediction.

[0007] According to one aspect of an embodiment of the present application, a branch prediction method is provided, including: Reading a first branch instruction, and predicting an execution result of the first branch instruction according to a first prediction information index to obtain a first prediction result, wherein the first prediction result includes a predicted jump direction and a predicted jump address of the first branch instruction; Reading a second branch instruction and predicting an execution result of the second branch instruction to obtain a second prediction result, wherein the second prediction result includes a predicted jump direction and a predicted jump address of the second branch instruction, and the second branch instruction is a next branch instruction of the first branch instruction; The second prediction result is updated according to the execution result of the first branch instruction.

[0008] According to one aspect of an embodiment of the present application, a branch predictor is provided, including: A branch prediction module, used for receiving a branch instruction and predicting the branch instruction to obtain a prediction result, wherein the prediction result is used to indicate whether the branch instruction jumps; An instruction fetch module is used to read the branch instruction and send the branch instruction to the branch prediction module; receive the prediction result returned by the branch prediction module, and perform an instruction fetch operation of the next instruction fetch cycle according to the prediction result; The instruction execution module is used to execute the branch instruction, obtain the execution result of the branch instruction, and send the execution result to the branch prediction module, so that the branch prediction module updates the prediction result according to the execution result.

[0009] According to one aspect of an embodiment of the present application, there is provided an electronic device, including: One or more processors, wherein the processor includes the branch predictor provided by the above embodiment; A storage device is used to store one or more programs, and when the one or more programs are executed by the one or more processors, the electronic device implements the methods provided in the above-mentioned various optional implementations.

[0010] The branch prediction method provided in the embodiment of the present application reads a first branch instruction, predicts the execution result of the first branch instruction according to the first predicted branch information index, and obtains a first prediction result; reads a second branch instruction according to the first prediction result, and predicts the execution result of the second branch instruction to obtain a second prediction result, the second prediction result; updates the second prediction result according to the execution result of the first branch instruction; the branch predictor provided in another embodiment of the present application sets an instruction fetch module, a branch prediction module and an instruction execution module, reads the branch instruction through the instruction fetch module, and sends the branch instruction to the branch prediction module; the branch prediction module predicts the execution result of the branch instruction to obtain a prediction result, and returns the prediction result to the instruction fetch module, so that the instruction fetch module can perform an instruction fetch operation of the next instruction fetch cycle according to the prediction result, so that the branch prediction module can predict the execution result of the branch instruction of the next instruction fetch cycle, and can update the prediction result of the branch instruction of the next instruction fetch cycle according to the execution result of the branch instruction of the current instruction fetch cycle, thereby improving the efficiency of branch prediction and ensuring that the circuit structure used to execute the branch prediction method is simple and the hardware occupies a small area.

[0011] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0014] Figure 1 A schematic diagram of the architecture of a branch predictor proposed in an embodiment of the present application is shown.

[0015] Figure 2 A schematic diagram of the application environment of the branch predictor is shown.

[0016] Figure 3 A schematic diagram of the workflow of the branch prediction module is shown.

[0017] Figure 4 A schematic diagram showing the state transition of a two-bit saturation counter is shown.

[0018] Figure 5 A schematic flow chart of the branch prediction method provided by this embodiment is shown.

[0019] Figure 6 A schematic structural diagram of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present application will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0021] In addition, the described features, structures or characteristics may be combined in one or more example embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the example embodiments of the present application. However, those skilled in the art will appreciate that the technical solution of the present application may be practiced while omitting one or more of the specific details, or other methods, components, steps, etc. may be adopted. In other cases, known structures, methods, implementations or operations are not shown or described in detail to avoid obscuring the present application and making the various aspects of the present application obscure.

[0022] Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0023] In the design of modern processor micro-architecture, pipeline technology is used to improve the execution efficiency and throughput of the processor, and branch prediction is one of the key technologies to improve the efficiency of instruction pipeline. In pipeline technology, the processor obtains instructions in advance instead of waiting for the previous instruction to be fully completed. However, when encountering a branch instruction, the next instruction to be executed depends on the result of the branch instruction, which may cause pipeline interruption and greatly reduce the execution efficiency of the processor. Therefore, it is necessary to introduce branch prediction technology to predict the execution result of the branch instruction to meet the normal operation of the pipeline. However, for the branch prediction technology itself, a branch prediction algorithm with high accuracy means that there will be more logic circuits, occupy more silicon chip area, consume more power, and also affect the processing time of a single cycle in the processor pipeline technology. In addition, due to the diversity of software programs, the branch prediction accuracy of the same branch prediction algorithm will be different in different software programs.

[0024] This embodiment provides a branch predictor and a branch prediction method based on the branch instructions in the RV64IC instruction set, which are suitable for the branch instruction processing environment in the RISC-V processor.

[0025] There are 13 branch instructions in the RISC-V instruction set, 8 of which are in the integer instruction set RV64I and 5 in the compressed instruction set RVC.

[0026] The addressing methods of branch instructions are divided into direct addressing and indirect addressing. Direct addressing means that the jump address is the PC value of the current instruction plus the offset address information carried in the instruction. Indirect addressing means that the jump address is equal to the base address in the addressing register plus the offset address information written in the instruction.

[0027] All conditional branch instructions use direct addressing. Conditional branch instructions are used to determine the execution path of a program based on the true or false condition.

[0028] Conditional branch instructions use the global history branch prediction method. Global history branch prediction is to record the execution results of all previous conditional branch instructions using a global history register.

[0029] The global history register is a serial shift register. Whenever a conditional branch instruction is executed, the execution result is shifted into the register from the right. 1 indicates that the conditional branch instruction has jumped, and 0 indicates that the conditional branch instruction has not jumped.

[0030] Figure 1 A schematic diagram of the architecture of a branch predictor proposed in an embodiment of the present application is shown.

[0031] like Figure 1 As shown, the branch predictor includes: A branch prediction module 50 is used to receive a branch instruction and predict the branch instruction to obtain a prediction result, and the prediction result is used to indicate whether the branch instruction jumps; The instruction fetch module 10 is used to read the branch instruction and send the branch instruction to the branch prediction module 50; receive the prediction result returned by the branch prediction module 50, and perform the instruction fetch operation of the next instruction fetch cycle according to the prediction result; The instruction execution module 30 is used to execute the branch instruction, obtain the execution result of the branch instruction, and send the execution result to the branch prediction module 50, so that the branch prediction module 50 updates the prediction result according to the execution result. Specifically, the branch predictor is combined with the pipeline architecture to ensure the normal operation of the pipeline on the one hand. On the other hand, the execution result of the branch instruction is predicted by the branch predictor, and the obtained prediction result is used to guide the operation of the next branch instruction. Figure 2 A schematic diagram of the application environment of the branch predictor is shown.

[0032] like Figure 2 As shown, further, the branch predictor also includes: A fast decoding module 70, one end of which is connected to the instruction fetch module 10, and the other end of which is connected to the branch prediction module 50, is used to receive the branch instruction sent by the instruction fetch module 10, extract the instruction information of the branch instruction, and send the instruction information of the branch instruction to the branch prediction module 50.

[0033] The fast decoding module 70 is used to extract valid information from the branch instruction and send the valid information to the branch prediction module 50 .

[0034] Figure 3 A schematic diagram of the working process of the branch prediction module 50 is shown.

[0035] Furthermore, the branch prediction module 50 includes a first-level prediction unit and a second-level prediction unit, and the branch prediction module 50 stores the prediction results of the branch instructions through the first-level prediction unit and the second-level prediction unit.

[0036] The first-level prediction unit and the second-level prediction unit are branch storage units of the branch history table in the branch prediction module 50, which are used to store the prediction results of the next branch instruction according to two possible jump results, and can shield the one-cycle delay when the memory interface reads data.

[0037] Both the first-level forecasting unit and the second-level forecasting unit include: A branch direction prediction unit, the branch direction prediction unit is used to predict the jump direction of the branch instruction; A branch address prediction unit, the branch address prediction unit is used to predict the jump address of the branch instruction; The return stack is used to store the return address of branch instructions.

[0038] Specifically, the branch direction prediction unit can address a two-bit saturation counter according to the prediction index information, and obtain a prediction result about the jump direction according to the state value of the two-bit saturation counter.

[0039] There are two types of branch instructions in the RISC-V instruction set that require address prediction. The first is the jump address of the conditional branch instruction. The second is the JALR instruction in the indirect addressing mode.

[0040] The JALR (Jump And Link Register) instruction, Table 1, is used to implement operations such as function calls, indirect jumps, or dynamic jumps.

[0041] Table 1 JALR instruction encoding and return address stack execution table

[0042] Among them, rd is the destination register, which is used to store the return address; rs1 is the source register 1, which contains the base address.

[0043] The return stack is the subroutine return stack. It uses a Last In First Out (LIFO) structure. In the RISC-V architecture, there are two instructions for calling a subroutine: the JAL instruction and the JALR instruction.

[0044] The JAL (Jump And Link) instruction is used to implement a direct jump while saving the return address. It is often used for function calls and program control flow jumps.

[0045] In the RISC-V architecture, when the destination register in the JAL instruction is the x1 register or the x5 register, it means that this is the calling process of the subroutine, and the return address in the JAL instruction needs to be written to the return stack.

[0046] Furthermore, in this embodiment, a five-stage pipeline is adopted, which includes an instruction fetch module 10 , an instruction decoding module 20 , an instruction execution module 30 , a memory access module 40 and a write-back module 60 .

[0047] The branch predictor reads the branch instruction through the instruction fetch module 10 and extracts the instruction information of the branch instruction through the fast decoding module 70 .

[0048] The instruction decoding module 20 is responsible for parsing the branch instruction and determining the operation type and operand location.

[0049] The instruction execution module 30 is used to execute branch instructions, including performing operations and address calculations.

[0050] The memory access module 40 is used to access the data memory to read or write data.

[0051] The write-back module 60 writes the operation result back to the register or memory.

[0052] Pipeline technology breaks down the execution process of instructions into several stages and executes different stages of multiple instructions simultaneously to improve instruction throughput.

[0053] The branch prediction module 50 is provided with a branch history table, and the prediction information index of the branch history table is composed of a part of the PC value and the value of the global history register. The prediction information index is used to address the two-bit saturated counter value in the branch history table, and predict whether the current branch instruction will jump according to the two-bit saturated counter value.

[0054] Figure 4 Table 2 shows the corresponding relationship between the state value and the predicted behavior of the two-bit saturated counter.

[0055] Table 2 Correspondence between state value and predicted behavior

[0056] (1) Strongly Not Taken: The counter is in a saturated state and predicts that the conditional branch instruction will not take a jump. The update rule is that if the conditional branch instruction does not take a jump, keep the current state value; otherwise, change the state value to 01. (2) Weakly Not Taken: The counter is in an unsaturated state and predicts that the conditional branch instruction will not take a jump. The update rule is that if the conditional branch instruction does not take a jump, keep the current state value; otherwise, change it to 10. (3) Weakly Taken: The counter is in an unsaturated state and predicts that the conditional branch instruction will jump. The update rule is that if the conditional branch instruction jumps, the state value changes to 11; otherwise, it changes to 01. (4) Strongly Taken: The counter is in a saturated state and predicts that a conditional branch instruction will jump. The update rule is that if the conditional branch instruction jumps, keep the current state value; otherwise, change it to 10.

[0057] Based on the above content, it can be concluded that when the prediction result of the branch instruction is consistent with the execution result of the branch instruction, the two-bit saturation counter will maintain the current prediction and deepen the strength of the prediction.

[0058] When the prediction result of the branch instruction is inconsistent with the execution result of the branch instruction, the state of the two-bit saturation counter is adjusted in the opposite direction.

[0059] The branch prediction module 50 predicts the branch instruction of the next instruction fetch cycle by using the value of the global history register.

[0060] Assume that the branch instruction of the current cycle is A4 and the value of the global history register (GHR) is 0101.

[0061] For the next branch instruction A5, the value of GHR is one of 01010 and 01011. 01010 indicates that the execution result of A4 is no jump, and 01011 indicates that the execution result of A4 is a jump.

[0062] In the cycle of predicting A4, a read access to the branch history table can be initiated based on the GHR value of branch instruction A4, that is, the prediction result of branch instruction A5 can be obtained.

[0063] Because memory reads are delayed by one cycle, even if A4 and A5 are executed continuously, A5 can obtain its predicted result in the cycle when A4 is executed.

[0064] Figure 5 FIG. 2 is a flow chart of the branch prediction method provided in this embodiment. The branch prediction method can be applied to the branch predictor provided in the above embodiment. Figure 5 As shown, the method includes: S100, reading a first branch instruction, predicting an execution result of the first branch instruction according to a first prediction information index, and obtaining a first prediction result, wherein the first prediction result includes a predicted jump direction and a predicted jump address of the first branch instruction.

[0065] S200, read the second branch instruction and predict the execution result of the second branch instruction to obtain a second prediction result, the second prediction result includes the predicted jump direction and predicted jump address of the second branch instruction, and the second branch instruction is the next branch instruction of the first branch instruction.

[0066] S300, updating the second prediction result according to the execution result of the first branch instruction.

[0067] Specifically, the first prediction information index is formed by concatenating a partial PC value and a storage value of a global history register, and predicts the execution result of the first branch instruction to obtain a first prediction result.

[0068] When executing an instruction, the instruction fetch module 10 fetches the instruction pointed to by the program counter (PC) from the memory, processes the instruction according to the PC value processing method of the branch instruction, passes the current PC value to the branch prediction module 50, and updates the PC value according to the prediction result of the branch prediction module 50.

[0069] When the instruction fetch module 10 fetches the instruction to be executed in the memory and the instruction is a branch instruction, the instruction is sent to the branch prediction module 50. The branch prediction module 50 predicts the execution result of the branch instruction and obtains a first prediction result. The first prediction result includes a predicted jump direction and a predicted jump address. The branch prediction module 50 then returns the first prediction result to the instruction fetch module 10.

[0070] At the instruction fetch module 10 stage, if the first prediction result indicates that the first branch instruction jumps, the instruction fetch module 10 will jump to the predicted jump address included in the first prediction result. If the first prediction result indicates that the first branch instruction does not jump, the instruction fetch module 10 continues to fetch instructions from sequential addresses.

[0071] In the instruction fetch cycle of the next instruction, namely the second branch instruction, access to the branch history table can be initiated based on the first prediction result to obtain a second prediction result, which includes a predicted jump address and a predicted jump direction of the second branch instruction.

[0072] In the cycle of processing the first branch instruction, when the instruction fetch module obtains the next instruction according to the first prediction unit, the first branch instruction is decoded by the instruction decoding module and the operand is read from the register. In the cycle, the instruction execution module 30 determines whether the values ​​of the two registers meet the branch condition. If the condition is met, the jump is executed; if not, the sequential instruction is continued to be executed.

[0073] In this embodiment, the instruction execution module 30 returns the execution result of the first branch instruction to the branch prediction module 50. After receiving the execution result, the branch prediction module 50 updates the prediction result of the second branch instruction.

[0074] After the instruction fetch module obtains the first branch instruction according to the PC value, the PC value and other instruction codes of the first branch instruction are sent to the branch prediction module 50. The branch prediction module 50 splices the first prediction information index according to the partial PC value and the value of the global history register. The first prediction information index is used to initiate a read access to the branch history table, and then address the two-bit saturation counter, and predict the execution result of the first branch instruction according to the state value of the two-bit saturation counter.

[0075] The jump results of historical branch instructions are recorded through the global history register.

[0076] For example, for the first branch instruction, the value of the global history register is 0101.

[0077] For the second branch instruction, the value of the global history register is 01011 or 01010, which are respectively concatenated with a part of the PC value to obtain two prediction results for the second branch instruction, namely, 0 and 1.

[0078] Two prediction units are reserved in the branch prediction module 50 to store two prediction results of the second branch instruction respectively.

[0079] When the branch prediction module 50 receives the execution result of the first branch instruction, it first determines the jump result of the first branch instruction according to the execution result, and updates the state value of the two-bit saturated counter according to the jump result. The change of the state value of the two-bit saturated counter may affect the second prediction result. Therefore, it is necessary to update the second prediction result according to the execution result of the first branch instruction.

[0080] Further, S100, reading a first branch instruction, and predicting an execution result of the first branch instruction according to a first prediction information index to obtain a first prediction result, including: S110, obtaining a first prediction information index, and predicting a predicted jump direction of a first branch instruction according to the first prediction information index.

[0081] S120, obtaining a predicted jump address of the first branch instruction according to the instruction type of the first branch instruction.

[0082] The state value of the two-bit saturated counter in the addressing branch history table is indexed according to the first prediction information to obtain a prediction result about the jump direction, and the predicted jump address of the first branch instruction is calculated according to the prediction result of the jump direction and the instruction type of the first branch instruction.

[0083] For example, there are two types of branch instructions in RISC-V that require address prediction. The first is the jump address of the conditional branch instruction; the second is the JALR instruction in the indirect addressing mode.

[0084] The instruction fetch module 10 can fetch the instruction after the first branch instruction jumps according to the predicted jump address, thereby reducing delay.

[0085] Further, S120, obtaining a first prediction information index, and predicting a predicted jump direction of the first branch instruction according to the first prediction information index, including: S1201, obtain the instruction address value and global historical data value stored in the program counter register.

[0086] S1203, concatenate the instruction address value with the global historical data value to obtain a first prediction information index.

[0087] S1205, obtain saturation count data based on the first prediction information index addressing, and obtain the predicted jump direction of the first branch instruction according to the saturation count data.

[0088] Specifically, the saturation count data refers to the state value of a two-bit saturation counter in this embodiment.

[0089] The program counter register, also known as the program counter, is an important register in the processor that is used to store the address value of the instruction currently being executed.

[0090] The first prediction information index addresses a two-bit saturation counter in the branch history table, and predicts the predicted jump direction of the first branch instruction according to the saturation count data of the two-bit saturation counter.

[0091] Further, S200, reading the second branch instruction and predicting the execution result of the second branch instruction to obtain a second prediction result includes: S210, generating a second prediction information index according to the predicted jump direction in the first prediction result and the first prediction information index.

[0092] S220, based on the second prediction information index, obtain the predicted jump direction of the second branch instruction.

[0093] S230, obtaining a predicted jump address of the second branch instruction according to the instruction type of the second branch instruction.

[0094] The execution result prediction method of the second branch instruction is the same as that of the first branch instruction.

[0095] The second branch instruction is the next branch instruction of the first branch instruction. When generating the second prediction information index, it is necessary to include a global historical data value recording the execution result of the first branch instruction.

[0096] In order to reduce delay, the second branch instruction is predicted without waiting for the first branch instruction to be executed.

[0097] The second branch instruction is predicted according to two possible values ​​of the global history data respectively to obtain a second prediction unit.

[0098] Since the memory read instruction will be delayed by one cycle, even if the first branch instruction and the second branch instruction are executed continuously, the prediction result of the second branch instruction can be obtained in the current cycle. Furthermore, the second prediction information index needs to be updated according to the execution result of the first branch instruction, including: After the first branch instruction is executed, the execution result of the first branch instruction is obtained.

[0099] The second prediction information index is updated according to the execution result of the first branch instruction.

[0100] If the actual jump direction of the first branch instruction is inconsistent with the predicted jump direction of the first branch instruction, a pipeline refresh operation is performed and the first branch instruction is re-executed.

[0101] Furthermore, the change in the state value of the two-bit saturated counter may affect the second prediction result. Figure 4 From the contents of Table 2, it can be concluded that when the two-bit saturated counter is in saturation state, two consecutive prediction failures will change the prediction result.

[0102] This means that when predicting the first branch instruction, the two-bit saturation counter is in a saturated state; and when predicting the second branch instruction, the predicted jump result of the second branch instruction will be consistent with the predicted jump result of the first branch instruction. If the execution result of the first branch instruction is different from the predicted result, the state value will be updated to an unsaturated state consistent with the predicted behavior, which will not affect the predicted result of the second branch instruction.

[0103] However, the second prediction result of the second branch instruction is not obtained based on the prediction result of the first branch instruction, but is obtained by addressing the global history table value of the first branch instruction as the second prediction information index, and when the execution result of the second branch instruction is predicted, the first branch instruction has not yet been executed. After the first branch instruction is executed, the value of the global history register is updated according to the execution result of the first branch instruction, and the second prediction result returned by the branch direction prediction unit to the instruction fetch module 10 is adjusted.

[0104] This embodiment chooses to update in the execution stage, and a prediction error of the first branch instruction will only affect the refresh of the first branch instruction and the next instruction of the execution result of the branch instruction.

[0105] However, the branch predictor provided in this embodiment has a simple structure, reduces the storage size of the branch history table, and is suitable for embedded processors that are sensitive to silicon chip area and power consumption; the branch prediction method provided in this embodiment is applied to the branch predictor, which can reduce the pipeline delay.

[0106] Reference below Figure 6 An electronic device 80 according to an embodiment of the present application is described. Figure 6 The electronic device 80 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0107] like Figure 6 As shown, the electronic device 80 is in the form of a general computing device. The components of the electronic device 80 may include but are not limited to: at least one processing unit 510, at least one storage unit 520, and a bus 530 connecting different system components (including the storage unit 520 and the processing unit 510).

[0108] The storage unit stores program codes, which can be executed by the processing unit 510, so that the processing unit 510 executes the steps according to various exemplary embodiments of the present application described in the description of the exemplary method described above in this specification. For example, the processing unit 510 can execute the following steps: Figure 1 The steps shown in .

[0109] The storage unit 520 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 5201 and / or a cache storage unit 5202 , and may further include a read-only storage unit (ROM) 5203 .

[0110] The storage unit 520 may also include a program / utility 5204 having a set (at least one) of program modules 5205, such program modules 5205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0111] Bus 530 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0112] The electronic device 80 may also communicate with one or more external devices 600 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 80, and / or may communicate with any device that enables the electronic device 80 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 550. The input / output (I / O) interface 550 is connected to a display unit 540. In addition, the electronic device 80 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 560. As shown, the network adapter 560 communicates with other modules of the electronic device 80 via a bus 530. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 80, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0113] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solution according to the implementation method of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a mobile terminal, etc.) to execute the branch prediction method according to the implementation method of the present application.

[0114] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units. In addition, although the steps of the method in the present application are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0115] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation method of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a mobile terminal, etc.) to execute the method according to the implementation method of the present application.

[0116] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the appended claims.

Claims

1. A branch prediction method, characterized in that: The method comprises: Reading a first branch instruction, and predicting an execution result of the first branch instruction according to a first prediction information index to obtain a first prediction result, wherein the first prediction result includes a predicted jump direction and a predicted jump address of the first branch instruction; Reading a second branch instruction and predicting an execution result of the second branch instruction to obtain a second prediction result, wherein the second prediction result includes a predicted jump direction and a predicted jump address of the second branch instruction, and the second branch instruction is a next branch instruction of the first branch instruction; The second prediction result is updated according to the execution result of the first branch instruction.

2. The branch prediction method according to claim 1, characterized in that: The reading of the first branch instruction and predicting the execution result of the first branch instruction according to the first prediction information index to obtain a first prediction result include: Obtaining the first prediction information index, and predicting a predicted jump direction of the first branch instruction according to the first prediction information index; According to the instruction type of the first branch instruction, a predicted jump address of the first branch instruction is obtained.

3. The branch prediction method according to claim 2, characterized in that: The obtaining the first prediction information index and predicting the predicted jump direction of the first branch instruction according to the first prediction information index includes: Get the instruction address value and global history data value stored in the program counter register; Concatenate the instruction address value with the global historical data value to obtain the first prediction information index; Saturation count data is obtained based on the first prediction information index addressing, and the predicted jump direction of the first branch instruction is obtained according to the saturation count data.

4. The branch prediction method according to claim 1, characterized in that: The reading the second branch instruction and predicting the execution result of the second branch instruction to obtain a second prediction result includes: generating a second prediction information index according to the predicted jump direction in the first prediction result and the first prediction information index; Based on the second prediction information index, obtaining a predicted jump direction of the second branch instruction; According to the instruction type of the second branch instruction, a predicted jump address of the second branch instruction is obtained.

5. The branch prediction method according to claim 4, characterized in that: The updating of the second prediction result according to the execution result of the first branch instruction includes: After the execution of the first branch instruction is completed, obtaining the execution result of the first branch instruction; The second prediction information index is updated according to the execution result of the first branch instruction.

6. The branch prediction method according to claim 5, characterized in that: The execution result includes an actual jump direction and an actual jump address of the first branch instruction. After the second prediction result is updated according to the execution result of the first branch instruction, the method further includes: If the actual jump direction of the first branch instruction is inconsistent with the predicted jump direction of the first branch instruction, a pipeline refresh operation is performed and the first branch instruction is re-executed.

7. A branch predictor, characterized in that: The branch predictor comprises: A branch prediction module, used for receiving a branch instruction and predicting the branch instruction to obtain a prediction result, wherein the prediction result is used to indicate whether the branch instruction jumps; An instruction fetch module is used to read the branch instruction and send the branch instruction to the branch prediction module; receive the prediction result returned by the branch prediction module, and perform an instruction fetch operation of the next instruction fetch cycle according to the prediction result; The instruction execution module is used to execute the branch instruction, obtain the execution result of the branch instruction, and send the execution result to the branch prediction module, so that the branch prediction module updates the prediction result according to the execution result.

8. The branch predictor according to claim 7, characterized in that: The branch prediction module comprises a first-level prediction unit and a second-level prediction unit, and the branch prediction module stores the prediction result of the branch instruction through the first-level prediction unit and the second-level prediction unit; The first-level prediction unit and the second-level prediction unit both include: A branch direction prediction unit, the branch direction prediction unit is used to predict the jump direction of the branch instruction; A branch address prediction unit, the branch address prediction unit is used to predict the jump address of the branch instruction; The return stack is used to store the return address of the branch instruction.

9. The branch predictor according to claim 7, characterized in that: The branch predictor also includes: A fast decoding module, one end of which is connected to the instruction fetch module, and the other end of which is connected to the branch prediction module, for receiving the branch instruction sent by the instruction fetch module, extracting the instruction information of the branch instruction, and sending the instruction information of the branch instruction to the branch prediction module.

10. An electronic device, characterized in that: include: One or more processors, the processor comprising a branch predictor as claimed in any one of claims 7 to 9; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the branch prediction method according to any one of claims 1 to 6.

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