Method for expanding grinding window of metal gate layer

Abstract

The invention provides a method for expanding a grinding window of a metal gate layer, which comprises the following steps of: providing a substrate, forming pseudo gate structures with different lengths on a long channel device region and a short channel device region on the substrate, and forming an etching stop layer covering the pseudo gate structures; a first interlayer dielectric layer with a preset thickness is formed on the etching stop layer, and then a second interlayer dielectric layer covering the pseudo gate structures is formed on the first interlayer dielectric layer, so that only the first interlayer dielectric layer is filled in a narrower gap between part of the pseudo gate structures; a first interlayer dielectric layer and a second interlayer dielectric layer are filled in wider gaps among part of the pseudo gate structures, and the grinding rate of the second interlayer dielectric layer is slower than that of the first interlayer dielectric layer; grinding the first interlayer dielectric layer and the second interlayer dielectric layer to the pseudo gate polycrystalline silicon layer; and removing the pseudo gate polycrystalline silicon layer to form a groove, forming a metal gate layer for filling the groove, and grinding the metal gate layer to a required height. According to the invention, the dished defect degree after the second interlayer dielectric layer is ground is reduced, and the problem that a subsequent process window is too small is avoided.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for enlarging a metal gate layer grinding window. Background Art

[0002] After the source and drain regions are formed, silicon nitride and silicon oxide masks of varying thickness will remain on the polysilicon gates in different regions. Currently, the photoresist etch-back (PREB) process is used to remove the masks on the gates. However, due to process bottlenecks, even after optimization, the height difference of the silicon nitride sidewalls of N / P MOS, for example, is still about 100 angstroms.

[0003] The prior art method for forming a metal gate includes:

[0004] Step 1: providing a substrate 101, forming dummy gate structures of different lengths on the long channel device regions and the short channel device regions on the substrate 101, wherein the dummy gate structures include a dummy gate polysilicon layer 103 and a sidewall structure 104 located on the dummy gate polysilicon layer 103, and forming an etch stop layer 105 covering the dummy gate structures;

[0005] Step 2: forming an interlayer dielectric layer 106 covering the dummy gate structure, forming Figure 1 The structure shown;

[0006] Step 3: Grind the interlayer dielectric layer 106 onto the pseudo gate polysilicon layer 103 to form Figure 2 In the structure shown, in order to cover the height difference of the photoresist back etching and ensure that the pseudo gate polysilicon layer 103 is completely opened, over polishing is required, which leads to serious dishing in the large dielectric layer area;

[0007] Step 4: remove the pseudo gate polysilicon layer 103 to form a groove, and form a metal gate layer 107 filling the groove, so as to form a Figure 3 The structure shown in FIG. 1 is formed by grinding the metal gate layer 107 to a desired height. Figure 4 The structure shown. In order to ensure that the metal on the interlayer dielectric layer 106 is ground clean, the metal gate layer 107 also needs to be over-grinded, which results in a poor level of metal scratch defects. In addition, since a high selectivity grinding liquid (e.g., AL:OX≈100:1) is used to grind the metal gate layer 107, the grinding rate of the long channel area is faster than that of the narrow channel area. Finally, the long channel area will be ground to a lower position (about 70 angstroms lower), which cannot meet the process requirements.

[0008] In order to solve the above problems, it is necessary to propose a new method for expanding the metal gate layer grinding window. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for expanding the metal gate layer grinding window, so as to solve the problem in the prior art that grinding of the interlayer dielectric layer may form a large depression, affecting the subsequent process window.

[0010] To achieve the above objectives and other related objectives, the present invention provides a method for expanding a metal gate layer polishing window, comprising:

[0011] Step 1: providing a substrate, forming dummy gate structures of different lengths on the long channel device regions and the short channel device regions on the substrate, wherein the dummy gate structures include a dummy gate polysilicon layer and a sidewall structure located on the dummy gate polysilicon layer, and forming an etch stop layer covering the dummy gate structures;

[0012] Step 2: forming a first interlayer dielectric layer of a preset thickness on the etch stop layer, and then forming a second interlayer dielectric layer covering the dummy gate structure on the first interlayer dielectric layer, so that the narrower gaps between some of the dummy gate structures are filled with only the first interlayer dielectric layer, and the wider gaps between some of the dummy gate structures are filled with the first and second interlayer dielectric layers, and the polishing rate of the second interlayer dielectric layer is slower than that of the first interlayer dielectric layer;

[0013] Step 3, grinding the first and second interlayer dielectric layers onto the dummy gate polysilicon layer;

[0014] Step 4: remove the dummy gate polysilicon layer to form a groove, form a metal gate layer filling the groove, and grind the metal gate layer to a desired height.

[0015] Preferably, a pad oxide layer is also formed on the substrate in step one, and the dummy gate structure is formed on the pad oxide layer.

[0016] Preferably, the material of the etch stop layer in step one is silicon nitride.

[0017] Preferably, the first interlayer dielectric layer in step 2 is an oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

[0018] Preferably, the second interlayer dielectric layer in step 2 is an oxide layer formed by plasma enhanced chemical vapor deposition.

[0019] Preferably, the grinding method in step three is chemical mechanical planarization grinding.

[0020] Preferably, in step four, the dummy gate polysilicon layer is removed by wet etching.

[0021] Preferably, before forming the metal gate layer in step four, the method further includes forming an interface layer, a high-K dielectric layer, a bottom isolation layer, a work function metal layer and a top isolation layer in the groove.

[0022] Preferably, the material of the metal gate layer in step 4 is Al.

[0023] Preferably, the grinding method in step 4 is chemical mechanical planarization grinding.

[0024] As described above, the method for enlarging the metal gate layer grinding window of the present invention has the following beneficial effects:

[0025] The present invention reduces the degree of dish-shaped defects after grinding the second interlayer dielectric layer, so that less metal gate layer remains there, thereby increasing the process window of the metal gate layer residue thereafter, and the over-grinding time can be reduced, and finally the metal gate layer grinding scratch defect can be improved; in addition, the second interlayer dielectric layer is ground in the long channel device area, and the first interlayer dielectric layer is ground in the long channel device area, and the grinding rate difference between the long and short channel device areas is reduced, and finally the gate height difference between the long and short channel device areas can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of forming an interlayer dielectric layer in the prior art;

[0027] Figure 2 A schematic diagram of the prior art of grinding to expose the pseudo gate polysilicon layer is shown;

[0028] Figure 3 It is a schematic diagram of forming a metal gate layer in the prior art;

[0029] Figure 4 A schematic diagram of a prior art metal gate layer grinding is shown;

[0030] Figure 5 Shown is a schematic diagram of the process flow of the present invention;

[0031] Figure 6 It is a schematic diagram showing the formation of the first and second interlayer dielectric layers of the present invention;

[0032] Figure 7 It is a schematic diagram showing the present invention of grinding until the pseudo gate polysilicon layer is exposed;

[0033] Figure 8 It is a schematic diagram of forming a metal gate layer according to the present invention;

[0034] Fig. 9 It is a schematic diagram of polishing the metal gate layer of the present invention. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] See also Figure 5 The present invention provides a method for expanding a metal gate layer grinding window, comprising:

[0037] Step 1: providing a substrate 201, forming dummy gate structures of different lengths on the long channel device regions and the short channel device regions on the substrate 201, wherein the dummy gate structures include a dummy gate polysilicon layer 203 and a sidewall structure 204 located on the dummy gate polysilicon layer 203, and forming an etch stop layer 205 covering the dummy gate structures;

[0038] In some embodiments, a pad oxide layer 202 is further formed on the substrate 201 in step 1, and the dummy gate structure is formed on the pad oxide layer 202 .

[0039] In some embodiments, the material of the etch stop layer 205 in step 1 is silicon nitride.

[0040] Step 2: forming a first interlayer dielectric layer 206 of a preset thickness on the etch stop layer 205, and then forming a second interlayer dielectric layer 207 covering the dummy gate structure on the first interlayer dielectric layer 206, so that the narrow gaps between some dummy gate structures are filled with only the first interlayer dielectric layer 206, and the wider gaps between some dummy gate structures are filled with the first and second interlayer dielectric layers, and the polishing rate of the second interlayer dielectric layer 207 is slower than that of the first interlayer dielectric layer 206;

[0041] In some embodiments, the first interlayer dielectric layer 206 in step 2 is an oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

[0042] In some embodiments, the second interlayer dielectric layer 207 in step 2 is an oxide layer formed by plasma enhanced chemical vapor deposition, which is harder than an oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

[0043] Step 3, grinding the first and second interlayer dielectric layers onto the dummy gate polysilicon layer 203. This step requires grinding until the dummy gate polysilicon layer 203 is completely exposed. Since the grinding rate of the second interlayer dielectric layer 207 is slower than that of the first interlayer dielectric layer 206, the dishing defect degree of the second interlayer dielectric layer 207 at the wider gap after grinding can be reduced.

[0044] In some embodiments, the polishing method in step three is chemical mechanical planarization polishing.

[0045] Step 4: remove the pseudo gate polysilicon layer 203 to form a groove, form a metal gate layer 208 filling the groove, and grind the metal gate layer 208 to the required height. Since the dishing defect degree is reduced in step 3, less metal remains there, thereby increasing the process window of the metal residue later, and the over-grinding time can be reduced, and finally the metal grinding scratch defect can be improved; in addition, the second interlayer dielectric layer 207 is ground in the long channel device area, and the first interlayer dielectric layer 206 is ground in the long channel device area, and the grinding rate difference between the long and short channel device areas is reduced, and finally the gate height difference between the long and short channel device areas can also be improved.

[0046] In some embodiments, in step 4, the dummy gate polysilicon layer 203 is removed by wet etching.

[0047] In some embodiments, before forming the metal gate layer 208 in step four, the step of forming an interface layer, a high-K dielectric layer, a bottom isolation layer, a work function metal layer and a top isolation layer in the groove is also included. This is a common MOS structure in the prior art and will not be described in detail here.

[0048] The interface layer may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SION). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0049] The work function metal layer may include a work function metal to provide a suitable work function for the high-k / metal gate structure.

[0050] The bottom isolation layer and the top isolation layer may be titanium nitride or other suitable materials.

[0051] In some embodiments, the material of the metal gate layer 208 in step 4 is Al. In other embodiments, the material of the metal gate layer 208 may also be tungsten, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0052] In some embodiments, the polishing method in step 4 is chemical mechanical planarization polishing.

[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] In summary, the present invention reduces the degree of dishing defects after grinding the second interlayer dielectric layer, so that the metal gate layer remaining there is less, thereby increasing the process window of the metal gate layer residue, and the over-grinding time can be reduced, and finally the metal gate layer grinding scratch defect can be improved; in addition, the second interlayer dielectric layer is ground in the long channel device area, and the first interlayer dielectric layer is ground in the long channel device area, and the grinding rate difference between the long and short channel device areas is reduced, and finally the gate height difference between the long and short channel device areas can also be improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for enlarging a metal gate layer grinding window, characterized in that: At least: Step 1: providing a substrate, forming dummy gate structures of different lengths on the long channel device regions and the short channel device regions on the substrate, wherein the dummy gate structures include a dummy gate polysilicon layer and a sidewall structure located on the dummy gate polysilicon layer, and forming an etch stop layer covering the dummy gate structures; Step 2: forming a first interlayer dielectric layer of a preset thickness on the etch stop layer, and then forming a second interlayer dielectric layer covering the dummy gate structure on the first interlayer dielectric layer, so that the narrower gaps between some of the dummy gate structures are filled with only the first interlayer dielectric layer, and the wider gaps between some of the dummy gate structures are filled with the first and second interlayer dielectric layers, and the polishing rate of the second interlayer dielectric layer is slower than that of the first interlayer dielectric layer; Step 3, grinding the first and second interlayer dielectric layers onto the dummy gate polysilicon layer; Step 4: remove the dummy gate polysilicon layer to form a groove, form a metal gate layer filling the groove, and grind the metal gate layer to a desired height.

2. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: A pad oxide layer is also formed on the substrate in step one, and the dummy gate structure is formed on the pad oxide layer.

3. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: The material of the etching stop layer in step 1 is silicon nitride.

4. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: The first interlayer dielectric layer in step 2 is an oxide layer formed by sub-atmospheric pressure chemical vapor deposition.

5. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: The second interlayer dielectric layer in step 2 is an oxide layer formed by plasma enhanced chemical vapor deposition.

6. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: The grinding method in step three is chemical mechanical planarization grinding.

7. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: In step 4, the dummy gate polysilicon layer is removed by wet etching.

8. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: Before forming the metal gate layer in step 4, the method further includes forming an interface layer, a high-K dielectric layer, a bottom isolation layer, a work function metal layer and a top isolation layer in the groove.

9. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: The material of the metal gate layer in step 4 is Al.

10. The method for enlarging the metal gate layer grinding window according to claim 1, characterized in that: The grinding method in step 4 is chemical mechanical planarization grinding.

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