Device and method for detecting key signal of Loran C

Abstract

The invention discloses a Roland C key signal detection device, which comprises an input circuit, a counter, a state marker register and an anomaly detection circuit, and also provides a Roland C key signal detection method, which comprises the following steps: detecting a rising edge of a serial data signal SERDA by using the input circuit so as to control the counter and the anomaly detection circuit; the anomaly detection circuit detects count values output by the counter so as to detect whether a serial data signal SERDA sequentially comprises four single pulses, namely a starting pulse STP, a charging trigger pulse Charge, a discharging trigger pulse DCTrig and a magnetic pulser reference pulse MEGREF, and time corresponding to the count values of the four single pulses is within a count value threshold interval corresponding to each single pulse. Therefore, the integrity of the serial data signal SERDA is judged. According to the invention, the problem of monitoring the SERDA signal in the Rowland wave transmission control system is effectively solved, and the normal operation of the transmission control system is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, in particular to a device for detecting a Loran C key signal, and also to a method for detecting a Loran C key signal. Background Art

[0002] The Loran-C navigation system is a large-scale long-range, high-precision radio navigation system with a range of up to 2,000 kilometers and an operating frequency of 100kHz. The basic components of the system include ground facilities, user equipment, and communication media. The ground facilities consist of a transmitter, a work area monitoring station, and a station chain control center. The transmitter transmits radio navigation signals, while the work area monitoring station and the station chain control center ensure that the signals meet the system requirements. Although satellite navigation systems have been widely used, their anti-interference ability is low, so relying solely on satellite navigation systems is not reliable. In contrast, the Loran-C system has higher signal power and anti-interference ability, and has become one of the familiar and reliable navigation methods. Many countries use the Loran-C system as a backup system for satellite navigation systems to ensure the continuity of navigation services for transportation. In addition, the Loran-C system is also widely used in national time service systems, and its timing function and performance have been further improved through continuous technical improvements.

[0003] The serial data signal (SERDA) is generated by the timing pulse control unit in the Roland C control cabinet. It contains all the timing and amplitude control information required by the half-cycle power generation unit (HCG) of the Roland C transmitter. In the entire broadcast control system, there are four serial data signals SERDA with exactly the same signal format. Figure 1 Shown is a waveform of a serial data signal SERDA.

[0004] All pulses and data bits in the serial data signal SERDA are 5μs in length. The start pulse (STP) is the first single pulse of the serial data signal SERDA. The charge trigger pulse (CHARGE) is the second single pulse of the serial data signal SERDA. It is located after the start pulse STP, so that the HCG half-cycle power generation unit starts charging. The eight-bit digital amplitude reference (DAR) is 8-bit data, which is delayed by 60μs relative to the start pulse STP. The eight-bit digital amplitude reference DAR controls the charging time of the HCG half-cycle power generation unit capacitor, thereby controlling the voltage of the HCG half-cycle power generation unit storage capacitor, and then controlling the amplitude of the half-cycle pulse generated by each HCG half-cycle power generation unit. The seven-bit amplitude compensation delay (ACD) is delayed by 160μs relative to the start pulse STP. It is a signal in the timing control loop of the HCG half-cycle power generation unit, and its function is to adjust the timing of the half-cycle pulse. The one-bit A-rate phase code (φA) after the seven-bit amplitude compensation delay ACD is controlled by the phase code square wave of the timing logic. When the signal is an A-rate positive phase code square wave, the bit is positive, otherwise it is negative. The discharge trigger pulse (DC_Trig) and the magnetic pulser reference pulse (MEG_REF) are delayed by 375μs and 405μs respectively relative to the start pulse STP signal. The magnetic pulser reference pulse (MEG_REF) corrects the timing of the discharge trigger pulse in the serial data signal SERDA, thereby ensuring that the time of the half-cycle pulse generated by the HCG half-cycle power generation unit triggered by the same serial data signal SERDA is the same.

[0005] The serial data signal SERDA is a key signal that controls the subsequent transmitter to generate the Loran waveform and transmit it, and plays a key role in the entire Loran C system. If there is an error in the serial data signal SERDA, it may not only damage the subsequent transmitter, but also affect the use of the Loran C user. Therefore, it is necessary to monitor the serial data signal SERDA. However, there is currently no method or device for monitoring the serial data signal SERDA. Summary of the invention

[0006] The purpose of the present invention is to provide a device for detecting a Loran C key signal in view of the deficiencies of the existing key signal detection technology, and also to provide a method for detecting a Loran C key signal. The method can measure the relative phase of four single pulses in a serial data signal SERDA, and can sample two eight-bit data values ​​at the same time to monitor the serial data signal SERDA.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A device for detecting a Roland C key signal includes an input circuit, the input circuit captures a serial data signal SERDA, and when the input circuit detects the first rising edge in the serial data signal SERDA, sends a count enable signal to a counter; whenever the input circuit detects a rising edge in the serial data signal SERDA, it sends a detection enable signal to an abnormality detection circuit;

[0009] The counter receives a clock signal and a count enable signal from a clock source, starts to count continuously when the counter receives the count enable signal, and sends the count value count1 to the abnormality detection circuit in sequence;

[0010] The abnormality detection circuit determines, according to the received detection enable signal and the count value count1, whether the serial data signal SERDA includes four single pulses, namely, the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF, and the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse. According to the judgment result, the abnormality detection circuit outputs a flag setting signal corresponding to each single pulse and a flag setting signal corresponding to the integrity error flag SERDA_Integrity_Error to the status flag register, thereby setting the flag corresponding to the single pulse and the integrity error flag SERDA_Integrity_Error;

[0011] The reset control circuit selects whether to send a reset execution signal to the counter and the status flag register according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register;

[0012] The external monitoring control unit controls the link switch between the input circuit and the HCG half-cycle power generation unit according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register.

[0013] As mentioned above, the counting value threshold intervals corresponding to each single pulse include:

[0014] The charge trigger pulse count threshold interval Charge_thr represents the time limit corresponding to the count value countl corresponding to the rising edge of the charge trigger pulse, corresponding to the charge trigger pulse Charge;

[0015] The discharge trigger pulse count threshold interval DC_Trig_thr represents the time limit corresponding to the count value count1 corresponding to the rising edge of the discharge trigger pulse, corresponding to the discharge trigger pulse DC_Trig;

[0016] The magnetic pulser reference pulse counting threshold interval MEG_REF_thr represents the time limit corresponding to the count value countl corresponding to the rising edge of the magnetic pulser reference pulse, corresponding to the magnetic pulser reference pulse MEG_REF;

[0017] The flag bits corresponding to each single pulse in the serial data signal SERDA include:

[0018] The start pulse flag Find_STP_Flag corresponds to the start pulse STP;

[0019] The charge trigger pulse flag bit Find_Charge_Flag corresponds to the charge trigger pulse Charge;

[0020] The discharge trigger pulse flag Find_DC_Trig_Flag corresponds to the discharge trigger pulse DC_Trig;

[0021] The magnetic pulser reference pulse flag Find_MEG_REF_Flag corresponds to the magnetic pulser reference pulse MEG_REF.

[0022] As mentioned above, the input circuit adopts a three-stage shift register structure.

[0023] The device for detecting a Roland C key signal as described above also includes a sampling circuit and an output circuit.

[0024] The sampling circuit receives the clock signal from the clock source, and according to the flag bits corresponding to the start pulse STP and the charge trigger pulse Charge, selects whether to sample and temporarily store the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA;

[0025] The output circuit reads the flag bits corresponding to each single pulse of the status flag register and the value of the integrity error flag bit SERDA_Integrity_Error, and selects whether to transmit the data temporarily stored in the counter, sampling circuit and status flag register to the external monitoring control unit;

[0026] The data temporarily stored in the counter are: the count value count1 corresponding to the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF;

[0027] The data temporarily stored in the sampling circuit are: eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD and one-bit A-rate phase code φA;

[0028] The data temporarily stored in the status flag register are: the flag bits corresponding to each single pulse and the value of the integrity error flag bit SERDA_Integrity_Error;

[0029] The reset control circuit selects whether to send a reset execution signal to the sampling circuit according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register.

[0030] A method for detecting a Loran C key signal, using the device for detecting a Loran C key signal as described above, is characterized by comprising the following steps:

[0031] Step 1, setting the count value threshold interval and the maximum count value threshold count_max corresponding to each single pulse in the abnormality detection circuit, and setting the preset sampling time point in the sampling circuit;

[0032] Step 2: Set the link switch to off;

[0033] Step 3, resetting and initializing the count value count1 in the counter, the register of the sampling circuit, and all the flag bits in the status flag register through the reset control circuit;

[0034] Step 4, the input circuit captures the serial data signal SERDA and detects the rising edge in the serial data signal SERDA, the counter starts counting, the abnormality detection circuit detects the starting pulse STP, the charging trigger pulse Charge, the discharging trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF in the serial data signal SERDA through the count value count1 output by the counter, and determines whether the serial data signal SERDA is complete. If the serial data signal SERDA is complete, that is, the serial data signal SERDA includes four single pulses, namely, the starting pulse STP, the charging trigger pulse Charge, the discharging trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF, and the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse, then step 5 is executed; if any of the starting pulse STP, the charging trigger pulse Charge, the discharging trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF is not detected, then return to step 3;

[0035] Step 5: The external monitoring control unit turns on the link switch so that the complete and normal serial data signal SERDA in the input circuit is input into the HCG half-cycle power generation unit of the corresponding Loran C transmitter, and then returns to step 2.

[0036] As described above in step 1, the maximum count value threshold count_max is set to be the maximum interval time between the two preceding and following serial data signals SERDA of the same path.

[0037] As mentioned in step 1,

[0038] Set the lower limit Charge_thr_l of the charge trigger pulse count threshold interval Charge_thr to be greater than 5μs, and the upper limit Charge_thr_h of the charge trigger pulse count threshold interval Charge_thr to be less than 60μs;

[0039] The discharge trigger pulse count threshold interval lower limit DC_Trig_thr_l in the discharge trigger pulse count threshold interval DC_Trig_thr is greater than 200 μs, and the discharge trigger pulse count threshold interval upper limit DC_Trig_thr_h is less than 405 μs;

[0040] The lower limit MEG_REF_thr_l of the magnetic pulser reference pulse count threshold interval MEG_REF_thr is greater than or equal to 405 μs, and the upper limit MEG_REF_thr_h of the magnetic pulser reference pulse count threshold interval is less than 425 μs.

[0041] The above-mentioned step 4 specifically includes the following steps:

[0042] Step 4.1, the serial data signal SERDA is captured by the input circuit;

[0043] Step 4.2, when the input circuit detects the first rising edge, the count value count1 output by the counter starts counting from 0, the abnormality detection circuit receives the first detection enable signal sent by the input circuit, and the abnormality detection circuit outputs a flag setting signal corresponding to the start pulse flag Find_STP_Flag to the status flag register, so that the start pulse flag Find_STP_Flag in the status flag register is set; after the counter starts counting, it continuously sends the count value count1 corresponding to each moment to the abnormality detection circuit;

[0044] Step 4.3, the input circuit continues to detect the rising edge of the serial data signal SERDA, and the counter continues to count;

[0045] At the same time, the abnormal detection circuit judges the count value countl:

[0046] If the input circuit still does not detect the second rising edge when the count value count1 output by the counter reaches the maximum count value threshold value count_max, return to step 3;

[0047] If the count value count1 output by the counter does not reach the maximum count value threshold value count_max, the input circuit detects the second rising edge, and the abnormal detection circuit receives the second detection enable signal sent by the input circuit, then the register of the counter temporarily stores the count value count1 corresponding to the second rising edge; the abnormal detection circuit uses the time corresponding to the count value count1 corresponding to the second rising edge as the charge trigger pulse phase difference delta_Charge_phase and determines whether the charge trigger pulse phase difference delta_Charge_phase is within the set charge trigger pulse count threshold interval Charge_thr. If the charge trigger pulse phase difference delta_Charge_phase is within the charge trigger pulse count threshold interval Charge_thr, the abnormal detection circuit sets the charge trigger pulse flag Find_Charge_Flag in the status flag register, and then executes step 4.4; otherwise, returns to step 3;

[0048] Step 4.4, the counter continues to count, and after the sampling circuit recognizes that the charge trigger pulse flag Find_Charge_Flag is 1, the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA are sequentially sampled according to the preset sampling time point, and the sampling results are temporarily stored in the register of the sampling circuit;

[0049] During the sampling process, the abnormality detection circuit does not judge the count value count1;

[0050] Step 4.5, the input circuit continues to detect the rising edge of the serial data signal SERDA, and the counter continues to count;

[0051] At the same time, the abnormal detection circuit judges the count value countl:

[0052] If the input circuit still does not detect the third rising edge when the count value count1 output by the counter reaches the maximum count value threshold value count_max, return to step 3;

[0053] If the count value countl output by the counter does not reach the maximum count value threshold value count_max, the input circuit detects the third rising edge, the abnormality detection circuit receives the third detection enable signal sent by the input circuit, and the register of the counter temporarily stores the count value countl corresponding to the third rising edge. The abnormality detection circuit uses the time corresponding to the count value countl corresponding to the third rising edge as the discharge trigger pulse phase difference delta_DC_Trig_phase, and compares it with the set discharge trigger pulse count threshold interval DC_Trig_thr. If the discharge trigger pulse phase difference delta_DC_Trig_phase is within the range of the discharge trigger pulse count threshold interval DC_Trig_thr, the discharge trigger pulse flag Find_DC_Trig_Flag is set, and then step 4.6 is executed; otherwise, return to step 3;

[0054] Step 4.6, the input circuit continues to detect the rising edge of the serial data signal SERDA, and the counter continues to count;

[0055] At the same time, the abnormal detection circuit judges the count value countl:

[0056] If the input circuit still does not detect the fourth rising edge when the count value count1 output by the counter reaches the maximum count value threshold value count_max, return to step 3;

[0057] If the count value countl output by the counter does not reach the maximum count value threshold count_max, the input circuit detects the fourth rising edge, and the abnormal detection circuit receives the fourth detection enable signal sent by the input circuit, then the register of the counter temporarily stores the count value countl corresponding to the fourth rising edge, and the abnormal detection circuit uses the time corresponding to the count value countl corresponding to the fourth rising edge as the magnetic pulser reference pulse phase difference delta_MEG_REF_phase and compares it with the magnetic pulser reference pulse count threshold interval MEG_REF_thr. If the magnetic pulser reference pulse phase difference delta_MEG_REF_phase is within the range of the magnetic pulser reference pulse count threshold interval MEG_REF_thr, the abnormal detection circuit sets the magnetic pulser reference pulse flag Find_MEG_REF_Flag and the integrity error flag SERDA_Integrity_Error in the status flag register, and executes step 5; otherwise, returns to step 3.

[0058] The above step 5 specifically includes the following steps:

[0059] The output circuit outputs the data temporarily stored in the counter, sampling circuit and status flag register to the external monitoring control unit. The external monitoring control unit turns on the link switch so that the complete and abnormal serial data signal SERDA in the current input circuit detected in step 4 is input into the HCG half-cycle power generating unit of the corresponding Loran C transmitter, and then returns to step 2.

[0060] A set of the above-mentioned Loran C key signal detection device processes one serial data signal SERDA, and four serial data signals SERDA are input in parallel to the corresponding set of the above-mentioned Loran C key signal detection device.

[0061] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0062] The present invention effectively solves the problem of monitoring SERDA signals in the Roland wave control system, and ensures the normal operation of the wave control system by detecting the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 Schematic diagram of a single serial data signal (SERDA signal) in the Roland broadcast control system.

[0064] Figure 2 The diagram is a relative timing relationship diagram of the four serial data signals (SERDA signals) in the Roland broadcast control system. Among them, ① represents the first serial data signal SERDA, ② represents the second serial data signal SERDA, ③ represents the third serial data signal SERDA, and ④ represents the fourth serial data signal SERDA.

[0065] Figure 3 The figure is a schematic diagram of the structure of a device for detecting Roland C key signals.

[0066] Among them, 1-input circuit; 2-counter; 3-clock source; 4-abnormal detection circuit; 5-status flag register; 6-sampling circuit; 7-reset control circuit; 8-output circuit; 9-external monitoring control unit; 10-link switch; 11-HCG half-cycle power generation unit. DETAILED DESCRIPTION

[0067] In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below in conjunction with embodiments. It should be understood that the implementation examples described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0068] Example 1

[0069] A device for detecting a Roland C key signal comprises an input circuit 1, a counter 2, a sampling circuit 6, a status flag register 5, an abnormality detection circuit 4 and an output circuit 8, wherein:

[0070] The input circuit 1 is used to capture the serial data signal SERDA and detect the rising edge in the serial data signal SERDA. When the input circuit 1 detects the rising edge in the serial data signal SERDA, it sends a count enable signal to the counter 2 (in this embodiment, when the input circuit 1 detects the first rising edge in the serial data signal SERDA, the input circuit 1 sends the count enable signal to the counter 2), and at the same time sends a detection enable signal to the abnormality detection circuit 4 (in this embodiment, whenever the input circuit 1 detects a rising edge in the serial data signal SERDA, it sends a detection enable signal to the abnormality detection circuit 4); in this embodiment, the input circuit 1 adopts a three-stage shift register structure, and determines whether a rising edge occurs according to the state change of the serial data signal SERDA;

[0071] The counter 2 receives the clock signal of the clock source 3 and the count enable signal output by the input circuit 1. When the counter 2 receives the count enable signal from the initial state, it starts counting and sends the count value count1 corresponding to each moment to the abnormality detection circuit 4 in sequence. Since the counter 2 starts counting after detecting the first rising edge from the input circuit 1, when the next rising edge is used as the current rising edge, the corresponding count value count1 can represent the phase difference between the current rising edge and the first rising edge. In this embodiment, the clock source 3 provides a clock with a frequency of 100 MHz, and each increase of 1 in the count value count1 represents that 10 ns has passed.

[0072] The abnormality detection circuit 4 determines whether the serial data signal SERDA is complete according to the received detection enable signal, the count value count1 and the preset count threshold value (i.e., determines whether the serial data signal SERDA includes four single pulses, namely, the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF, and the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse), and outputs a flag bit setting signal corresponding to each single pulse in the serial data signal SERDA and a flag bit setting signal corresponding to the integrity error flag SERDA_Integrity_Error to the status flag register 5 according to the judgment result; wherein the preset count threshold value includes the maximum count value threshold value count_max and the count value threshold interval corresponding to each single pulse in the serial data signal SERDA; the threshold interval corresponding to each single pulse includes:

[0073] The charge trigger pulse count threshold interval Charge_thr represents the time limit corresponding to the count value countl corresponding to the rising edge of the charge trigger pulse, corresponding to the charge trigger pulse Charge;

[0074] The discharge trigger pulse count threshold interval DC_Trig_thr represents the time limit corresponding to the count value count1 corresponding to the rising edge of the discharge trigger pulse, corresponding to the discharge trigger pulse DC_Trig;

[0075] The magnetic pulser reference pulse counting threshold interval MEG_REF_thr represents the time limit corresponding to the count value countl corresponding to the rising edge of the magnetic pulser reference pulse, corresponding to the magnetic pulser reference pulse MEG_REF;

[0076] The flag bits corresponding to a single pulse include:

[0077] The start pulse flag Find_STP_Flag corresponds to the start pulse STP;

[0078] The charge trigger pulse flag bit Find_Charge_Flag corresponds to the charge trigger pulse Charge;

[0079] The discharge trigger pulse flag Find_DC_Trig_Flag corresponds to the discharge trigger pulse DC_Trig;

[0080] The magnetic pulser reference pulse flag Find_MEG_REF_Flag corresponds to the magnetic pulser reference pulse MEG_REF;

[0081] The status flag register 5 sets the flag corresponding to each single pulse in the serial data signal SERDA and the integrity error flag SERDA_Integrity_Error according to the flag setting signal output by the abnormal detection circuit 4; wherein the start pulse flag Find_STP_Flag is used to identify whether the corresponding start pulse STP is correctly detected, the charge trigger pulse flag Find_Charge_Flag is used to identify whether the corresponding charge trigger pulse Charge is correctly detected, the discharge trigger pulse flag Find_DC_Trig_Flag is used to identify whether the corresponding discharge trigger pulse DC_Trig is correctly detected, the magnetic pulser reference pulse flag Find_MEG_REF_Flag is used to identify whether the corresponding magnetic pulser reference pulse MEG_REF is correctly detected, and the integrity error flag SERDA_Integrity_Error is used to identify whether the entire serial data signal SERDA is received;

[0082] The sampling circuit 6 receives the clock signal of the clock source 3, and reads the flag bits corresponding to the start pulse STP and the charge trigger pulse Charge of the serial data signal SERDA in the status flag register 5 (i.e., the start pulse flag bit Find_STP_Flag and the charge trigger pulse flag bit Find_Charge_Flag), and selects whether to sample and temporarily store the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A-rate phase encoding φA data according to the preset sampling time point after detecting the start pulse STP and the charge trigger pulse Charge;

[0083] The reset control circuit 7 reads the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register 5, and selects whether to send a reset execution signal to the counter 2, the sampling circuit 6 and the status flag register 5, thereby resetting and initializing the counter 2, the sampling circuit 6 and the status flag register 5;

[0084] In order to facilitate monitoring and checking the data temporarily stored in the counter 2, the sampling circuit 6 and the status flag register 5, the present invention further includes an output circuit 8, which reads the flag bits corresponding to each single pulse of the status flag register 5 and the value of the integrity error flag bit SERDA_Integrity_Error, and selects whether to transmit the data temporarily stored in the counter 2, the sampling circuit 6 and the status flag register 5 to the external monitoring control unit 9; the output circuit 8 is used to output to the external monitoring control unit 9 when all four single pulses are correctly detected, and the data temporarily stored in the counter 2, the sampling circuit 6 and the status flag register 5 include:

[0085] The count value count1 corresponding to the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF temporarily stored in the counter 2 (the count value count1 corresponding to the charge trigger pulse Charge corresponds to the phase difference between the output charge trigger pulse Charge and the start pulse STP, the count value count1 corresponding to the discharge trigger pulse DC_Trig corresponds to the phase difference between the discharge trigger pulse DC_Trig and the start pulse STP, and the count value count1 corresponding to the magnetic pulser reference pulse MEG_REF corresponds to the phase difference between the magnetic pulser reference pulse MEG_REF and the start pulse STP);

[0086] The eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA temporarily stored in the sampling circuit 6;

[0087] The flag bits corresponding to each single pulse temporarily stored in the status flag register 5 and the value of the integrity error flag bit SERDA_Integrity_Error.

[0088] The external monitoring control unit 9 controls the link switch 10 between the input circuit 1 and the HCG half-cycle power generating unit 11 according to the value of the integrity error flag SERDA_Integrity_Error in the received status flag register 5; in the present embodiment, when the value of the integrity error flag SERDA_Integrity_Error is 1, the link switch 10 is closed, and when the value of the integrity error flag SERDA_Integrity_Error is 0, the link switch 10 is opened.

[0089] Example 2

[0090] A method for detecting a Loran C key signal, using the device for detecting a Loran C key signal described in Example 1.

[0091] The timing pulse control unit in the Roland C control cabinet generates four parallel serial data signals SERDA. Each serial data signal SERDA is as follows: Figure 1 As shown, each includes four single pulses (start pulse STP, charge trigger pulse Charge, discharge trigger pulse DC_Trig, and magnetic pulser reference pulse MEG_REF) and eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD, and one-bit A-rate phase encoding φA. Four serial data signals SERDA are input in parallel to the input circuit 1 of the device for detecting the Roland C key signal of the present invention. The timing sequence of each signal in each serial data signal SERDA is as follows: start pulse STP, charge trigger pulse Charge, eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD, one-bit A-rate phase encoding φA, discharge trigger pulse DC_Trig, and magnetic pulser reference pulse MEG_REF;

[0092] Among them, the rising edge time of the start pulse STP in the four-way serial data signal SERDA is the same, the rising edge time of the eight-bit digital amplitude reference DAR in the four-way serial data signal SERDA is the same, the rising edge time of the seven-bit amplitude compensation delay ACD in the four-way serial data signal SERDA is the same, and the rising edge time of the one-bit A-rate phase code φA in the four-way serial data signal SERDA is the same; within a time interval of 200μs from the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA after the start pulse STP signal, the charging trigger pulse Charge in the second serial data signal SERDA, the charging trigger pulse Charge in the third serial data signal SERDA and the charging trigger pulse Charge in the fourth serial data signal SERDA are respectively relative to the charging trigger pulse Charge in the first serial data signal SERDA. Charge is delayed by 5μs, 10μs and 15μs; the discharge trigger pulse DC_Trig in the second serial data signal SERDA, the discharge trigger pulse DC_Trig in the third serial data signal SERDA and the discharge trigger pulse DC_Trig in the fourth serial data signal SERDA are delayed by 5μs, 10μs and 15μs respectively relative to the discharge trigger pulse DC_Trig in the first serial data signal SERDA; the magnetic pulser reference pulse MEG_REF in the second serial data signal SERDA, the magnetic pulser reference pulse MEG_REF in the third serial data signal SERDA and the magnetic pulser reference pulse MEG_REF in the fourth serial data signal SERDA are delayed by 5μs, 10μs and 15μs respectively relative to the magnetic pulser reference pulse MEG_REF in the first serial data signal SERDA; Figure 2 shown.

[0093] A set of the aforementioned Roland C key signal detection device processes one serial data signal SERDA, and four serial data signals SERDA are input in parallel to the corresponding set of the aforementioned Roland C key signal detection device, and the detection of each serial data signal SERDA does not affect each other. Each serial data signal SERDA is independently detected according to the following steps:

[0094] Step 1, setting the count value threshold interval and the maximum count value threshold count_max corresponding to each single pulse in the abnormality detection circuit 4, and setting the preset sampling time point in the sampling circuit 6;

[0095] The count thresholds include:

[0096] The maximum count value threshold count_max indicates that the count value count1 in counter 2 can reach the maximum value. When the count value count1 exceeds the maximum count value threshold count_max, it is considered that a fault occurs. The maximum count value threshold count_max is set to the maximum interval time of the two serial data signals SERDA on the same path. In this embodiment, the maximum interval between the two serial data signals SERDA on the same path is 99ms. As long as the time corresponding to the count value count1 exceeds 99ms, the integrity error flag SERDA_Integrity_Error is set to 1. If there is no signal or no rising edge input and the count value count1 count time exceeds 99ms, the count value count1 will be cleared and the counting will start again. This process is cyclically carried out. In this embodiment, the system uses a clock with a frequency of 100MHz. Every increase of 1 in the count value count1 represents that 10ns have passed.

[0097] The charging trigger pulse counting threshold interval Charge_thr represents the limited range corresponding to the phase difference of the rising edge of the charging trigger pulse relative to the rising edge of the start pulse; the charging trigger pulse counting threshold interval lower limit Charge_thr_l in the charging trigger pulse counting threshold interval Charge_thr is greater than 5μs, and the charging trigger pulse counting threshold interval upper limit Charge_thr_h is less than 60μs; in this embodiment, the rising edges of the charging trigger pulse Charge in the preset four-way serial data signal SERDA are respectively 15μs, 20μs, 25μs, and 30μs away from the rising edge of the start pulse STP, and the charging trigger pulse counting threshold interval Charge_thr corresponding to the four-way serial data signal SERDA is [13μs, 32μs].

[0098] The discharge trigger pulse counting threshold interval DC_Trig_thr represents the limited range corresponding to the phase difference of the rising edge of the discharge trigger pulse relative to the rising edge of the start pulse; the discharge trigger pulse counting threshold interval lower limit DC_Trig_thr_l in the discharge trigger pulse counting threshold interval DC_Trig_thr is greater than 200μs, and the discharge trigger pulse counting threshold interval upper limit DC_Trig_thr_h is less than 405μs. In this embodiment, DC_Trig_thr=[373μs, 397μs];

[0099] The magnetic pulser reference pulse count threshold interval MEG_REF_thr represents the limited range corresponding to the phase difference of the rising edge of the magnetic pulser reference pulse relative to the rising edge of the start pulse; the lower limit of the magnetic pulser reference pulse count threshold interval MEG_REF_thr_l in the magnetic pulser reference pulse count threshold interval MEG_REF_thr is greater than or equal to 405μs, and the upper limit of the magnetic pulser reference pulse count threshold interval MEG_REF_thr_h is less than 425μs.

[0100] During the counting process of the counter 2, the abnormal detection circuit 4 will check in real time whether the time corresponding to the count value count1 in the counter 2 is within the threshold interval corresponding to the above four single pulses. When the rising edge is detected and the threshold interval corresponding to the corresponding single pulse is satisfied at the same time, it is considered that the single pulse is correctly detected, and the count value count1 at this time is recorded, and the corresponding flag bits of the single pulse are set at the same time (the start pulse flag bit Find_STP_Flag, the charge trigger pulse flag bit Find_Charge_Flag, the discharge trigger pulse flag bit Find_DC_Trig_Flag and the magnetic pulser reference pulse flag bit Find_MEG_REF_Flag).

[0101] Preset sampling time point: The preset sampling time point determines the time point at which the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA are sampled. In this embodiment, the sampling time points corresponding to the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA are spaced 60μs, 160μs and 195μs relative to the start pulse STP, respectively.

[0102] Step 2: The link switch 10 is set to be closed;

[0103] Step 3, reset and initialize the count value count1 in the counter 2, the register of the sampling circuit 6 and all the flag bits in the status flag register 5 through the reset control circuit 7;

[0104] In this embodiment, the flag bits corresponding to the count value count1 and all single pulses are initialized to 0, and the integrity error flag bit SERDA_Integrity_Error is initialized to 1;

[0105] The flags corresponding to the single pulse include: the start pulse flag Find_STP_Flag, the charge trigger pulse flag Find_Charge_Flag, the discharge trigger pulse flag Find_DC_Trig_Flag, and the magnetic pulser reference pulse flag Find_MEG_REF_Flag.

[0106] Step 4: Perform integrity detection and data sampling on the serial data signal SERDA:

[0107] Input circuit 1 captures serial data signal SERDA and detects the rising edge in serial data signal SERDA, counter 2 starts counting, abnormality detection circuit 4 detects the starting pulse STP, charging trigger pulse Charge, discharge trigger pulse DC_Trig and magnetic pulser reference pulse MEG_REF in serial data signal SERDA through the count value count1 output by counter 2, and judges the integrity of serial data signal SERDA. If serial data signal SERDA is complete, that is, serial data signal SERDA includes four single pulses, namely, starting pulse STP, charging trigger pulse Charge, discharge trigger pulse DC_Trig and magnetic pulser reference pulse MEG_REF, and the time corresponding to the count value count1 of the four single pulses meets the preset counting threshold requirement, then step 5 is executed; if any of the starting pulse STP, charging trigger pulse Charge, discharge trigger pulse DC_Trig and magnetic pulser reference pulse MEG_REF is not detected, then return to step 3 and re-detect the next rising edge. The specific steps are:

[0108] Step 4.1, the serial data signal SERDA is captured by the input circuit 1. The input circuit 1 uses a shift register and edge detection to obtain the rising edge moment of the serial data signal SERDA. When the input circuit 1 detects the rising edge, it is considered that the input circuit 1 detects the first single pulse, and step 4.2 is executed. In this embodiment, the input circuit 1 uses a three-stage shift register to determine whether there is a rising edge according to the state change of the serial data signal SERDA.

[0109] Step 4.2, when the input circuit 1 detects the first rising edge, the count value count1 output by the counter 2 starts counting from 0, the abnormality detection circuit 4 receives the first detection enable signal sent by the input circuit 1, and the abnormality detection circuit 4 outputs a flag setting signal corresponding to the start pulse flag Find_STP_Flag to the status flag register 5, so that the start pulse flag Find_STP_Flag is set. In this embodiment, the start pulse flag Find_STP_Flag is set to 1; after the counter 2 starts counting, it continues to send the count value count1 corresponding to each moment to the abnormality detection circuit 4.

[0110] Because when the program is initially run (or an error in the serial data signal SERDA is detected and the program is reset), the count value count1 and the flag bits corresponding to all single pulses are 0, then any pulse detected is regarded as the start pulse STP, and the corresponding start pulse flag Find_STP_Flag is set to 1. If there is the next single pulse input, the input circuit 1 regards the second pulse as the charge trigger pulse Charge.

[0111] Step 4.3, input circuit 1 continues to detect the rising edge of serial data signal SERDA, while counter 2 continues to count;

[0112] At the same time, the abnormality detection circuit 4 judges the count value count1:

[0113] If the input circuit 1 still does not detect the second rising edge when the count value count1 output by the counter 2 reaches the maximum count value threshold value count_max (that is, the abnormality detection circuit 4 does not receive the second detection enable signal), then return to step 3;

[0114] If the count value count1 output by the counter 2 does not reach the maximum count value threshold value count_max, the input circuit 1 detects the second rising edge, and the abnormal detection circuit 4 receives the second detection enable signal sent by the input circuit 1. At this time, the start pulse flag Find_STP_Flag is 1 and the charge trigger pulse flag Find_Charge_Flag is 0, and the second pulse is considered to be the charge trigger pulse Charge. At this time, the register of the counter 2 temporarily stores the phase difference between the rising edge of the second pulse and the rising edge of the start pulse STP (that is, the time corresponding to the count value count1 corresponding to the second rising edge); the abnormal detection circuit 4 uses the time corresponding to the count value count1 corresponding to the second rising edge as the charge trigger pulse phase difference delta_Charge_phase And determine whether the charging trigger pulse phase difference delta_Charge_phase is within the set charging trigger pulse counting threshold interval Charge_thr. If the charging trigger pulse phase difference delta_Charge_phase is within the charging trigger pulse counting threshold interval Charge_thr, the abnormal detection circuit 4 sets the charging trigger pulse flag Find_Charge_Flag in the status flag register 5. In this implementation, the charging trigger pulse flag Find_Charge_Flag is set to 1, and then execute step 4.4; otherwise, return to step 3 (that is, set the flag positions corresponding to all single pulses to 0, clear all caches, set the integrity error flag SERDA_Integrity_Error to 1, and the link switch 10 remains closed).

[0115] Step 4.4, counter 2 continues to count, and after sampling circuit 6 identifies that the charge trigger pulse flag Find_Charge_Flag is 1, it sequentially samples the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A-rate phase code φA according to the preset sampling time point, and stores the sampling results in the register of sampling circuit 6 as cache data (the cache data is not output in step 4.4). Then execute step 4.5;

[0116] In step 4.4, it is only necessary to perform sampling according to the preset sampling time point. Only when the four single pulses of the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF are detected, the sampled data (eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD, one-bit A-rate phase code φA) will be output to the external monitoring control unit 9.

[0117] During the sampling process, the abnormality detection circuit 4 does not judge the count value count1.

[0118] Step 4.5, input circuit 1 continues to detect the rising edge of serial data signal SERDA, while counter 2 continues to count;

[0119] At the same time, the abnormality detection circuit 4 judges the count value count1:

[0120] If the input circuit 1 still does not detect the third rising edge when the count value count1 output by the counter 2 reaches the maximum count value threshold value count_max, return to step 3;

[0121] If the count value count1 output by counter 2 does not reach the maximum count value threshold value count_max, the input circuit 1 detects the third rising edge, and the abnormality detection circuit 4 receives the third detection enable signal sent by the input circuit 1. At this time, the start pulse flag Find_STP_Flag and the charge trigger pulse flag Find_Charge_Flag are all 1, and the discharge trigger pulse flag Find_DC_Trig_Flag is 0. It is considered that this single pulse is the discharge trigger pulse DC_Trig, and the register of counter 2 temporarily stores the phase difference between the rising edge of the third pulse and the rising edge of the start pulse STP (that is, the time corresponding to the count value count1 corresponding to the third rising edge) as the discharge trigger pulse phase difference delta_DC_Trig_phase. The abnormality detection circuit 4 will discharge The trigger pulse phase difference delta_DC_Trig_phase is compared with the set discharge trigger pulse count threshold interval DC_Trig_thr. If the discharge trigger pulse phase difference delta_DC_Trig_phase is within the range of the discharge trigger pulse count threshold interval DC_Trig_thr, the abnormal detection circuit 4 sets the discharge trigger pulse flag Find_DC_Trig_Flag in the status flag register 5. In this embodiment, the discharge trigger pulse flag Find_DC_Trig_Flag is set to 1, and then the next step 4.6 is executed; otherwise, return to step 3 (that is, set the flag positions corresponding to all single pulses to 0, clear all caches, set the integrity error flag SERDA_Integrity_Error to 1, and the link switch 10 remains closed).

[0122] In step 4.5, when both the start pulse STP and the charge trigger pulse Charge are detected, when the third single pulse is detected, it may be interfered by the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase encoding φA signal, causing these data to be misjudged as the discharge trigger pulse DC_Trig. Therefore, the third single pulse is judged by the discharge trigger pulse flag Find_DC_Trig_Flag to exclude the serial data signal SERDA with data bit interference.

[0123] Step 4.6, input circuit 1 continues to detect the rising edge of serial data signal SERDA, while counter 2 continues to count;

[0124] At the same time, the abnormality detection circuit 4 judges the count value count1:

[0125] If the input circuit 1 still does not detect the fourth rising edge when the count value count1 output by the counter 2 reaches the maximum count value threshold value count_max, return to step 3;

[0126] If the count value count1 output by the counter 2 does not reach the maximum count value threshold value count_max, the input circuit 1 detects the fourth rising edge, and the abnormality detection circuit 4 receives the fourth detection enable signal sent by the input circuit 1. At this time, the fourth single pulse is input and the flags corresponding to the first three pulses of the serial data signal SERDA (i.e., the start pulse flag Find_STP_Flag, the charge trigger pulse flag Find_Charge_Flag and the discharge trigger pulse flag Find_DC_Trig_Flag) are all 1, the register of the counter 2 temporarily stores the phase difference between the fourth pulse rising edge and the first pulse rising edge (i.e., the time corresponding to the count value count1 corresponding to the fourth rising edge), which is recorded as the magnetic pulser reference pulse phase difference delta_MEG_REF_phase, and the abnormality detection circuit 4 compares the magnetic pulser reference pulse phase difference delta_MEG_REF_phase with the magnetic pulser reference pulse count threshold value. The interval MEG_REF_thr is compared. If the phase difference delta_MEG_REF_phase of the magnetic pulser reference pulse is within the range of the magnetic pulser reference pulse counting threshold interval MEG_REF_thr, the magnetic pulser reference pulse flag Find_MEG_REF_Flag is set. In the present embodiment, the magnetic pulser reference pulse flag Find_MEG_REF_Flag is set to 1, indicating that the four single pulses of the serial data signal SERDA are all detected, and the integrity error flag SERDA_Integrity_Error is set. In the present embodiment, the integrity error flag SERDA_Integrity_Error is set to 0, and the process goes to step 5; otherwise, it returns to step 3 (i.e., the flag positions corresponding to all single pulses are set to 0, all caches are cleared, the integrity error flag SERDA_Integrity_Error flag position is set to 1, and the link switch 10 remains closed).

[0127] If any single pulse is not detected in step 4, the count value count1 is set to 0, and the integrity error flag SERDA_Integrity_Error is set to 1. At the same time, the program is reset and waits for the next single pulse to be detected.

[0128] Since the count value count1 is always counting, only when the first pulse is input is recorded as time 0, and the count value is cleared. If there is no serial data signal SERDA input, counter 2 will continue to count, that is, regardless of whether there is a signal input, the count value count1 will continue to count, and will be set to 0 only when the start pulse STP input is detected or the program is reset or there is no signal input so that the count value count1 exceeds the maximum count threshold. If the count value count1 exceeds the maximum count value threshold count_max, the integrity error flag SERDA_Integrity_Error flag position is set to 1, and return to step 3 to restart counting. The maximum count value threshold count_max is set to the maximum interval time between the two serial data signals SERDA on the same path. In this embodiment, the interval between the two serial data signals SERDA on the same path is up to 99ms. As long as the time recorded by the count value count1 exceeds 99ms, the integrity error flag SERDA_Integrity_Error is set to 1. If there is no signal input and the counting time of the count value count1 exceeds 99ms, the count value count1 will be cleared and counting will start again. This process is always carried out.

[0129] In steps 4.3-4.6, if the rising edge is not detected, the program continues to detect the rising edge after resetting. It may happen that the pulse detected during reset is not actually the starting pulse STP. Due to the threshold interval limitation of each single pulse in the serial data signal SERDA, even if the program mistakenly detects other pulses as the starting pulse STP, the program will still reset and recount because the next pulse is not within the preset charge trigger pulse counting threshold interval Charge_thr.

[0130] Step 5. At this time, the integrity detection of the entire serial data signal SERDA has been completed. The output circuit 8 outputs the data temporarily stored in the counter 2, the sampling circuit 6 and the status flag register 5 to the external monitoring control unit 9. The external monitoring control unit 9 turns on the link switch 10 to allow the complete and abnormal serial data signal SERDA in the current input circuit 1 detected in step 4 to be input into the HCG half-cycle power generating unit 11 of the corresponding Loran C transmitter, and then returns to step 2.

[0131] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A device for detecting a Loran C key signal, comprising an input circuit (1), characterized in that: The input circuit (1) captures the serial data signal SERDA. When the input circuit (1) detects the first rising edge in the serial data signal SERDA, it sends a count enable signal to the counter (2). Whenever the input circuit (1) detects a rising edge in the serial data signal SERDA, it sends a detection enable signal to the abnormality detection circuit (4). The counter (2) receives a clock signal and a count enable signal from a clock source (3). When the counter (2) receives the count enable signal, it starts to count continuously and sends the count value count1 to the abnormality detection circuit (4) in sequence. The abnormality detection circuit (4) determines, based on the received detection enable signal and the count value count1, whether the serial data signal SERDA includes four single pulses, namely, a start pulse STP, a charge trigger pulse Charge, a discharge trigger pulse DC_Trig and a magnetic pulser reference pulse MEG_REF, in sequence, and whether the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse. Based on the judgment result, the abnormality detection circuit (4) outputs a flag setting signal corresponding to each single pulse and a flag setting signal corresponding to the integrity error flag SERDA_Integrity_Error to the status flag register (5), thereby setting the flag corresponding to the single pulse and the integrity error flag SERDA_Integrity_Error; the reset control circuit (7) selects whether to send a reset execution signal to the counter (2) and the status flag register (5) based on the value of the integrity error flag SERDA_Integrity_Error in the status flag register (5); The external monitoring control unit (9) controls the link switch (10) between the input circuit (1) and the HCG half-cycle power generation unit (11) according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register (5).

2. A Loran C key signal detection device according to claim 1, characterized in that: The counting value threshold intervals corresponding to each single pulse include: The charge trigger pulse count threshold interval Charge_thr represents the time limit corresponding to the count value countl corresponding to the rising edge of the charge trigger pulse, corresponding to the charge trigger pulse Charge; The discharge trigger pulse count threshold interval DC_Trig_thr represents the time limit corresponding to the count value count1 corresponding to the rising edge of the discharge trigger pulse, corresponding to the discharge trigger pulse DC_Trig; The magnetic pulser reference pulse counting threshold interval MEG_REF_thr represents the time limit corresponding to the count value countl corresponding to the rising edge of the magnetic pulser reference pulse, corresponding to the magnetic pulser reference pulse MEG_REF; The flag bits corresponding to each single pulse in the serial data signal SERDA include: The start pulse flag Find_STP_Flag corresponds to the start pulse STP; The charge trigger pulse flag bit Find_Charge_Flag corresponds to the charge trigger pulse Charge; The discharge trigger pulse flag Find_DC_Trig_Flag corresponds to the discharge trigger pulse DC_Trig; The magnetic pulser reference pulse flag Find_MEG_REF_Flag corresponds to the magnetic pulser reference pulse MEG_REF.

3. A Loran C key signal detection device according to claim 1, characterized in that , the input circuit (1) adopts a three-stage shift register structure.

4. A Loran C key signal detection device according to claim 2, characterized in that , further comprising a sampling circuit (6) and an output circuit (8), The sampling circuit (6) receives the clock signal of the clock source (3), and selects whether to sample and temporarily store the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA according to the flag bits corresponding to the start pulse STP and the charge trigger pulse Charge; The output circuit (8) reads the flag bits corresponding to each single pulse of the status flag register (5) and the value of the integrity error flag bit SERDA_Integrity_Error, and selects whether to transmit the data temporarily stored in the counter (2), the sampling circuit (6) and the status flag register (5) to the external monitoring control unit (9); The data temporarily stored in the counter (2) are: the count value count1 corresponding to the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF; The data temporarily stored in the sampling circuit (6) are: eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD and one-bit A-rate phase code φA; The data temporarily stored in the status flag register (5) are: the flag bits corresponding to each single pulse and the value of the integrity error flag bit SERDA_Integrity_Error; The reset control circuit (7) selects whether to send a reset execution signal to the sampling circuit (6) according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register (5).

5. A method for detecting a Loran C key signal, using the device for detecting a Loran C key signal according to claim 4, characterized in that , including the following steps: Step 1, setting the count value threshold interval and the maximum count value threshold count_max corresponding to each single pulse in the abnormality detection circuit (4), and setting the preset sampling time point in the sampling circuit (6); Step 2, the link switch (10) is set to off; Step 3, resetting and initializing the count value count1 in the counter (2), the register of the sampling circuit (6) and all the flag bits in the status flag register (5) through the reset control circuit (7); Step 4, the input circuit (1) captures the serial data signal SERDA and detects the rising edge in the serial data signal SERDA, the counter (2) starts counting, the abnormality detection circuit (4) detects the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF in the serial data signal SERDA through the count value count1 output by the counter (2), and determines whether the serial data signal SERDA is complete. If the serial data signal SERDA is complete, that is, the serial data signal SERDA includes four single pulses, namely, the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF, and the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse, then step 5 is executed; if any one of the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF is not detected, then return to step 3; Step 5: The external monitoring control unit (9) turns on the link switch (10) so that the complete and normal serial data signal SERDA in the input circuit (1) is input into the HCG half-cycle power generation unit (11) of the corresponding Loran C transmitter, and then returns to step 2.

6. A method for detecting a Loran C key signal according to claim 5, characterized in that In the step 1, the maximum count value threshold count_max is set to the maximum interval time between the two serial data signals SERDA on the same path.

7. A method for detecting a Loran C key signal according to claim 5, characterized in that , in the step 1, Set the lower limit Charge_thr_l of the charge trigger pulse count threshold interval Charge_thr to be greater than 5μs, and the upper limit Charge_thr_h of the charge trigger pulse count threshold interval Charge_thr to be less than 60μs; The discharge trigger pulse count threshold interval lower limit DC_Trig_thr_l in the discharge trigger pulse count threshold interval DC_Trig_thr is greater than 200 μs, and the discharge trigger pulse count threshold interval upper limit DC_Trig_thr_h is less than 405 μs; The lower limit MEG_REF_thr_l of the magnetic pulser reference pulse count threshold interval MEG_REF_thr is greater than or equal to 405 μs, and the upper limit MEG_REF_thr_h of the magnetic pulser reference pulse count threshold interval is less than 425 μs.

8. A method for detecting a Loran C key signal according to claim 5, characterized in that , the step 4 specifically includes the following steps: Step 4.1, the serial data signal SERDA is captured by the input circuit (1); Step 4.2, when the input circuit (1) detects the first rising edge, the count value count1 output by the counter (2) starts counting from 0, the abnormality detection circuit (4) receives the first detection enable signal sent by the input circuit (1), and the abnormality detection circuit (4) outputs a flag setting signal corresponding to the start pulse flag Find_STP_Flag to the status flag register (5), so that the start pulse flag Find_STP_Flag in the status flag register (5) is set; After the counter (2) starts counting, it continuously sends the count value count1 corresponding to each moment to the abnormality detection circuit (4); Step 4.3, the input circuit (1) continues to detect the rising edge of the serial data signal SERDA, and the counter (2) continues to count; At the same time, the abnormality detection circuit (4) determines the count value count1: If the input circuit (1) still does not detect the second rising edge when the count value count1 output by the counter (2) reaches the maximum count value threshold value count_max, the process returns to step 3; If the count value count1 output by the counter (2) does not reach the maximum count value threshold value count_max, the input circuit (1) detects a second rising edge, and the abnormality detection circuit (4) receives the second detection enable signal sent by the input circuit (1), then the register of the counter (2) temporarily stores the count value count1 corresponding to the second rising edge; the abnormality detection circuit (4) uses the time corresponding to the count value count1 corresponding to the second rising edge as the charge trigger pulse phase difference delta_Charge_phase and determines whether the charge trigger pulse phase difference delta_Charge_phase is within the set charge trigger pulse count threshold interval Charge_thr. If the charge trigger pulse phase difference delta_Charge_phase is within the charge trigger pulse count threshold interval Charge_thr, the abnormality detection circuit (4) sets the charge trigger pulse flag Find_Charge_Flag in the status flag register (5) and then executes step 4.4; otherwise, returns to step 3; Step 4.4, the counter (2) continues to count, and after the sampling circuit (6) identifies that the charge trigger pulse flag Find_Charge_Flag is 1, the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA are sequentially sampled according to the preset sampling time point, and the sampling result is temporarily stored in the register of the sampling circuit (6); During the sampling process, the abnormality detection circuit (4) does not judge the count value count1; Step 4.5, the input circuit (1) continues to detect the rising edge of the serial data signal SERDA, and the counter (2) continues to count; At the same time, the abnormality detection circuit (4) determines the count value count1: If the input circuit (1) still does not detect the third rising edge when the count value count1 output by the counter (2) reaches the maximum count value threshold value count_max, the process returns to step 3; If the count value count1 output by the counter (2) does not reach the maximum count value threshold value count_max, the input circuit (1) detects the third rising edge, the abnormality detection circuit (4) receives the third detection enable signal sent by the input circuit (1), the register of the counter (2) temporarily stores the count value count1 corresponding to the third rising edge, the abnormality detection circuit (4) uses the time corresponding to the count value count1 corresponding to the third rising edge as the discharge trigger pulse phase difference delta_DC_Trig_phase, and compares it with the set discharge trigger pulse count threshold interval DC_Trig_thr. If the discharge trigger pulse phase difference delta_DC_Trig_phase is within the range of the discharge trigger pulse count threshold interval DC_Trig_thr, the discharge trigger pulse flag Find_DC_Trig_Flag is set, and then step 4.6 is executed; otherwise, return to step 3; Step 4.6, the input circuit (1) continues to detect the rising edge of the serial data signal SERDA, and the counter (2) continues to count; At the same time, the abnormality detection circuit (4) determines the count value count1: If the input circuit (1) still does not detect the fourth rising edge when the count value count1 output by the counter (2) reaches the maximum count value threshold value count_max, return to step 3; If the count value count1 output by the counter (2) does not reach the maximum count value threshold value count_max, the input circuit (1) detects the fourth rising edge, and the abnormality detection circuit (4) receives the fourth detection enable signal sent by the input circuit (1), then the register of the counter (2) temporarily stores the count value count1 corresponding to the fourth rising edge, and the abnormality detection circuit (4) uses the time corresponding to the count value count1 corresponding to the fourth rising edge as the magnetic pulser reference pulse phase difference delta_MEG_REF_phase and compares it with the magnetic pulser reference pulse count threshold interval MEG_REF_thr. If the magnetic pulser reference pulse phase difference delta_MEG_REF_phase is within the range of the magnetic pulser reference pulse count threshold interval MEG_REF_thr, the abnormality detection circuit (4) sets the magnetic pulser reference pulse flag Find_MEG_REF_Flag and the integrity error flag SERDA_Integrity_Error in the status flag register (5), and executes step 5; otherwise, returns to step 3.

9. A method for detecting a Loran C key signal according to claim 8, characterized in that , the step 5 specifically includes the following steps: The output circuit (8) outputs the data temporarily stored in the counter (2), the sampling circuit (6) and the status flag register (5) to the external monitoring control unit (9). The external monitoring control unit (9) turns on the link switch (10) so that the complete and abnormal serial data signal SERDA detected in step 4 in the current input circuit (1) is input into the HCG half-cycle power generation unit (11) of the corresponding Loran C transmitter, and then returns to step 2.

10. A method for detecting a Loran C key signal according to claim 5, characterized in that A set of the Roland C key signal detection device processes one serial data signal SERDA, and four serial data signals SERDA are input in parallel to the corresponding set of the Roland C key signal detection device.

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