Key destroying control device for key component and use method of key destroying control device

Abstract

The invention belongs to the technical field of control circuits. The invention provides a key destruction control device for a key component and a use method of the key destruction control device. According to the embodiment of the invention, after the device is intercepted by a competitor, in order to prevent data in the device from being acquired by the competitor, a central processing unit in the device triggers key element key-destroying operation, generates a key-destroying instruction and sends the key-destroying instruction to a control circuit; the control circuit generates a key destroying signal according to the key destroying instruction; the switching circuit processes the key destroying signal to improve the driving capability of the key destroying signal and generates a switching signal; the driving circuit responds to the switching signal and generates a high-voltage and large-current key destroying power supply; the key destroying power supply is sent to the power supply end of the key component through the protection circuit, the key component is physically destroyed, and the safety of key data is protected; the protection circuit ensures that other circuits of the equipment are not influenced by the key destroying power supply, and the purpose of only destroying key parts is achieved. Key destroying is carried out according to the key destroying instruction, so that misoperation and misoperation are avoided; and protection measures are adopted, so that other components are prevented from being damaged.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of control circuit technology, and more particularly to a key component destruction control device and a method of using the same. Background Art

[0002] With the vigorous development of marine resources and the rapid development of sonar technology, various types of underwater acoustic detection systems have been widely used in underwater communications, marine resource exploration, submarine tunnel construction, remote detection of underwater targets, etc. The underwater acoustic data of the underwater acoustic detection system is usually stored in key components (memory cards), and there is a risk of competitors and hostile forces obtaining key data. Appropriate security measures need to be taken to protect the security of key data.

[0003] Therefore, it is necessary to improve one or more problems existing in the above-mentioned related technical solutions.

[0004] It should be noted that this section is intended to provide background or context for the technical solutions of the present disclosure stated in the claims. The description herein is not admitted to be prior art by virtue of being included in this section. Summary of the invention

[0005] In order to avoid the deficiencies of the prior art, the present invention provides a XX to solve the problem in the prior art that there is a risk of key data being acquired by competitors or hostile forces.

[0006] According to a first aspect of an embodiment of the present disclosure, a key component key destruction control device is provided, the device comprising: A control circuit, a switch circuit, a drive circuit and a protection circuit are electrically connected in sequence, wherein the drive circuit is electrically connected to the input key-destroying power supply, and the protection circuit is electrically connected to the key component power supply terminal; wherein, The control circuit is used to receive a key-destroying instruction and generate a key-destroying signal according to the key-destroying instruction; The switch circuit is used to process the key destruction signal to generate a switch signal; The driving circuit is used to generate a key-destroying power supply in response to the switch signal; The protection circuit is used to process the key-destroying power supply and output the processed key-destroying power supply to the key component power supply terminal to prevent other components from being damaged when the key component is destroyed.

[0007] Furthermore, the control circuit comprises: Decoding chip, first working power supply, resistor R37, resistor R68, resistor R69, resistor R63; wherein, The first working power supply is electrically connected to pin 16 of the decoding chip, the first end of the resistor R37 is electrically connected to pin 1 of the decoding chip, the first end of the resistor R68 is electrically connected to pin 2 of the decoding chip, the first end of the resistor R69 is electrically connected to pin 3 of the decoding chip, the pin 6 of the decoding chip is electrically connected to the first end of the resistor R63, the second ends of the resistor R37, the second ends of the resistor R68 and the second ends of the resistor R69 are all grounded, the second end of the resistor R63 is electrically connected to the switching circuit, and the remaining pins of the decoding chip are suspended.

[0008] Further, the key destruction instruction includes a CTL_TFHY_L instruction and a CTL_TFHY_H instruction, and the key destruction signal includes a CTL_TFHY signal; wherein, Pin 2 of the decoding chip is used to receive the CTL_TFHY_L instruction, pin 3 of the decoding chip is used to receive the CTL_TFHY_H instruction, and the CTL_TFHY signal is output through pin 6 of the decoding chip.

[0009] Furthermore, the switch circuit comprises: a first sub-switch circuit and a second sub-switch circuit connected in parallel; The first sub-switch circuit includes a driving chip D23, a second working power supply, a transistor D25, a resistor R70, a resistor R71 and a capacitor C36; wherein, Pin 2 of the driving chip D23 is electrically connected to the control circuit, pin 3 of the driving chip D23 is grounded, pin 5 of the driving chip D23 is electrically connected to the second working power supply, pin 4 of the driving chip D23 is electrically connected to the first end of the resistor R70, the second end of the resistor R70 is electrically connected to the first end of the capacitor C36, the first end of the resistor R71, and the base of the transistor D25, respectively, the second end of the capacitor C36, the second end of the resistor R71, and the emitter of the transistor D25 are all grounded, pin 1 of the driving chip D23 is suspended, and the collector of the transistor D25 is electrically connected to the driving circuit; The second sub-switch circuit includes a driving chip D24, a transistor D26, a resistor R72, a resistor R73 and a capacitor C37; wherein, Pin 2 of the driving chip D24 is electrically connected to the control circuit, pin 3 of the driving chip D24 is grounded, pin 5 of the driving chip D24 is electrically connected to the second working power supply, pin 4 of the driving chip D24 is electrically connected to the first end of the resistor R72, the second end of the resistor R72 is electrically connected to the first end of the capacitor C37, the first end of the resistor R73, and the base of the transistor D26, respectively, the second end of the capacitor C37, the second end of the resistor R73, and the emitter of the transistor D26 are all grounded, pin 1 of the driving chip D24 is suspended, and the collector of the transistor D26 is electrically connected to the driving circuit. Further, the key destruction signal includes a CTL_TFHY_L signal, and the switch signal includes SW1_TFHY and SW2_TFHY signals; wherein, Pin 2 of the driver chip D23 is used to receive the CTL_TFHY signal, and the SW1_TFHY signal is output through the collector of the transistor D25; Pin 2 of the driver chip D24 is used to receive the CTL_TFHY signal, and the SW2_TFHY signal is output through the collector of the transistor D26.

[0010] Furthermore, the driving circuit comprises: CMOS chip D21, CMOS chip D22, resistor R74, resistor R75, resistor R76, resistor R77, resistor R78, capacitor C38 and capacitor C39; wherein, The first end of the capacitor C38 and the first end of the resistor R75 are both electrically connected to the S end of the CMOS chip D21, the second end of the capacitor C38, the second end of the resistor R75 and the first end of the resistor R74 are both electrically connected to the G end of the CMOS chip D21, the first end of the capacitor C39 and the first end of the resistor R78 are both electrically connected to the D end of the CMOS chip D21 and the S end of the CMOS chip D22, the second end of the capacitor C39, the second end of the resistor R78 and the first end of the resistor R77 are all electrically connected to the G end of the CMOS chip D22, the D end of the CMOS chip D22 is electrically connected to the first end of the resistor R76, the second end of the resistor R76 is electrically connected to the protection circuit, the second end of the resistor R74 is electrically connected to the collector of the transistor D25 and the drive circuit, and the second end of the resistor R77 is electrically connected to the collector of the transistor D26 and the drive circuit.

[0011] Furthermore, the protection circuit comprises: The third working power supply, diode D17 and diode D18; wherein, The anode of the diode D17 is electrically connected to the third working power supply, the anode of the diode D18 is electrically connected to the driving circuit, and the cathode of the diode D17 and the cathode of the diode D18 are both electrically connected to the key component power supply terminal.

[0012] According to a second aspect of an embodiment of the present disclosure, a method for using a key component key destruction control device is provided, the method comprising: Receiving a key-destroying instruction using a control circuit, and generating a key-destroying signal according to the key-destroying instruction; Processing the key-destroying signal by using a switch circuit to generate a switch signal; Using a driving circuit to respond to the switch signal to generate a key-destroying power supply; The key-destroying power supply is processed by a protection circuit, and the processed key-destroying power supply is output to the key component power supply terminal to prevent other components from being damaged when the key component is destroyed.

[0013] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects: In the embodiments of the present disclosure, through the above-mentioned key component key destruction control device and its use method, on the one hand, when the device is intercepted by a competitor, in order to prevent the data in the device from being obtained by the competitor, the central processor in the device triggers the key component key destruction operation, generates a key destruction instruction and sends it to the control circuit; the control circuit generates a key destruction signal according to the key destruction instruction; the switch circuit processes the key destruction signal to enhance the driving ability of the key destruction signal and generates a switch signal; the drive circuit responds to the switch signal to generate a high-voltage, high-current key destruction power supply; the key destruction power supply is sent to the power supply end of the key component through the protection circuit, physically destroying the key component and protecting the security of the key data; the protection circuit ensures that other circuits of the device are not affected by the key destruction power supply, so as to achieve the purpose of destroying only the key component. On the other hand, the key is destroyed according to the key destruction instruction to avoid misoperation and misoperation; and protective measures are taken to prevent damage to other components. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0015] Figure 1 A schematic diagram showing the structure of a key component key destruction control device in an exemplary embodiment of the present disclosure; Figure 2 A circuit diagram showing a control circuit in an exemplary embodiment of the present disclosure; Figure 3 A circuit diagram showing a switch circuit in an exemplary embodiment of the present disclosure; Figure 4 A circuit diagram showing a driving circuit in an exemplary embodiment of the present disclosure; Figure 5 A circuit diagram showing a protection circuit in an exemplary embodiment of the present disclosure; Figure 6 A step diagram showing a method for using a key component destruction control device in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0017] In addition, the accompanying drawings are only schematic illustrations of the embodiments of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0018] In this example implementation, a key component key destruction control device is first provided. Figure 1 As shown in , the key component key destruction control device may include: The control circuit, switch circuit, drive circuit and protection circuit are electrically connected in sequence, the drive circuit is electrically connected to the input key-destroying power supply, and the protection circuit is electrically connected to the key component power supply terminal; wherein, The control circuit is used to receive a key-destroying instruction and generate a key-destroying signal according to the key-destroying instruction; The switch circuit is used to process the key destruction signal and generate a switch signal; The driving circuit is used to generate a key-destroying power supply in response to a switch signal; The protection circuit is used to process the key-destroying power supply and output the processed key-destroying power supply to the key component power supply terminal to prevent other components from being damaged when the key component is destroyed.

[0019] Through the above-mentioned key component key destruction control device, on the one hand, when the device is intercepted by a competitor, in order to prevent the data in the device from being obtained by the competitor, the central processor in the device triggers the key component key destruction operation, generates a key destruction instruction and sends it to the control circuit; the control circuit generates a key destruction signal according to the key destruction instruction; the switch circuit processes the key destruction signal to enhance the driving ability of the key destruction signal and generates a switch signal; the drive circuit responds to the switch signal to generate a high-voltage, high-current key destruction power supply; the key destruction power supply is sent to the power supply end of the key component through the protection circuit, physically destroying the key component and protecting the security of the key data; the protection circuit ensures that other circuits of the device are not affected by the key destruction power supply, so as to achieve the purpose of destroying only the key component. On the other hand, the key is destroyed according to the key destruction instruction to avoid misoperation and misoperation; and protective measures are taken to prevent damage to other components.

[0020] Next, we will refer to Figures 1 to 5 The various parts of the above-mentioned key component key destruction control device in this example implementation are described in more detail.

[0021] In one embodiment, Figure 2 As shown, the control circuit includes: a decoding chip, a first working power supply, a resistor R37, a resistor R68, a resistor R69, and a resistor R63; wherein, The first working power supply is electrically connected to pin 16 of the decoding chip, the first end of resistor R37 is electrically connected to pin 1 of the decoding chip, the first end of resistor R68 is electrically connected to pin 2 of the decoding chip, the first end of resistor R69 is electrically connected to pin 3 of the decoding chip, pin 6 of the decoding chip is electrically connected to the first end of resistor R63, the second ends of resistor R37, resistor R68 and resistor R69 are all grounded, the second end of resistor R63 is electrically connected to the switching circuit, and the remaining pins of the decoding chip are suspended.

[0022] The key-destroying instructions include CTL_TFHY_L instructions and CTL_TFHY_H instructions, and the key-destroying signals include CTL_TFHY signals; wherein, pin 2 of the decoding chip is used to receive the CTL_TFHY_L instructions, pin 3 of the decoding chip is used to receive the CTL_TFHY_H instructions, and the CTL_TFHY signal is output through pin 6 of the decoding chip.

[0023] The control circuit is used to decode the key-destroying instruction, effectively avoiding misoperation and mis-triggering.

[0024] like Figure 2As shown, the input signals of the control circuit include CTL_TFHY_L, CTL_TFHY_H, and SL_WK_+3.3V, wherein SL_WK_+3.3V is the working power supply of the control circuit, and the remaining signals are key destruction instructions generated externally (such as a single-chip microcomputer, ARM, FPGA, etc.); the output signal includes CTL_TFHY, and the output signal is sent to the switch circuit.

[0025] In one embodiment, Figure 3 As shown, the switch circuit includes: a first sub-switch circuit and a second sub-switch circuit connected in parallel; The first sub-switch circuit includes a driving chip D23, a second working power supply, a transistor D25, a resistor R70, a resistor R71 and a capacitor C36; wherein, pin 2 of the driving chip D23 is electrically connected to the control circuit, pin 3 of the driving chip D23 is grounded, pin 5 of the driving chip D23 is electrically connected to the second working power supply, pin 4 of the driving chip D23 is electrically connected to the first end of the resistor R70, the second end of the resistor R70 is electrically connected to the first end of the capacitor C36, the first end of the resistor R71, and the base of the transistor D25, respectively, the second end of the capacitor C36, the second end of the resistor R71 and the emitter of the transistor D25 are all grounded, pin 1 of the driving chip D23 is suspended, and the collector of the transistor D25 is electrically connected to the driving circuit; The second sub-switch circuit includes a driving chip D24, a transistor D26, a resistor R72, a resistor R73 and a capacitor C37; wherein, pin 2 of the driving chip D24 is electrically connected to the control circuit, pin 3 of the driving chip D24 is grounded, pin 5 of the driving chip D24 is electrically connected to the second working power supply, pin 4 of the driving chip D24 is electrically connected to the first end of the resistor R72, the second end of the resistor R72 is electrically connected to the first end of the capacitor C37, the first end of the resistor R73, and the base of the transistor D26 respectively, the second end of the capacitor C37, the second end of the resistor R73 and the emitter of the transistor D26 are all grounded, pin 1 of the driving chip D24 is suspended, and the collector of the transistor D26 is electrically connected to the driving circuit.

[0026] Pin 2 of the driver chip D23 is used to receive the CTL_TFHY signal, and the SW1_TFHY signal is output through the collector of the transistor D25; Pin 2 of the driver chip D24 is used to receive the CTL_TFHY signal, and the SW2_TFHY signal is output through the collector of the transistor D26. The switch circuit is used to enhance the driving capability of the key-destroy command.

[0027] like Figure 3As shown, the input signals of the switch circuit include CTL_TFHY and SL_WK_+3.3V, where SL_WK_+3.3V is the working power supply of the switch circuit, and the CTL_TFHY signal is the key-destroying signal generated by the external control circuit; the output signal is sent to the drive circuit through transistors D25 and D26.

[0028] In one embodiment, Figure 4 As shown, the driving circuit includes: a CMOS chip D21, a CMOS chip D22, a resistor R74, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a capacitor C38 and a capacitor C39; wherein a first end of the capacitor C38 and a first end of the resistor R75 are electrically connected to the S end of the CMOS chip D21, a second end of the capacitor C38, a second end of the resistor R75 and a first end of the resistor R74 are electrically connected to the G end of the CMOS chip D21, and a first end of the capacitor C39 and a first end of the resistor R78 are electrically connected to the G end of the CMOS chip D21. It is electrically connected to the D end of the CMOS chip D21 and the S end of the CMOS chip D22, the second end of the capacitor C39, the second end of the resistor R78 and the first end of the resistor R77 are all electrically connected to the G end of the CMOS chip D22, the D end of the CMOS chip D22 is electrically connected to the first end of the resistor R76, the second end of the resistor R76 is electrically connected to the protection circuit, the second end of the resistor R74 is electrically connected to the collector of the transistor D25 and the driving circuit, and the second end of the resistor R77 is electrically connected to the collector of the transistor D26 and the driving circuit.

[0029] The driving circuit outputs the key-destroying power supply to the power supply terminal of the key component, while avoiding the phenomenon that a CMOS tube is damaged and causes malfunction.

[0030] like Figure 4 As shown, the input signal of the driving circuit is IN_HYPW, which is the input key-destroying power supply of the driving circuit; the output signal is OUT_TF_HYPW, which is the output key-destroying power supply after passing through the driving circuit.

[0031] In one embodiment, Figure 5 As shown, the protection circuit includes: a third working power supply, a diode D17 and a diode D18; wherein the anode of the diode D17 is electrically connected to the third working power supply, the anode of the diode D18 is electrically connected to the drive circuit, and the cathode of the diode D17 and the cathode of the diode D18 are both electrically connected to the power supply terminal of the key component.

[0032] The protection circuit ensures that other circuits of the device are not affected by the key-destroying power supply, so that only the key components are destroyed.

[0033] like Figure 5As shown, the input signals of the protection circuit are VCC_CARD and OUT_TF_HYPW, where VCC_CARD is the power required for the normal operation of the TF card, and OUT_TF_HYPW is the key-destroying power generated by the driving circuit; the output signal is TF_+3.3V, which is sent to the power terminal of the TF card.

[0034] This example implementation also provides a method for using a key component destruction control device. Figure 6 As shown in , the method for using the key component destruction control device may include: step S101 to step S104.

[0035] Step S101: receiving a key-destroying instruction by using a control circuit, and generating a key-destroying signal according to the key-destroying instruction; Step S102: Processing the key destruction signal by using a switch circuit to generate a switch signal; Step S103: using the driving circuit to respond to the switch signal to generate a key-destroying power supply; Step S104: the key-destroying power is processed by the protection circuit, and the processed key-destroying power is output to the key component power supply terminal to prevent other components from being damaged when the key component destroys the key.

[0036] Specifically, when the device is intercepted by enemy forces, in order to prevent the data in key components (such as TF cards) from being obtained by enemy forces, the device triggers the key destruction operation, generates a key destruction instruction and sends it to the control circuit. The control circuit generates a key destruction signal. The key destruction signal turns on the drive circuit and sends a high-voltage, high-current key destruction power supply (for example, 28V) to the power supply end of the key components through the protection circuit. The protection circuit ensures that other circuits of the device are not affected by the key destruction power supply, thereby achieving the purpose of destroying only the key components.

[0037] Through the above-mentioned key component key destruction control device and its use method, on the one hand, when the device is intercepted by a competitor, in order to prevent the data in the device from being obtained by the competitor, the central processor in the device triggers the key component key destruction operation, generates a key destruction instruction and sends it to the control circuit; the control circuit generates a key destruction signal according to the key destruction instruction; the switch circuit processes the key destruction signal to enhance the driving ability of the key destruction signal and generates a switch signal; the drive circuit responds to the switch signal to generate a high-voltage, high-current key destruction power supply; the key destruction power supply is sent to the power supply end of the key component through the protection circuit, physically destroying the key component and protecting the security of the key data; the protection circuit ensures that other circuits of the device are not affected by the key destruction power supply, so as to achieve the purpose of destroying only the key component. On the other hand, the key is destroyed according to the key destruction instruction to avoid misoperation and misoperation; and protective measures are taken to prevent damage to other components.

[0038] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. in the above description indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0040] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0041] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0042] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0043] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A key component destruction control device, characterized in that: The device includes: A control circuit, a switch circuit, a drive circuit and a protection circuit are electrically connected in sequence, wherein the drive circuit is electrically connected to the input key-destroying power supply, and the protection circuit is electrically connected to the key component power supply terminal; wherein, The control circuit is used to receive a key-destroying instruction and generate a key-destroying signal according to the key-destroying instruction; The switch circuit is used to process the key destruction signal to generate a switch signal; The driving circuit is used to generate a key-destroying power supply in response to the switch signal; The protection circuit is used to process the key-destroying power supply and output the processed key-destroying power supply to the key component power supply terminal to prevent other components from being damaged when the key component is destroyed.

2. The key component key destruction control device according to claim 1, characterized in that: The control circuit comprises: Decoding chip, first working power supply, resistor R37, resistor R68, resistor R69, resistor R63; wherein, The first working power supply is electrically connected to pin 16 of the decoding chip, the first end of the resistor R37 is electrically connected to pin 1 of the decoding chip, the first end of the resistor R68 is electrically connected to pin 2 of the decoding chip, the first end of the resistor R69 is electrically connected to pin 3 of the decoding chip, the pin 6 of the decoding chip is electrically connected to the first end of the resistor R63, the second ends of the resistor R37, the second ends of the resistor R68 and the second ends of the resistor R69 are all grounded, the second end of the resistor R63 is electrically connected to the switching circuit, and the remaining pins of the decoding chip are suspended.

3. The key component destruction control device according to claim 2, characterized in that: The key destruction instruction includes CTL_TFHY_L instruction and CTL_TFHY_H instruction, and the key destruction signal includes CTL_TFHY signal; wherein, Pin 2 of the decoding chip is used to receive the CTL_TFHY_L instruction, pin 3 of the decoding chip is used to receive the CTL_TFHY_H instruction, and the CTL_TFHY signal is output through pin 6 of the decoding chip.

4. The key component destruction control device according to claim 1, characterized in that: The switch circuit comprises: a first sub-switch circuit and a second sub-switch circuit connected in parallel; The first sub-switch circuit includes a driving chip D23, a second working power supply, a transistor D25, a resistor R70, a resistor R71 and a capacitor C36; wherein, Pin 2 of the driving chip D23 is electrically connected to the control circuit, pin 3 of the driving chip D23 is grounded, pin 5 of the driving chip D23 is electrically connected to the second working power supply, pin 4 of the driving chip D23 is electrically connected to the first end of the resistor R70, the second end of the resistor R70 is electrically connected to the first end of the capacitor C36, the first end of the resistor R71, and the base of the transistor D25, respectively, the second end of the capacitor C36, the second end of the resistor R71, and the emitter of the transistor D25 are all grounded, pin 1 of the driving chip D23 is suspended, and the collector of the transistor D25 is electrically connected to the driving circuit; The second sub-switch circuit includes a driving chip D24, a transistor D26, a resistor R72, a resistor R73 and a capacitor C37; wherein, Pin 2 of the driving chip D24 is electrically connected to the control circuit, pin 3 of the driving chip D24 is grounded, pin 5 of the driving chip D24 is electrically connected to the second working power supply, pin 4 of the driving chip D24 is electrically connected to the first end of the resistor R72, the second end of the resistor R72 is electrically connected to the first end of the capacitor C37, the first end of the resistor R73, and the base of the transistor D26, respectively, the second end of the capacitor C37, the second end of the resistor R73, and the emitter of the transistor D26 are all grounded, pin 1 of the driving chip D24 is suspended, and the collector of the transistor D26 is electrically connected to the driving circuit.

5. The key component destruction control device according to claim 4, characterized in that: The key-destroying signal includes a CTL_TFHY_L signal, and the switch signal includes SW1_TFHY and SW2_TFHY signals; wherein, Pin 2 of the driver chip D23 is used to receive the CTL_TFHY signal, and the SW1_TFHY signal is output through the collector of the transistor D25; Pin 2 of the driver chip D24 is used to receive the CTL_TFHY signal, and the SW2_TFHY signal is output through the collector of the transistor D26.

6. The key component destruction control device according to claim 4, characterized in that: The driving circuit comprises: CMOS chip D21, CMOS chip D22, resistor R74, resistor R75, resistor R76, resistor R77, resistor R78, capacitor C38 and capacitor C39; wherein, The first end of the capacitor C38 and the first end of the resistor R75 are both electrically connected to the S end of the CMOS chip D21, the second end of the capacitor C38, the second end of the resistor R75 and the first end of the resistor R74 are both electrically connected to the G end of the CMOS chip D21, the first end of the capacitor C39 and the first end of the resistor R78 are both electrically connected to the D end of the CMOS chip D21 and the S end of the CMOS chip D22, the second end of the capacitor C39, the second end of the resistor R78 and the first end of the resistor R77 are all electrically connected to the G end of the CMOS chip D22, the D end of the CMOS chip D22 is electrically connected to the first end of the resistor R76, the second end of the resistor R76 is electrically connected to the protection circuit, the second end of the resistor R74 is electrically connected to the collector of the transistor D25 and the drive circuit, and the second end of the resistor R77 is electrically connected to the collector of the transistor D26 and the drive circuit.

7. The key component key destruction control device according to claim 1, characterized in that: The protection circuit comprises: The third working power supply, diode D17 and diode D18; wherein, The anode of the diode D17 is electrically connected to the third working power supply, the anode of the diode D18 is electrically connected to the driving circuit, and the cathode of the diode D17 and the cathode of the diode D18 are both electrically connected to the key component power supply terminal.

8. A method for using a key component destruction control device, characterized in that: The method includes: Receiving a key-destroying instruction using a control circuit, and generating a key-destroying signal according to the key-destroying instruction; Processing the key-destroying signal by using a switch circuit to generate a switch signal; Using a driving circuit to respond to the switch signal to generate a key-destroying power supply; The key-destroying power supply is processed by a protection circuit, and the processed key-destroying power supply is output to the key component power supply terminal to prevent other components from being damaged when the key component is destroyed.

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