LDO circuit for VCM sampling structure
By designing an LDO circuit for VCM sampling structure, using a three-stage amplifier unit and a switch control unit, the problem of increased area and power consumption of the existing LDO circuit is solved, and higher integration and low power consumption are achieved.
Patent Information
- Application Number
- CN202411378989.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-02-07
AI Technical Summary
The existing LDO circuit for VCM sampling structure cannot guarantee that the voltage will be charged to the same voltage value within the sampling time after each Vdrop, resulting in an increase in the area of the entire LDO circuit and an increase in power consumption, making it difficult to achieve high integration and low chips. Power consumption requirements.
An LDO circuit including a first stage, a second stage and a third stage amplification unit, a switch control unit and a biasing unit is designed. The switch control unit controls the opening or closing of each amplification unit and a biasing unit respectively to reduce the opening or closing of each amplification unit and the biasing unit. Power consumption; the third-level amplification unit makes the MOS tube of the last stage amplification unit smaller, reducing the chip area.
The power consumption and area reduction of LDO circuits are achieved, the use range and accuracy of LDO circuits are improved, and the chips are highly integrated and low-power consumption requirements are supported.
Smart Images
Figure CN119402012A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and more particularly to an LDO circuit for a VCM sampling structure. Background Art
[0002] For SAR ADC (successive approximation ADC) circuit, the design of internal DAC (digital-to-analog conversion structure) is the most important, which determines the speed, power consumption and area size of ADC. The internal DAC structure includes traditional switch structure, monotonic switch structure, energy-saving switch structure and VCM-based switch structure. Among the above structures, the VCM-based structure has the most obvious comprehensive performance, which can achieve high-speed digital-to-analog conversion with lower power consumption and area; the difference between this structure and other structures is that it adds an external common-mode voltage, while the common-mode voltage required by the general structure on the market is very high. In practical applications, an external voltage source or an internal LDO (low-dropout linear regulator) is required to power the VCM, and the LDO is required to have good linear regulation (the amplitude of the output voltage change when the power supply voltage changes) and load regulation (the amplitude of the output voltage change when the load changes), which places high requirements on the LDO circuit.
[0003] For the VCM-based ADC sampling structure, during the conversion process, the reference voltage VCM will have a Vdrop (VCM voltage mutation value when charging starts) when sampling, and then continue to charge during the sampling period (ideally, charging to the voltage value before Vdrop). However, the existing LDO circuit used for the VCM sampling structure cannot guarantee that the voltage is charged to the same voltage value within the sampling time after each Vdrop, so the MOS tube of the last-stage amplifier circuit must be made particularly large to ensure that there is enough current to charge to the voltage before Vdrop; this makes the chip area occupied by the entire LDO circuit larger, and the power consumption also increases accordingly, which is not conducive to the development of highly integrated chips and the requirements for low power consumption.
[0004] Therefore, it is necessary to provide an improved LDO circuit for a VCM sampling structure to overcome the above defects. Summary of the invention
[0005] The object of the present invention is to provide an LDO circuit for a VCM sampling structure. The LDO circuit for a VCM sampling structure of the present invention has a simple structure, occupies a small area, can directly use a digital voltage as an input voltage, can flexibly adjust the voltage value of the output VCM voltage, reduces the power consumption of the entire circuit, and improves the application range of the LDO circuit.
[0006] To achieve the above-mentioned object, the present invention provides an LDO circuit for a VCM sampling structure, comprising a first-stage amplifying unit, a second-stage amplifying unit, a third-stage amplifying unit, a switch control unit and a bias unit, wherein the switch control unit is respectively connected to the first-stage amplifying unit, the second-stage amplifying unit, the third-stage amplifying unit and the bias unit, the switch control unit can selectively output a high level or a low level to control the opening or closing of the first-stage amplifying unit, the second-stage amplifying unit, the third-stage amplifying unit and the bias unit, the first-stage amplifying unit, the second-stage amplifying unit and the third-stage amplifying unit are sequentially connected and are all connected to an external power supply, an external reference voltage is input to the first-stage amplifying unit, the first-stage amplifying unit, the second-stage amplifying unit and the third-stage amplifying unit amplify the input external reference voltage in turn, and the third-stage amplifying unit outputs a VCM voltage of a set value; the bias unit is connected to the first-stage amplifying unit to provide the first-stage amplifying unit with a required working current.
[0007] Preferably, the switch control unit has two output terminals, and the output levels of the two output terminals are in opposite phases.
[0008] Preferably, the first-stage amplifying unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube, an external reference voltage is input to the gate of the first MOS tube, the sources of the first MOS tube and the second MOS tube are connected to the drain of the fifth MOS tube, the gate of the fifth MOS tube is connected to the bias unit, and the source thereof is grounded; the sources of the third MOS tube and the fourth MOS tube are connected to the external power supply, the drain of the third MOS tube is connected to the drain of the first MOS tube, the drain of the second MOS tube is connected to the drain of the fourth MOS tube, the gate of the third MOS tube is connected to its drain, and is connected to the second-stage amplifying unit; the gate of the fourth MOS tube is connected to its drain, and is connected to the second-stage amplifying unit.
[0009] Preferably, the second-stage amplification unit includes a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a ninth MOS tube, the sources of the sixth MOS tube and the seventh MOS tube are connected to an external power supply, the gate of the sixth MOS tube is connected to the gate of the fourth MOS tube, the drain of the sixth MOS tube is connected to the drain of the eighth MOS tube and connected to the third-stage amplification unit, the gate of the seventh MOS tube is connected to the gate of the third MOS tube, and the drain of the seventh MOS tube is connected to the drain of the ninth MOS tube; the sources of the eighth MOS tube and the ninth MOS tube are grounded, and the gates of the eighth MOS tube and the ninth MOS tube are connected together and connected to the drain of the ninth MOS tube.
[0010] Preferably, the third-stage amplification unit includes a tenth MOS tube, a first resistor and a second resistor, the source of the tenth MOS tube is connected to the external power supply, the gate thereof is connected to the drain of the sixth MOS tube, the drain of the tenth MOS tube outputs the VCM voltage and is connected to one end of the first resistor; the other end of the first resistor, the gate of the second MOS tube, and one end of the second resistor are connected together, and the other end of the second resistor is grounded.
[0011] Preferably, the third-stage amplifying unit further includes a first capacitor, one end of the first capacitor is connected to the drain of the tenth MOS tube, and the other end is grounded.
[0012] Preferably, the LDO circuit for the VCM sampling structure further includes a current control unit, which includes an eleventh MOS tube and a twelfth MOS tube, wherein the source of the eleventh MOS tube is connected to the bias unit, the gate thereof is connected to an output end of the switch control unit, the drain of the eleventh MOS tube is connected to the gate of the fifth MOS tube; the gate and drain of the twelfth MOS tube are connected together and to the drain of the eleventh MOS tube, and the source thereof is grounded.
[0013] Preferably, the bias unit includes a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, an eleventh MOS tube, a third resistor and a second capacitor; the gates of the thirteenth MOS tube and the fourteenth MOS tube are connected together and connected to the drain of the sixteenth MOS tube, the source of the thirteenth MOS tube is connected to one end of the third resistor, the other end of the third resistor and the source of the fourteenth MOS tube are grounded, the drain of the thirteenth MOS tube is connected to the source of the fifteenth MOS tube, the drain of the fourteenth MOS tube is connected to the source of the sixteenth MOS tube, and the gates of the fifteenth MOS tube and the sixteenth MOS tube are connected together and connected to the other output end of the switch control unit , the drain of the fifteenth MOS tube is connected to the drain of the seventeenth MOS tube, the drain of the sixteenth MOS tube is connected to the drain of the eighteenth MOS tube, the gates of the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube are connected together and connected to one end of the second capacitor, the sources of the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube and the other end of the second capacitor are all connected to the external power supply, the drain of the nineteenth MOS tube is connected to the source of the twentieth MOS tube, the gate of the twentieth MOS tube is connected to an output end of the switch control unit, and the drain thereof is connected to the source of the eleventh MOS tube; the source of the twenty-first MOS tube is connected to the gate of the seventeenth MOS tube, the drain thereof is connected to the drain of the seventeenth MOS tube, and the gate thereof is connected to an output end of the switch control unit.
[0014] Preferably, the switch control unit includes a plurality of switch tubes, each of which is a MOS tube, the drain of each switch tube is connected to the drain of the corresponding MOS tube, and the source of each switch tube is grounded or connected to an external power supply; the gate of the switch tube connected to the ninth MOS tube and the twelfth MOS tube forms an output end of the switch control unit, and the gate of the switch tube connected to the third MOS tube, the fourth MOS tube and the sixth MOS tube forms another output end of the switch control unit.
[0015] Compared with the prior art, the LDO circuit for the VCM sampling structure of the present invention is provided with a switch control unit to respectively control the opening or closing of the first-stage amplification unit, the second-stage amplification unit, the third-stage amplification unit and the bias unit, so that each unit can be closed separately when it is idle, thereby greatly reducing the power consumption required by the entire circuit; at the same time, since the three-stage amplification unit is provided, the MOS tube of the last-stage (third-stage) amplification unit can be implemented using a relatively small tube, thereby greatly reducing the chip area occupied by the entire LDO circuit, further reducing the chip area, and facilitating the high integration of the chip.
[0016] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a structural schematic diagram of the LDO circuit used for the VCM sampling structure of the present invention.
[0018] Figure 2 For Figure 1 Schematic diagram of the structure of the bias unit shown. DETAILED DESCRIPTION
[0019] Embodiments of the present invention are now described with reference to the accompanying drawings, in which similar element numbers represent similar elements. As described above, the present invention provides an LDO circuit for a VCM sampling structure. The LDO circuit for a VCM sampling structure of the present invention has a simple structure, occupies a small area, can directly use a digital voltage as an input voltage, can flexibly adjust the voltage value of the output VCM voltage, reduces the power consumption of the entire circuit, and improves the application range of the LDO circuit.
[0020] Please refer to Figure 1 , Figure 1The present invention is a schematic diagram of the structure of the LDO circuit for the VCM sampling structure. As shown in the figure, the LDO circuit for the VCM sampling structure of the present invention includes a first-stage amplification unit, a second-stage amplification unit, a third-stage amplification unit, a switch control unit and a bias unit, the switch control unit is respectively connected to the first-stage amplification unit, the second-stage amplification unit, the third-stage amplification unit and the bias unit, the switch control unit can selectively output a high level or a low level to control the opening or closing of the first-stage amplification unit, the second-stage amplification unit, the third-stage amplification unit and the bias unit, the first-stage amplification unit, the second-stage amplification unit, and the third-stage amplification unit are sequentially connected and are all connected to the external power supply AVD, the external reference voltage VIN is input to the first-stage amplification unit, the first-stage amplification unit, the second-stage amplification unit, and the third-stage amplification unit amplify the input external reference voltage VIN in turn, and the third-stage amplification unit outputs a VCM voltage of a set value; the bias unit is connected to the first-stage amplification unit to provide the required working current for the first-stage amplification unit. As described above, in the LDO circuit for the VCM sampling structure of the present invention, since a switch control unit is provided to respectively control the opening or closing of the first-stage amplification unit, the second-stage amplification unit, the third-stage amplification unit and the bias unit, each unit can be individually closed when it is idle, thereby greatly reducing the power consumption required by the entire circuit; at the same time, since a three-stage amplification unit is provided, the MOS tube of the last-stage (third-stage) amplification unit can be implemented using a relatively small tube, thereby greatly reducing the chip area occupied by the entire LDO circuit, further reducing the chip area, and facilitating the high integration of the chip.
[0021] The first-stage amplifying unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4 and a fifth MOS tube M5. The external reference voltage VIN is input to the gate of the first MOS tube M1. The sources of the first MOS tube M1 and the second MOS tube M2 are connected to the drain of the fifth MOS tube M5. The gate of the fifth MOS tube M5 is connected to the bias unit, and the source thereof is grounded. The sources of the third MOS tube M3 and the fourth MOS tube M4 are connected to the external power supply AVD. The drain of the third MOS tube M3 is connected to the drain of the first MOS tube M1. The drain of the second MOS tube M2 is connected to the drain of the fourth MOS tube M4. The gate of the third MOS tube M3 is connected to its drain and is connected to the second-stage amplifying unit. The gate of the fourth MOS tube M4 is connected to its drain and is connected to the second-stage amplifying unit. In the first-stage amplifying unit, the bias unit provides bias current for each MOS tube of the first-stage amplifying unit through the fifth MOS tube M5, and the first MOS tube M1 and the second MOS tube M2 together form an operational amplifier input pair of the first-stage amplifying unit to amplify the input reference voltage VIN, and the third MOS tube M3 and the fourth MOS tube M4 together form an operational amplifier output pair of the first-stage amplifying unit to output the current generated on the first-stage amplifying unit to the second-stage amplifying unit.
[0022] The second-stage amplifying unit includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8 and a ninth MOS tube M9. The sources of the sixth MOS tube M6 and the seventh MOS tube M7 are both connected to the external power supply AVD, the gate of the sixth MOS tube M6 is connected to the gate of the fourth MOS tube M4, the drain of the sixth MOS tube M6 is connected to the drain of the eighth MOS tube M8 and to the third-stage amplifying unit, the gate of the seventh MOS tube M7 is connected to the gate of the third MOS tube M3, and the drain of the seventh MOS tube M7 is connected to the drain of the ninth MOS tube M9; the sources of the eighth MOS tube M8 and the ninth MOS tube M9 are both grounded, the gates of the eighth MOS tube M8 and the ninth MOS tube M9 are connected together and to the drain of the ninth MOS tube M9. In the second amplifying unit, the seventh MOS tube M7 and the sixth MOS tube M6 together form an operational amplifier input pair of the second-stage amplifying unit, and form a current mirror, mirroring the current of the third MOS tube M3 and the fourth MOS tube M4, so that the current on the first-stage amplifying unit can be input to the second-stage amplifying unit, and the eighth MOS tube M8 and the ninth MOS tube M9 amplify the input current again and form an operational amplifier output pair of the second-stage amplifying unit, so as to output the current generated on the second-stage amplifying unit to the third-stage amplifying unit.
[0023] The third-stage amplification unit includes a tenth MOS tube M10, a first resistor R1 and a second resistor R2. The source of the tenth MOS tube M10 is connected to the external power supply AVD, and the gate thereof is connected to the drain of the sixth MOS tube M6. The drain of the tenth MOS tube M10 outputs a VCM voltage and is connected to one end of the first resistor R1; the other end of the first resistor R1, the gate of the second MOS tube M2, and one end of the second resistor R2 are connected together, and the other end of the second resistor R2 is grounded. The tenth MOS tube M10 of the third-stage amplification unit receives and amplifies the current output by the eighth MOS tube M8 of the second amplification unit, and then outputs the required VCM voltage through the drain of the tenth MOS tube M10; in the present invention, since the tenth MOS tube M10 is at the last stage of the entire amplification unit, and before that, the first and second stage amplification units amplify the input voltage / current, so that the requirements for the amplification multiple of the third-stage amplification unit in the entire circuit are not high, so that the tenth MOS tube M10 can be implemented using a relatively small tube to reduce the chip area occupied by the entire LDO circuit, further reduce the chip area, and also reduce the power consumption. In addition, a first resistor R1 and a second resistor R2 are also provided in the third-stage amplification unit. The first resistor R1 and the second resistor R2 are voltage-dividing resistors, which can flexibly adjust the voltage value of the output voltage VCM, so that no matter what voltage the external reference voltage VIN is connected to, the output voltage VCM of the desired voltage value can be obtained by adjusting the resistance values of the first resistor R1 and the second resistor R2, so that the value of the output voltage VCM is adjustable to adapt to different application scenarios; in addition, due to the voltage-dividing effect of the first resistor R1 and the second resistor R2, the desired output voltage VCM can also be obtained by directly using the digital voltage input for voltage division, which further expands the application range of the entire circuit. In addition, as a preferred embodiment of the present invention, the third-stage amplification unit also includes a first capacitor C1, one end of the first capacitor C1 is connected to the drain of the tenth MOS tube M10, and the other end is grounded; in the present invention, the first capacitor C1 is a load capacitor, and after simulation verification, the capacitance of the first capacitor C1 is preferably half of the total capacitance of the capacitor array. By setting the first capacitor C1, the Vdrop value of the entire circuit is as small as possible, so that the VCM voltage can be charged to the ideal value at the maximum amplitude during the sampling period.
[0024] In addition, the LDO circuit for the VCM sampling structure of the present invention further includes a current control unit, which includes an eleventh MOS tube M11 and a twelfth MOS tube M12. The source of the eleventh MOS tube M11 is connected to the bias unit, and the gate thereof is connected to an output terminal PD of the switch control unit. The drain of the eleventh MOS tube M11 is connected to the gate of the fifth MOS tube M5, so that the eleventh MOS tube M11 is turned on or off under the control of the output terminal PD of the switch control unit, thereby controlling the bias current of the bias unit to be input to the first-stage amplification unit; the gate and drain of the twelfth MOS tube M13 are connected together and connected to the drain of the eleventh MOS tube M11, and the source thereof is grounded. The twelfth MOS tube M12 provides a bias voltage for the fifth MOS tube M5, so that the fifth MOS tube M5 can provide a tail current of the bias current for the first-stage amplification unit.
[0025] Please refer to Figure 2The bias unit includes a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a third resistor R3 and a second capacitor C2; the gates of the thirteenth MOS tube M13 and the fourteenth MOS tube M14 are connected together and connected to the drain of the sixteenth MOS tube M16, the source of the thirteenth MOS tube M13 is connected to one end of the third resistor R3, the other end of the third resistor R3 and the source of the fourteenth MOS tube M14 are grounded, the drain of the thirteenth MOS tube M13 is connected to the source of the fifteenth MOS tube M15, the drain of the fourteenth MOS tube M14 is connected to the source of the sixteenth MOS tube M16, the gates of the fifteenth MOS tube M15 and the sixteenth MOS tube M16 are connected together and connected to the other output end PDN of the switch control unit, and the The drain of the fifth MOS tube M15 is connected to the drain of the seventeenth MOS tube M17, the drain of the sixteenth MOS tube M16 is connected to the drain of the eighteenth MOS tube M18, the gates of the seventeenth MOS tube M17, the eighteenth MOS tube M18 and the nineteenth MOS tube M19 are connected together and connected to one end of the second capacitor C2, the sources of the seventeenth MOS tube M17, the eighteenth MOS tube M18 and the nineteenth MOS tube M19 and the other end of the second capacitor C2 are all connected to the external power supply AVD, the drain of the nineteenth MOS tube M19 is connected to the source of the twentieth MOS tube M20, the gate of the twentieth MOS tube M20 is connected to an output end PD of the switch control unit, and the drain thereof is connected to the source of the eleventh MOS tube M11; the source of the twenty-first MOS tube M21 is connected to the gate of the seventeenth MOS tube M17, the drain thereof is connected to the drain of the seventeenth MOS tube M17, and the gate thereof is connected to an output end PD of the switch control unit. In the bias unit, the gate voltages of the thirteenth MOS tube M13 and the fourteenth MOS tube M14 are the same, and the voltage from the gate to the ground is the gate-source voltage of the fourteenth MOS tube M14, which is also equal to the sum of the gate-source voltage of the thirteenth MOS tube M13 and the voltage drop of the third resistor R3. Therefore, the current branch current is the ratio of the gate-source voltage difference of the two MOS tubes (the thirteenth MOS tube M13 and the fourteenth MOS tube M14) to the resistance value of the third resistor R3. The fifteenth MOS tube M15 and the sixteenth MOS tube M16 provide a common source and common gate structure, which can improve the output impedance and make the drain output resistance of the fifteenth MOS tube M15 larger, thereby increasing the anti-interference ability of the entire circuit. The eighteenth MOS tube M18, the seventeenth MOS tube M17 and the nineteenth MOS tube M19 are current mirrors, which copy the branch current of the seventeenth MOS tube M17 to the branch of the nineteenth MOS tube M19. The second capacitor C2 (about 1pF) improves the PSRR (power supply rejection ratio) of the bias current Ibias output by the bias unit.The bias unit adjusts the value of the bias current Ibias by adjusting the resistance of the third resistor R3. Compared with the conventional bias unit circuit, the bias unit circuit of the present invention has low power consumption and does not require an additional operational amplifier.
[0026] In the present invention, the switch control unit includes a plurality of switch tubes, each of which is a MOS tube, the drain of each switch tube is connected to the drain of the corresponding MOS tube, and the source of each switch tube is grounded or connected to an external power supply AVD; the gate of the switch tube connected to the ninth MOS tube M9 and the twelfth MOS tube M12 forms an output terminal PD of the switch control unit, and the gate of the switch tube connected to the third MOS tube M3, the fourth MOS tube M4 and the sixth MOS tube M6 forms another output terminal PDN of the switch control unit. The connections of the switch tubes are as follows: Figure 1 As shown, the specific connection and function of each switch tube are well known to the staff in this field, and will not be described in detail here. In the present invention, different high and low levels are output by one output terminal PD and another output terminal PDN of the switch control unit to control the conduction and cutoff of each corresponding MOS tube, so as to coordinate the output of the accurate VCM voltage of the entire circuit; and the switch control unit is connected to the external pulse voltage so that one output terminal PD and another output terminal PDN simultaneously input high and low levels with opposite phases.
[0027] In the LDO circuit for the VCM sampling structure of the present invention, when the external power supply AVD is powered on, adjusting the resistance value of the third resistor R3 in the bias unit can adjust the branch currents of the thirteenth MOS tube M13, the fifteenth MOS tube M15, and the seventeenth MOS tube M17. Since the current mirror of the seventeenth MOS tube M17 and the nineteenth MOS tube M19 copies the current to the nineteenth MOS tube M19, a bias current Ibias is formed. In the LDO circuit, the bias current Ibas is copied to the fifth MOS tube M5 through the current mirror of the twelfth MOS tube M12 and the fifth MOS tube M5, and serves as a tail current for the first-stage amplifier unit; when the external reference voltage VIN is input, the external reference voltage VIN amplifies the voltage signal to the gate of the third MOS tube M3 and the seventh MOS tube M7 through the first-stage unit, and then amplifies the voltage signal to the gate of the ninth MOS tube M9 and the eighth MOS tube M8 through the seventh MOS tube M7 and the ninth MOS tube M9, and the amplifier composed of the eighth MOS tube M8 and the sixth MOS tube M6 amplifies the voltage signal to the gate of the tenth MOS tube M10, and finally the tenth MOS tube M10 amplifies the voltage signal and outputs the VCM voltage; and in the above process, because the operational amplifier input virtual short needs to be satisfied, that is, the voltage is the same, the node voltage between the first resistor R1 and the second resistor R2 is equal to the reference voltage VIN, so that the required voltage value of the VCM voltage can be obtained by adjusting the resistance values of the first resistor R1 and the second resistor R2.
[0028] In summary, the LDO circuit for the VCM sampling structure of the present invention is provided with a switch control unit to respectively control the opening or closing of the first-stage amplification unit, the second-stage amplification unit, the third-stage amplification unit and the bias unit, and specifically can control the conduction or cutoff of each corresponding MOS tube, so that each unit can be individually closed when it is idle, thereby greatly reducing the power consumption required by the entire circuit; at the same time, since the three-stage amplification unit is provided, the MOS tube (the tenth MOS tube M10) of the last-stage (third-stage) amplification unit can be implemented using a relatively small MOS tube, thereby greatly reducing the chip area occupied by the entire LDO circuit, further reducing the chip area, and facilitating the high integration of the chip; and in the third-stage amplification unit, the first resistor R1 and the second resistor R2 are provided as voltage-dividing resistors, so that the VCM voltage with a precise voltage value can be output by adjusting the resistance values of the first resistor R1 and the second resistor R2, thereby improving the accuracy of the entire circuit.
[0029] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.
Claims
1. An LDO circuit for a VCM sampling structure, characterized in that: The invention comprises a first-stage amplifying unit, a second-stage amplifying unit, a third-stage amplifying unit, a switch control unit and a bias unit. The switch control unit is respectively connected to the first-stage amplifying unit, the second-stage amplifying unit, the third-stage amplifying unit and the bias unit. The switch control unit can selectively output a high level or a low level to control the opening or closing of the first-stage amplifying unit, the second-stage amplifying unit, the third-stage amplifying unit and the bias unit. The first-stage amplifying unit, the second-stage amplifying unit and the third-stage amplifying unit are sequentially connected and are all connected to an external power supply. An external reference voltage is input to the first-stage amplifying unit. The first-stage amplifying unit, the second-stage amplifying unit and the third-stage amplifying unit amplify the input external reference voltage in turn, and the third-stage amplifying unit outputs a VCM voltage of a set value. The bias unit is connected to the first-stage amplifying unit to provide the first-stage amplifying unit with a required working current.
2. The LDO circuit for VCM sampling structure as claimed in claim 1, characterized in that: The switch control unit has two output terminals, and the phases of output levels of the two output terminals are opposite.
3. The LDO circuit for VCM sampling structure as claimed in claim 2, characterized in that: The first-stage amplification unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube. An external reference voltage is input to the gate of the first MOS tube. The sources of the first MOS tube and the second MOS tube are both connected to the drain of the fifth MOS tube. The gate of the fifth MOS tube is connected to the bias unit, and the source thereof is grounded. The sources of the third MOS tube and the fourth MOS tube are both connected to the external power supply. The drain of the third MOS tube is connected to the drain of the first MOS tube. The drain of the second MOS tube is connected to the drain of the fourth MOS tube. The gate of the third MOS tube is connected to its drain and is connected to the second-stage amplification unit. The gate of the fourth MOS tube is connected to its drain and is connected to the second-stage amplification unit.
4. The LDO circuit for VCM sampling structure as claimed in claim 3, characterized in that: The second-stage amplification unit includes a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a ninth MOS tube, the source electrodes of the sixth MOS tube and the seventh MOS tube are connected to an external power supply, the gate electrode of the sixth MOS tube is connected to the gate electrode of the fourth MOS tube, the drain electrode of the sixth MOS tube is connected to the drain electrode of the eighth MOS tube and connected to the third-stage amplification unit, the gate electrode of the seventh MOS tube is connected to the gate electrode of the third MOS tube, and the drain electrode of the seventh MOS tube is connected to the drain electrode of the ninth MOS tube; The sources of the eighth MOS tube and the ninth MOS tube are both grounded, and the gates of the eighth MOS tube and the ninth MOS tube are connected together and connected to the drain of the ninth MOS tube.
5. The LDO circuit for VCM sampling structure as claimed in claim 4, characterized in that: The third-stage amplification unit includes a tenth MOS tube, a first resistor and a second resistor. The source of the tenth MOS tube is connected to the external power supply, and the gate thereof is connected to the drain of the sixth MOS tube. The drain of the tenth MOS tube outputs a VCM voltage and is connected to one end of the first resistor. The other end of the first resistor, the gate of the second MOS tube, and one end of the second resistor are connected together, and the other end of the second resistor is grounded.
6. The LDO circuit for VCM sampling structure as claimed in claim 5, characterized in that: The third-stage amplifying unit also includes a first capacitor, one end of which is connected to the drain of the tenth MOS tube, and the other end of which is grounded.
7. The LDO circuit for VCM sampling structure as claimed in claim 5, characterized in that: It also includes a current control unit, which includes an eleventh MOS tube and a twelfth MOS tube. The source of the eleventh MOS tube is connected to the bias unit, the gate of the eleventh MOS tube is connected to an output end of the switch control unit, and the drain of the eleventh MOS tube is connected to the gate of the fifth MOS tube; the gate and drain of the twelfth MOS tube are connected together and connected to the drain of the eleventh MOS tube, and the source of the twelfth MOS tube is grounded.
8. The LDO circuit for VCM sampling structure as claimed in claim 7, characterized in that: The bias unit includes a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, an eleventh MOS tube, a third resistor and a second capacitor; the gates of the thirteenth MOS tube and the fourteenth MOS tube are connected together and connected to the drain of the sixteenth MOS tube, the source of the thirteenth MOS tube is connected to one end of the third resistor, the other end of the third resistor and the source of the fourteenth MOS tube are grounded, the drain of the thirteenth MOS tube is connected to the source of the fifteenth MOS tube, the drain of the fourteenth MOS tube is connected to the source of the sixteenth MOS tube, the gates of the fifteenth MOS tube and the sixteenth MOS tube are connected together and connected to the other output end of the switch control unit, and the The drain of the fifteenth MOS tube is connected to the drain of the seventeenth MOS tube, the drain of the sixteenth MOS tube is connected to the drain of the eighteenth MOS tube, the gates of the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube are connected together and connected to one end of the second capacitor, the sources of the seventeenth MOS tube, the eighteenth MOS tube and the nineteenth MOS tube and the other end of the second capacitor are all connected to the external power supply, the drain of the nineteenth MOS tube is connected to the source of the twentieth MOS tube, the gate of the twentieth MOS tube is connected to an output end of the switch control unit, and the drain thereof is connected to the source of the eleventh MOS tube; the source of the twenty-first MOS tube is connected to the gate of the seventeenth MOS tube, the drain thereof is connected to the drain of the seventeenth MOS tube, and the gate thereof is connected to an output end of the switch control unit.
9. The LDO circuit for a VCM sampling structure as claimed in claim 8, characterized in that: The switch control unit includes a plurality of switch tubes, each of which is a MOS tube, the drain of each switch tube is connected to the drain of the corresponding MOS tube, and the source of each switch tube is grounded or connected to an external power supply; the gate of the switch tube connected to the ninth MOS tube and the twelfth MOS tube forms an output end of the switch control unit, and the gate of the switch tube connected to the third MOS tube, the fourth MOS tube and the sixth MOS tube forms another output end of the switch control unit.