Image processing system and image sensor

Abstract

The invention provides an image processing system and an image sensor, the image processing system is electrically connected to a pixel array, the image processing system comprises a plurality of comparators and a pixel column circuit electrically connected to the pixel array, and when the pixel voltage of the pixel column circuit is equal to a preset voltage, the output level of the comparators is overturned; the clock tree unit outputs a counting clock signal; and the plurality of counters are electrically connected to the comparator, receive the counting starting signal, count pulses of the counting clock signal under delay triggering of the counting starting signal, and stop counting and output a count value as an analog-to-digital conversion quantized value of the pixel voltage signal when the output level of the comparator is overturned. The invention provides an image processing system and an image sensor, which can solve the problem of vertical blocks appearing in an image and reduce the power consumption of image processing.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to an image processing system and an image sensor. Background Art

[0002] In CMOS image sensors, single slope analog to digital converters (SS ADCs) are used to perform analog-to-digital conversion of pixel signals. One column of pixel units corresponds to one column of single slope analog to digital converters. When the number of columns in the pixel array is large, the load of the timing signal control increases, so the rising edge switching of the timing signal slows down. Therefore, in the pixel array, the starting phase of each counter is different, and the phase difference will eventually lead to differences in the final values ​​of analog-to-digital conversion quantization between pixel columns. Therefore, when the image sensor is imaging, the image scene that reaches the preset brightness appears vertically blocked, resulting in vertical block problems in the image. Summary of the invention

[0003] The object of the present invention is to provide an image processing system and an image sensor, which can solve the problem of vertical blocks appearing in images and reduce the power consumption of image processing.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0005] The present invention provides an image processing system, the image processing system is electrically connected to a pixel array, and the image processing system comprises:

[0006] A plurality of comparators, electrically connected to a pixel column circuit of the pixel array, wherein when a pixel voltage of the pixel column circuit is equal to a preset voltage, an output level of the comparator is flipped;

[0007] a clock tree unit, the clock tree unit outputting a counting clock signal; and

[0008] A plurality of counters are electrically connected to the comparator, and the counters receive a counting start signal. Under the delayed triggering of the counting start signal, the counters count the pulses of the counting clock signal. When the output level of the comparator flips, the counters stop counting and output the counting value as the analog-to-digital conversion quantization value of the pixel voltage signal.

[0009] In one embodiment of the present invention, the image processing system includes a clock delay unit, the clock delay unit having a first input end and a second input end, the first input end receives the counting clock signal, the second input end receives the counting start signals of the plurality of counters, the clock delay unit outputs a first counting signal and a second counting signal, wherein the level flip time of the first counting signal is later than the level flip time of the counting start signal.

[0010] In one embodiment of the present invention, the image processing system includes a phase selection unit, which is electrically connected to the clock delay unit and receives the first counting signal and the second counting signal. The output end of the phase selection unit is electrically connected to the counter and outputs the counting clock signal to the counter, and the counter counts the pulses of the counting clock signal.

[0011] In one embodiment of the present invention, the counter receives a process start signal. When the process start signal is at a high level, the counter starts and counts the rising edge, falling edge and initial high level signal of the counting clock signal.

[0012] In one embodiment of the present invention, the second counting signal and the first counting signal are inverted signals to each other, wherein the level of the first counting signal is high after being flipped, and the level of the second counting signal is low after being flipped, wherein when the initial value of the counter is an even number, the counting clock signal is the first counting signal, and when the initial value of the counter is an odd number, the counting clock signal is the second counting signal.

[0013] In one embodiment of the present invention, the plurality of counting start signals are respectively output to the counters of different pixel column circuits. At the rising edge of the process start signal, the counting start signal flips to a high level, allowing the process start signals in the plurality of pixel column circuits to have a phase difference.

[0014] In one embodiment of the present invention, the counter has a pixel reset signal counting stage and a pixel voltage signal counting stage. In the pixel reset signal counting stage, the counter obtains a first count value, which is an analog-to-digital conversion quantization value of the pixel reset signal. In the pixel voltage signal counting stage, the counter obtains a second count value, which is the difference between the first count value and the second count value.

[0015] In one embodiment of the present invention, between the pixel reset signal counting stage and the pixel voltage signal counting stage, when the plurality of process start signals are at a low level, the counting clock signal is reset and maintained at a high level until the counter enters the pixel signal counting stage.

[0016] In one embodiment of the present invention, the preset voltage is a ramp voltage, the first input terminal of the comparator receives the pixel voltage signal output by the pixel column circuit, the second input terminal of the comparator receives the ramp voltage signal, and when the voltage value of the ramp voltage signal drops to be equal to the voltage value of the pixel voltage signal, the output level of the comparator flips.

[0017] The present invention provides an image sensor, comprising:

[0018] a pixel array comprising a plurality of pixel column circuits; and

[0019] An image processing system as described above, wherein the image processing system is electrically connected to the pixel column circuit, receives a pixel voltage signal from the pixel column circuit, and obtains an analog-to-digital conversion quantization value of the pixel voltage signal.

[0020] As described above, the present invention provides an image processing system and an image sensor, which can compensate for the imaging vertical block problem caused by the phase difference generated in the clock signal transmission, reduce the error problem caused by the algorithm, and improve the image quality. The image sensor provided by the present invention has lower energy consumption.

[0021] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 FIG. 1 is a schematic diagram of an image in which a vertical block problem occurs in an embodiment of the present invention.

[0024] Figure 2 FIG. 4 is a schematic diagram of the structure of an image processing system in one embodiment of the present invention.

[0025] Figure 3 Schematic diagram of the structure of a comparator and a counter in one embodiment of the present invention.

[0026] Figure 4 FIG. 4 is a schematic diagram of the working principle of a ramp voltage in an embodiment of the present invention.

[0027] Figure 5 Schematic diagram of the counting structure of a counter in one embodiment of the present invention.

[0028] Figure 6 Schematic diagram of the counting principle of a counter in one embodiment of the present invention.

[0029] Figure 7 Schematic diagram of the phase difference of process start signals corresponding to different pixel column circuits in one embodiment of the present invention.

[0030] Figure 8 FIG. 4 is a schematic diagram of the counting principle of a pixel cancellation method in an embodiment of the present invention.

[0031] Fig. 9 A schematic diagram of a counting signal with errors under a pixel cancellation method according to an embodiment of the present invention.

[0032] Fig.10 Schematic diagram of signal transmission between a clock delay unit and a phase selection unit in one embodiment of the present invention.

[0033] Fig.11 FIG. 4 is a schematic diagram of clock signal control of a clock tree unit according to an embodiment of the present invention.

[0034] In the figure: 100, pixel array; 200, column-level current source load circuit; 300, analog-to-digital conversion module; 310, ramp voltage generator; 320, comparator; 330, counter; 331, clock delay unit; 332, phase selection unit; 340, buffer; 350, clock tree unit. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] See also Figure 1 and Figure 2 As shown, Figure 1 The image processing system provided by the present invention can solve the following problems: Figure 1 The vertical block problem shown in the figure. The image processing system provided by the present invention is applied to a CMOS image sensor. The image sensor includes a pixel array 100 and an image processing system. The pixel array 100 includes a plurality of pixel units, and the plurality of pixel units are arranged in an array in rows and columns. In this embodiment, the pixel array 100 includes a plurality of pixel column circuits and a plurality of pixel row circuits. Figure 2As shown, in the pixel array 100, the position of the pixel unit pixel in the pixel array 100 can be represented in the form of array coordinates. When reading out the electrical signal of the pixel unit pixel, the row to be read out is selected by the row scanning circuit, and then the pixel signal in the selected row is read out by the column reading circuit. In this embodiment, the signals of multiple pixel units located in different columns and the same row are read out at the same time, and analog-to-digital conversion is performed at the same time. In this embodiment, Figure 2 The column readout circuit is not shown. In this embodiment, the image processing system includes a column-level current source load circuit 200 and an analog-to-digital conversion module 300. The column-level current source load circuit 200 is electrically connected to the column readout circuit, and the mode conversion module 300 is electrically connected to the column-level current source load circuit 200, so as to receive the pixel signal of the column circuit 101, convert the input pixel signal, and output the pixel value.

[0037] See also Figure 2 As shown, in one embodiment of the present invention, the input end of the column-level current source load circuit 200 is electrically connected to the pixel column circuit of the pixel array 100, and the output end of the column-level current source load circuit 200 is electrically connected to the analog-to-digital conversion module 300. The number of column-level current source load circuits 200 is consistent with the number of pixel column circuits, and the corresponding column numbers are connected one by one. In a CMOS image sensor, after the pixel signal is exposed in the pixel array 100, the photoelectrons accumulated in the pixel unit pixel are converted into a voltage signal inside the pixel array 100. The internal circuit of the pixel array 100 and the column-level current source load circuit 200 form a signal amplification circuit, which is electrically connected to the column-level current source load circuit 200, receives the voltage signal, and outputs the amplified voltage signal as a pixel signal. The pixel signal is input into the analog-to-digital conversion module 300, and the pixel signal is converted into a pixel value after the analog-to-digital conversion. After being processed by the image processing system, the digital image data corresponding to all the pixel signals of the pixel array 100 is obtained.

[0038] See also Figure 2 As shown, in one embodiment of the present invention, the analog-to-digital conversion module 300 includes a ramp voltage generator 310, a comparator 320, a counter 330, a buffer 340 and a clock tree unit 350. The comparator 320 has a first input terminal and a second input terminal, and the first input terminal of the comparator 320 is electrically connected to the ramp voltage generator 310 to receive the ramp voltage V RAMP The second input terminal of the comparator 320 is electrically connected to the pixel column circuit to receive the pixel voltage V PIXThe output end of the comparator 320 is electrically connected to the counter 330. The counter 330 performs real-time counting according to the level flipping of the comparator 320. In this embodiment, the start of the counter 330 is controlled by the level signal outside the array, and the stop of the counter 330 is controlled by the output level of the comparator 320. The counter 330 is electrically connected to the clock tree unit 350, and the count clock input is electrically connected to the clock tree unit 350 through the buffer 340. The clock tree unit 350 is electrically connected to the counter 330, and the count clock signal is input to each column counter 330 respectively. The process start signal is transmitted to multiple counters 330. Due to the load problem, the process start signal received by each counter 330 has a phase difference. The count start signal is used to start the timer 330. When the process start signal flips to a high level, the count start signal flips to a high level, and the counter 330 starts. The count clock signal is initially a fixed pulse signal. After the delay processing and phase selection processing of the present invention, the count clock signal is set to a clock signal of a fixed initial level type.

[0039] See also Figures 2 to 4 As shown, in one embodiment of the present invention, the non-inverting input terminals of the plurality of comparators 320 are coupled to the same ramp voltage generator 310 to receive the ramp voltage V RAMP The inverting input terminal of the comparator 320 is coupled to the output terminal of the column-level current source load circuit 200 of the corresponding column to receive the pixel voltage V PIX In this embodiment, if Figure 4 As shown, the ramp voltage generator 310 outputs a ramp voltage V RAMP .like Figure 3 As shown, the output level of the comparator 320 is CMP_OUT. The output end of the comparator 320 is electrically connected to the counter 330 through a NOT gate circuit and an AND gate circuit in sequence. Specifically, the first input end of the AND gate circuit receives the inverted output level of the comparator 320, and the second input end of the AND gate circuit receives the process start signal CNT_CTL. The output end of the AND gate circuit outputs the count start signal CNT_EN. In this embodiment, the counter 330 is electrically connected to the output end of the AND gate circuit, and the counter 330 receives the initial count clock signal CNT_CLK. The output level of the counter 330 is CNT_OUT. In this embodiment, the initial count clock signal CNT_CLK is a single pulse signal, and the present invention does not limit the interval time and duration of the single pulse signal. During the counting period of the counter 330, the counter 330 counts the number of pulses of the initial count clock signal CNT_CLK. In this embodiment, when the ramp voltage V RAMPWhen the comparator 320 output level CMP_OUT is reversed, the counter 330 stops counting. In this embodiment, the count value of the counter 330 can be represented as the pixel value after the pixel signal is converted. In other embodiments of the present invention, the count value can also be mathematically processed to convert it into a pixel value that meets the pixel representation standard. When the output level of the comparator 320 flips CMP_OUT, the counter 330 stops counting.

[0040] See also Figures 2 to 4 As shown, in one embodiment of the present invention, before node a, the ramp voltage generator 310 is reset to make the ramp voltage V RAMP The value of the ramp voltage V RA MP The preset value of can be, for example, twice the standard pixel voltage. For example, if the pixel voltage is about 1V, then the ramp voltage V RAMP It can be set to 2V. The present invention does not limit the ramp voltage V RAMP It should be noted that the pixel voltage V PIX The value is a black box value. Before the test output, the pixel voltage V cannot be known. PIX The specific value of the pixel voltage V PIX At node a, the ramp voltage V RAMP , thereby resetting the comparator 320. Wherein, the ramp voltage V RAMP The raising range of V is, for example, 100mV to 200mV. After the raising, the ramp voltage V RAMP Maintain for a period of time, the present invention does not limit the ramp voltage V RAMP The specific duration of the rise can be adjusted by the designer according to the needs of the device. At node b, the quantization process of analog-to-digital conversion begins.

[0041] See also Figures 2 to 4 As shown, in one embodiment of the present invention, after node b, the ramp voltage V RAMP The value of the ramp voltage V RAMP The test standard value is restored. At this time, the process start signal CNT_CTL and the count start signal CNT_EN are flipped, and specifically flipped from a low level to a high level. At this time, the counter 330 starts to count the number of pulses of the initial count clock signal CNT_CLK. It should be noted that the test standard value is the ramp voltage V RAMP The initial value of the ramp voltage V RAMP The test standard value is not specifically limited. RAMP The value of continues to decrease at the set rate until the ramp voltage V RAMP and pixel voltage V PIX=Equal, at this time the output level CMP_OUT of the comparator 320 flips, and specifically flips from a low level to a high level. At the d node, the process start signal CNT_CTL also flips, and specifically flips from a high level to a low level. At this time, the counter 330 stops counting. It should be noted that the specific position of the d node is unknown and is only used to identify the ramp voltage V at this time. RAMP and pixel voltage V PIX When the counter 330 stops counting, the output level CNT_OUT of the counter 330 is maintained at the current count value and does not change. In this embodiment, a latch can be set to latch and output the CNT_OUT after the count stops as the final count value. In this embodiment, when the output of the comparator 320 flips to a high level, the ramp voltage V RAMP The value of the ramp voltage V RAMP The value of is reduced to the preset value, that is, the e node, at this time the timing signal CNT_CTL flips to a low level, and the analog-to-digital conversion process ends.

[0042] See also Figure 2 , Figure 5 and Figure 6 As shown, in one embodiment of the present invention, the principle of the counter 330 is as follows Figure 5 As shown, the starting level of the count is a low level. When the count start signal CNT_EN is at a high level, the counter 330 is started and the counter 330 starts counting. During the counting period of the counter 330, each time the count pulse level flips once, the counter 330 counts once. In this embodiment, Figure 5 The counter 330 of 4 bits is shown. The counter 330 includes a plurality of D flip-flops, wherein the first latch triggers counting in a level-maintaining state, and latches other than the first latch trigger counting in a level-flipping state. Specifically, the first latch triggers counting when the process start signal CNT_CTL is at a high level. Figure 6 As shown, the process start signal CNT_CTL is set to a high level, and the count start signal CNT_EN is flipped to a high level, and the counter 330 enters the counting state. It should be noted that the present invention does not limit the high and low levels of the initial count clock signal CNT_CLK. Figure 6 As shown in FIG. 1 , when the count start signal CNT_EN flips to a high level, the initial count clock signal CNT_CLK is also at a high level, and the counter 330 counts once. Then, during the counting period of the counter 330, the counter 330 counts once at both the rising and falling edges of the initial count clock signal CNT_CLK. Until the output level CMP_OUT of the comparator 320 flips, triggering the count start signal CNT_EN to flip from a high level to a low level, the counting ends. Figure 6As shown, the count value is 7.

[0043] See also Figure 1 , Figure 6 and Figure 7 As shown, it should be noted that the process start signal CNT_CTL is sent to each pixel column circuit. Under ideal conditions, the time when each pixel column circuit receives the process start signal CNT_CTL is consistent. However, in actual use, due to the interference of the circuit load, there is a phase difference in the rising edge time of each pixel column circuit receiving the process start signal CNT_CTL. Take pixel column circuit 0 and pixel column circuit 1 as an example to illustrate the phase difference of the process start signal CNT_CTL. When the effective level of the process start signal CNT_CTL_0 is 1, the effective level of the process start signal CNT_CTL_1 is 0. After an interval of error time, the effective level of the process start signal CNT_CTL_1 is 1. When the effective level of the process start signal CNT_CTL_0 is 1, the counting start signal CNT_EN_0 flips to a high level. At this time, the counter 330 connected to the pixel column circuit 0 is started. As shown Figure 7 As shown, when the counter 330 connected to the pixel column circuit 0 is started, the initial counting clock signal CNT_CLK is at a high level, and the counter 330 is counted directly at this time. The count is accumulated when the initial counting clock signal CNT_CLK is subsequently flipped to a level. When the effective level of the process start signal CNT_CTL_1 is 1, the counting start signal CNT_EN_1 flips to a high level, and the counter 330 connected to the pixel column circuit 1 is started. When the counter 330 connected to the pixel column circuit 1 is started, the initial counting clock signal CNT_CLK is at a low level, and the counter 330 does not count until the initial counting clock signal CNT_CLK is at a high level, and then it starts counting. And so on. Figure 7 As shown, until the output level CMP_OUT of the comparator 320 flips, triggering the count start signal CNT_EN_0 and the count start signal CNT_EN_1 to flip from high level to low level, the counting ends at this time. Therefore, due to the phase difference between the process start signal CNT_CTL_0 and the process start signal CNT_CTL_1, the count value D0 of the counter 330 connected to the pixel column circuit 0 is 7, and the count value D1 of the counter 330 connected to the pixel column circuit 1 is 5. Therefore, there are pixel differences between adjacent pixel column circuits or pixel column circuits that are close to each other, which is reflected as Figure 1 The vertical block imaging problem shown.

[0044] See also Figure 2 , Figure 4 , Figures 7 to 9As shown, it should be noted that in the counting step of the pixel column circuit, the value of the first count is used as the count value, and such calculation may result in a large error due to various interference factors. In one embodiment of the present invention, two counts are performed respectively. In the first count, that is, the pixel reset signal counting stage, as shown in FIG. Figure 8 During the R counting period shown in FIG. 1 , the pixel reset signal is converted into analog-to-digital and quantized to obtain the first count value. Then, during the second counting period, i.e., the pixel signal counting period, the pixel signal after exposure is read out and the pixel signal is converted into analog-to-digital. The second counting period is as follows: Figure 8 During the S counting period shown in FIG. 1 , a quantized second count value is obtained. In this embodiment, the quantized pixel value of the pixel signal is the difference between the first count value and the second count value. Fig. 9 As shown, the difference calculation method still cannot solve the vertical block problem in some cases. For example, during R counting, the initial count value is 10, which is 1010 in binary, and the lowest bit of the initial count value is 0. When counting starts, the first count will only be performed when the initial count clock signal CNT_CLK is high. Since the final count value of the pixel reset signal is an odd number, that is, the lowest bit of the binary is 1, the input clock must be low when the count is enabled to count for the first time. Therefore, the count values ​​of the pixel reset signal are not equal. Fig. 9 As shown, the count value D0 of the pixel column circuit 0 drops to 3, and the count value D1 of the pixel column circuit 1 drops to 5. Fig. 9 Since the rising edge of the pixel signal count starts at the high level of the count clock signal, the count value of the pixel signal is consistent. Figure 8 As shown, the count value of pixel column circuit 0 starts from 4, and the count value is 11. The count value of pixel column circuit 1 starts from 6, and the count value is 13. Therefore, after the difference calculation is performed, the counting error still exists.

[0045] See also Figure 2 and Figure 4 , Fig.10 and Fig.11As shown, in one embodiment of the present invention, the analog-to-digital conversion module 300 also includes a clock delay unit 331 and a phase selection unit 332. In this embodiment, the clock delay unit 331 has a first input terminal and a second input terminal, a first output terminal and a second output terminal. The first input terminal of the clock delay unit 331 is electrically connected to the initial counting clock signal CNT_CLK, and the second input terminal of the clock delay unit 331 is electrically connected to the process start signal CNT_CTL. The first output terminal of the clock delay unit 331 outputs the first counting signal CNT_CLK_DB, and the second output terminal of the clock delay unit 331 outputs the second counting signal CNT_CLK_DN. In this embodiment, the first counting signal CNT_CLK_DB and the second counting signal CNT_CLK_DN ​​are inverted signals. As Fig.11 As shown, the first counting signal CNT_CLK_DB flips from a low level to a high level when flipping, and the second counting signal CNT_CLK_DN ​​flips from a high level to a low level when flipping. In this embodiment, according to the type of count value required to be output by the counter 330, the phase selection unit 332 selects the first counting signal CNT_CLK_DB or the second counting signal CNT_CLK_DN ​​as the standard counting clock signal CNT_CLK_D. In this embodiment, at the count value D of the counter 330, <0> When the initial value is required to be an even number, CNTCLK_DB is selected as the standard counting clock signal CNT_CLK_D, and the count value D of the counter 330 is <0> When the initial value is an odd number, select CNTCLK_DN ​​as the standard counting clock signal CNT_CLK_D. Fig.11As shown, although there are differences in the rising edges of the process start signal CNT_CTL received by different counters 330, the actual counting of the counter 330 starts only after the standard counting clock signal CNT_CLK_D jumps, so the counting values ​​of multiple counters 330 can be kept consistent. For example, in the pixel reset signal counting stage, the counting value D0<3:0> of the counter 330 corresponding to the pixel column circuit 0 and the counting value D1<3:0> of the counter 330 corresponding to the pixel column circuit 1 are both 10 in the initial value, and the output count value is 5. Since the initial value is an even number, the lowest bit of the count is 0. In the pixel reset signal counting stage, the phase selection unit 332 selects CNTCLK_DB as the standard counting clock signal CNT_CLK_D. In the pixel signal counting stage, for the count value D0<3:0> of the counter 330 corresponding to the pixel column circuit 0, and the count value D1<3:0> of the counter 330 corresponding to the pixel column circuit 1, since the initial values ​​are both 5, which is an odd number, the lowest bit of the count is 1, so CNTCLK_DN ​​is selected as the standard counting clock signal CNT_CLK_D. Similarly, the counting of the pixel signal starts at the jump start of the standard counting clock signal CNT_CLK_D. Therefore, the count values ​​of the pixel reset signal and the pixel signal are consistent. Therefore, the final count values ​​output by multiple pixel column circuits are consistent, and there will be no vertical block phenomenon on the image.

[0046] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image processing system, the image processing system being electrically connected to a pixel array, characterized in that: The image processing system comprises: A plurality of comparators, electrically connected to a pixel column circuit of the pixel array, wherein when a pixel voltage of the pixel column circuit is equal to a preset voltage, an output level of the comparator is flipped; a clock tree unit, the clock tree unit outputting a counting clock signal; and A plurality of counters are electrically connected to the comparator, and the counters receive a counting start signal. Under the delayed triggering of the counting start signal, the counters count the pulses of the counting clock signal. When the output level of the comparator flips, the counters stop counting and output the counting value as the analog-to-digital conversion quantization value of the pixel voltage signal.

2. An image processing system according to claim 1, characterized in that: The image processing system includes a clock delay unit, which has a first input end and a second input end. The first input end receives the counting clock signal, and the second input end receives counting start signals of multiple counters. The clock delay unit outputs a first counting signal and a second counting signal, wherein a level flip time of the first counting signal is later than a level flip time of the counting start signal.

3. An image processing system according to claim 2, characterized in that: The image processing system includes a phase selection unit, which is electrically connected to the clock delay unit and receives the first counting signal and the second counting signal. The output end of the phase selection unit is electrically connected to the counter and outputs the counting clock signal to the counter. The counter counts the pulses of the counting clock signal.

4. An image processing system according to claim 3, characterized in that: The counter receives a process start signal. When the process start signal is at a high level, the counter starts and counts the rising edge, the falling edge and the initial high level signal of the counting clock signal.

5. An image processing system according to claim 4, characterized in that: The plurality of count start signals are respectively output to the counters of different pixel column circuits. At the rising edge of the process start signal, the count start signal flips to a high level, allowing the process start signals in the plurality of pixel column circuits to have a phase difference.

6. An image processing system according to claim 2, characterized in that: The second counting signal and the first counting signal are inverted signals to each other, wherein the level of the first counting signal is high after being flipped, and the level of the second counting signal is low after being flipped, wherein when the initial value of the counter is an even number, the counting clock signal is the first counting signal, and when the initial value of the counter is an odd number, the counting clock signal is the second counting signal.

7. An image processing system according to claim 4, characterized in that: The counter has a pixel reset signal counting stage and a pixel voltage signal counting stage. In the pixel reset signal counting stage, the counter obtains a first count value, which is an analog-to-digital conversion quantization value of the pixel reset signal. In the pixel voltage signal counting stage, the counter obtains a second count value, which is a difference between the first count value and the second count value.

8. An image processing system according to claim 7, characterized in that: Between the pixel reset signal counting stage and the pixel voltage signal counting stage, when a plurality of the process start signals are at a low level, the counting clock signal is reset and maintained at a high level until the counter enters the pixel signal counting stage.

9. An image processing system according to claim 1, characterized in that: The preset voltage is a ramp voltage, the first input end of the comparator receives the pixel voltage signal output by the pixel column circuit, the second input end of the comparator receives the ramp voltage signal, and when the voltage value of the ramp voltage signal drops to be equal to the voltage value of the pixel voltage signal, the output level of the comparator flips.

10. An image sensor, characterized in that: include: a pixel array, the pixel array comprising a plurality of pixel column circuits; as well as An image processing system as described in any one of claims 1 to 9, wherein the image processing system is electrically connected to the pixel column circuit, the image processing system receives a pixel voltage signal from the pixel column circuit, and obtains an analog-to-digital conversion quantization value of the pixel voltage signal.

Images