Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which can form an isolation resistor structure in a non-device area of the semiconductor device under the condition of not increasing extra mask cost. The isolation resistor structure has an isolation effect and can improve the breakdown voltage between the first trench structure and the second trench structure for isolating different device regions; the resistance value required by the device region can be provided, the area of the device region is not occupied, and the deployment of devices in the device region is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Resistors in existing semiconductor devices often require additional masks during the manufacturing process. When a resistor with a larger resistance is required in a semiconductor device, the area required for the manufactured resistor is often very large, and it also accounts for a large proportion of the device area, thus affecting the deployment of other devices in the device area.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can form an isolation resistor structure having both an isolation effect and a resistor function in a non-device area of ​​the semiconductor device without increasing additional mask costs, and does not occupy the area of ​​the device area.

[0005] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0006] A semiconductor device, comprising:

[0007] A semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer;

[0008] An isolation structure is disposed in the semiconductor body, the isolation structure divides the semiconductor body into a plurality of device regions, and the isolation structure includes a first trench and a second trench;

[0009] The first trench extends from the top surface of the epitaxial layer into the buried layer, a first trench structure is disposed in the first trench, and the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer;

[0010] The second trench extends from the top surface of the epitaxial layer into the substrate, a second trench structure is disposed in the second trench, and the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer;

[0011] an isolation resistor structure, disposed in the semiconductor body and between the first trench and the second trench, the isolation resistor structure being used at least to provide a required resistance value for the device region, and the isolation resistor structure being configured to isolate the first trench structure from the second trench structure, and the isolation resistor structure comprising a third trench;

[0012] The third trench extends from the top surface of the epitaxial layer into the substrate, and the depth of the third trench is less than the depth of the second trench. A third trench resistor structure is disposed in the third trench.

[0013] In one or more embodiments of the present invention, the third trench resistor structure includes:

[0014] A liner, disposed on an inner wall of the third groove;

[0015] A dielectric layer is disposed in the third trench and located on the surface of the liner, wherein the dielectric layer and the liner are partially etched at the top surface of the epitaxial layer to form a first opening;

[0016] A first conductive material is disposed in the third trench and at least fills the first opening.

[0017] In one or more embodiments of the present invention, the first conductive material includes polysilicon having a first doping type.

[0018] In one or more embodiments of the present invention, the resistance of the isolation resistor structure is adjusted by changing the doping concentration of the first conductive material in the first opening.

[0019] In one or more embodiments of the present invention, the first conductive material is counter-doped with a different doping type, or heavily doped with the same doping type, so as to change the doping concentration of the first conductive material.

[0020] In one or more embodiments of the present invention, the third trench resistor structure is divided into a connection area and a functional area;

[0021] The connection area is used to form a metal connection electrically connected to the first conductive material;

[0022] The first conductive material in the functional area is counter-doped with a different doping type, or heavily doped with the same doping type, so as to change the doping concentration of the first conductive material.

[0023] In one or more embodiments of the present invention, the first conductive material in the connection region is counter-doped with a different doping type to change the connection resistance between the metal connection and the first conductive material.

[0024] In one or more embodiments of the present invention, the width of the third groove is in the range of 0.6 μm-1.3 μm.

[0025] In one or more embodiments of the present invention, the semiconductor device further includes a shallow trench isolation structure, which is formed on the top surface of the epitaxial layer and extends into the epitaxial layer, and the shallow trench isolation structure is at least partially overlapped with the third trench resistance structure.

[0026] In one or more embodiments of the present invention, the resistance value of the isolation resistor structure is adjusted by adjusting the width of the overlapping region between the third trench resistor structure and the shallow trench isolation structure.

[0027] In one or more embodiments of the present invention, a width of an overlapping region between the shallow trench isolation structure and the third trench resistor structure is in a range of 0 μm-0.4 μm.

[0028] A method for manufacturing a semiconductor device, comprising:

[0029] Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer;

[0030] forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer;

[0031] forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer;

[0032] forming a second trench and a third trench in the semiconductor body, wherein the second trench is disposed around the first trench, the second trench extends from the top surface of the epitaxial layer into the substrate and has a first depth, and the third trench is located between the first trench and the second trench, the third trench extends from the top surface of the epitaxial layer into the substrate and has a second depth less than the first depth;

[0033] While forming the second trench structure in the second trench, a third trench resistor structure is formed in the third trench.

[0034] In one or more embodiments of the present invention, the manufacturing method further includes:

[0035] A shallow trench isolation structure is formed in the semiconductor body, wherein the shallow trench isolation structure exposes a portion of the first trench structure, a portion of the second trench structure, and a portion of the third trench resistor structure.

[0036] In one or more embodiments of the present invention, the resistance value of the isolation resistor structure is adjusted by adjusting the width of the overlapping region between the shallow trench isolation structure and the third trench resistor structure, or adjusting the width of the third trench.

[0037] In one or more embodiments of the present invention, while forming the second trench structure in the second trench, forming the third trench resistor structure in the third trench, comprises:

[0038] forming a liner on inner walls of the second groove and the third groove;

[0039] forming a dielectric layer on the surface of the liner in the second trench and the third trench;

[0040] Etching and removing the liner and the dielectric layer on the bottom wall of the second trench, and forming a first opening at least on the top surface of the third trench;

[0041] A first conductive material having a first doping type is deposited so that the first conductive material at least fills the second trench and the first opening.

[0042] In one or more embodiments of the present invention, the resistance of the isolation resistor structure is adjusted by counter-doping the first conductive material in the first opening with a different doping type or heavily doping the first conductive material in the first opening to change the doping concentration of the first conductive material in the first opening.

[0043] Compared with the prior art, the semiconductor device and the manufacturing method thereof of the present invention can form an isolation resistor structure in a non-device area of ​​the semiconductor device without increasing the cost of additional masks. The isolation resistor structure has both an isolation effect - it can increase the breakdown voltage between the first trench structure and the second trench structure that isolate different device areas; and a resistance function - it can provide the required resistance value of the device area; and does not occupy the area of ​​the device area.

[0044] The semiconductor device and its manufacturing method of the present invention can adjust the resistance of the isolation resistor structure by changing the width of the third trench and the doping concentration of the first conductive material in the third trench, and can also adjust the resistance of the isolation resistor structure by adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 is a schematic cross-sectional view of a semiconductor device in one embodiment of the present invention;

[0047] Figure 2 is a schematic top view of a semiconductor device in one embodiment of the present invention;

[0048] Figure 3 This is an experimental data diagram of the resistance value of the isolation resistor structure in the semiconductor device in one embodiment of the present invention due to different doping;

[0049] Figure 4 FIG. 1 is an experimental data diagram showing the resistance of the isolation resistor structure in the semiconductor device according to an embodiment of the present invention due to different third trench widths.

[0050] Figure 5 is a flow chart of a method for manufacturing a semiconductor device in one embodiment of the present invention;

[0051] Figure 6a-6m FIG. 1 is a process diagram of a method for manufacturing a semiconductor device in one embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] As mentioned in the background technology, resistors in existing semiconductor devices often require additional masks during the manufacturing process. When a resistor with a larger resistance is required in a semiconductor device, the area required for the manufactured resistor is often very large and accounts for a large proportion of the device area, thus affecting the deployment of other devices in the device area.

[0054] Based on this, the present invention provides a semiconductor device and a method for manufacturing the same, which can form an isolation resistor structure in a non-device area of ​​a semiconductor device without increasing additional mask costs. The isolation resistor structure has both an isolation effect - it can increase the breakdown voltage between a first trench structure and a second trench structure that isolate different device areas; and a resistance function - it can provide the required resistance value of the device area, and does not occupy the area of ​​the device area, which is conducive to the deployment of devices in the device area.

[0055] like Figure 1As shown, a semiconductor device in an embodiment of the present invention includes a semiconductor body 10, an isolation structure 20 and an isolation resistor structure 30 arranged in the semiconductor body 10, and a shallow trench isolation structure 40 arranged on the top surface of the semiconductor body 10 and partially extending into the semiconductor body 10.

[0056] The semiconductor body 10 includes a substrate 11, a buried layer 12 disposed on the substrate 11, and an epitaxial layer 13 disposed on the buried layer 12. The substrate 11 has a first doping type, the buried layer 12 has a second doping type opposite to the first doping type, and the epitaxial layer 13 has the first doping type. The thickness of the epitaxial layer 13 is 12 μm-15 μm, preferably 13 μm.

[0057] Exemplarily, the first doping type may be p-type, and the second doping type may be n-type. Alternatively, the first doping type may be n-type, and the second doping type may be p-type. The p-type dopant may include boron (B), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.

[0058] The isolation structure 20 is disposed in the semiconductor body 10 , and the isolation structure 20 divides the semiconductor body 10 into a plurality of device regions A. The isolation structure 20 includes a first trench 21 and a second trench 22 .

[0059] The first trench 21 is preferably arranged in an annular shape and extends from the top surface of the epitaxial layer 13 to the buried layer 12 . A first trench structure is arranged in the first trench 21 and is configured to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13 .

[0060] The first trench structure includes a second conductive material 211 electrically connected to the buried layer 12, and a barrier layer 212 formed between the second conductive material 211 and the sidewall of the first trench 21. The barrier layer 212 includes an oxide layer and a nitride layer. A metal connection (not shown) can be formed on the second conductive material 211 of the first trench structure to facilitate voltage application. The second conductive material 211 includes polysilicon having a second doping type.

[0061] The second trench 22 is also arranged in an annular shape and is located at the periphery of the first trench 21. The second trench 22 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a first depth D1. A second trench structure is arranged in the second trench 22, and the second trench structure is configured to electrically connect the substrate 11 to the top surface of the epitaxial layer 13.

[0062] The second trench structure includes a first conductive material 51 electrically connected to the substrate 11. The first conductive material 51 includes polysilicon having a first doping type. A liner 52 and a dielectric layer 53 are formed between the first conductive material 51 and the sidewall of the second trench 22. The liner 52 is preferably an oxide layer, and the dielectric layer 53 is preferably an oxide layer or a nitride layer. A metal connection (not shown) can also be formed on the first conductive material 51 of the second trench structure to facilitate the application of voltage.

[0063] When different voltages are applied to the metal connection of the first trench structure and the metal connection of the second trench structure at the same time, the first trench structure and the second trench structure work together to achieve isolation of different device regions A in the semiconductor device.

[0064] The isolation resistor structure 30 is disposed in the semiconductor body 10 and between the first trench 21 and the second trench 22 , and is used to provide a required resistance for the device region A at least, and is configured to isolate the first trench structure from the second trench structure. The isolation resistor structure 30 includes a third trench 31 .

[0065] The third trench 31 is arranged in an annular shape and is arranged in a concentric ring or concentric ring shape with the first trench 21 and the second trench 22. The width of the third trench 31 ranges from 0.6 μm to 1.3 μm. The third trench 31 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a second depth D2. The second depth D2 of the third trench 31 is less than the first depth D1 of the second trench 22. A third trench resistor structure is arranged in the third trench 31.

[0066] The third trench resistor structure includes a liner 52, a dielectric layer 53 and a first conductive material 51. The liner 52 is disposed on the inner wall of the third trench 31. The dielectric layer 53 is disposed in the third trench 31 and is located on the surface of the liner 52. The dielectric layer 53 and the liner 52 are partially etched at the top surface of the epitaxial layer 13 to form a first opening 311. The first conductive material 51 is disposed in the third trench 31 and at least fills the first opening 311. A metal connection (not shown) can also be formed on the first conductive material 51 of the third trench resistor structure to facilitate the application of voltage.

[0067] In the above technical solution, the resistance of the isolation resistor structure 30 can be adjusted by changing the doping concentration of the first conductive material 51 in the first opening 311. Exemplarily, the first conductive material 51 in the first opening 311 is counter-doped with different doping types, such as NWELL, NLDD, and NPLUS, or heavily doped with the same doping type, such as PPLUS, to change the doping concentration of the first conductive material 51.

[0068] For further reference, Figure 2As shown, the third trench resistor structure 30 is divided into a connection area 32 and a functional area 33. The connection area 32 is used to form a metal connection (not shown) electrically connected to the first conductive material 51. The functional area 33 is used to act as a resistor.

[0069] In one embodiment, only the first conductive material 51 in the functional area 33 may be counter-doped with different doping types, or heavily doped with the same doping type, to change the doping concentration of the first conductive material 51 in the area, thereby changing the resistance of the isolation resistor structure 30. The first conductive material 51 in the connection area 32 may be doped with PPLUS to facilitate better electrical connection with the subsequently formed metal connection, reduce the connection resistance between the two, and improve the connection stability.

[0070] In another embodiment, the first conductive material 51 in the connection region 32 may be counter-doped with different doping types to increase the connection resistance between the subsequently formed metal connection and the first conductive material 51 in the connection region 32 , thereby increasing the overall resistance of the isolation resistor structure 30 .

[0071] refer to Figure 3 As shown, Figure 3 As shown by the experimental study, for the isolation resistor structure 30, the resistance value changes when the metal connection is formed on the first conductive material 51 with different doping types and the first conductive material 51 with the same doping type. In one embodiment, the width of the third trench 31 (dti2 in the figure represents the third trench in the text) is uniformly 1.1μm, the extension length of the third trench 31 is 100μm (the extension length is the length of the functional area in the text), P+ represents PPLUS doping (the first conductive material itself is P doped), N+ represents NPLUS anti-doping, the left frame of the figure represents the metal connection formed on the first conductive material 51 doped with PPLUS, and the right frame of the figure represents the metal connection formed on the first conductive material 51 doped with NPLUS.

[0072] from Figure 3 It can be shown that when the metal connection is formed on the N+ anti-doped first conductive material 51 , the resistance of the isolation resistor structure 30 increases by about 1.6 times compared to when the metal connection is formed on the P+ doped first conductive material 51 .

[0073] refer to Figure 1 As shown, the shallow trench isolation structure 40 is formed on the top surface of the epitaxial layer 13 and extends into the epitaxial layer 13 . The shallow trench isolation structure 40 at least partially overlaps with the third trench resistor structure.

[0074] In the above technical solution, the resistance of the isolation resistor structure 30 can also be adjusted by adjusting the width of the third trench 31 or adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure 40. Preferably, the width of the overlapping area between the shallow trench isolation structure 40 and the third trench resistor structure is in the range of 0 μm-0.4 μm.

[0075] refer to Figure 4 As shown, Figure 4 The experimental study shows that for the isolation resistor structure 30, the resistance value changes corresponding to different widths of the third groove 31. In one embodiment, the width of the third groove 31 is selected from 1.0μm and 1.1μm, and the extension length is uniformly 50μm (the extension length is the length of the functional area in the text). The left frame of the figure represents that the width of the third groove 31 is selected from 1.0μm, and the right frame of the figure represents that the width of the third groove 31 is selected from 1.1μm.

[0076] from Figure 4 It can be seen from the figure that when the width of the third trench 31 is set to 1.0 μm, the resistance of the isolation resistor structure 30 increases by about 36% compared with when the width of the third trench 31 is set to 1.1 μm.

[0077] refer to Figure 5 As shown, the present invention also provides a method for manufacturing the semiconductor device, comprising:

[0078] S1, providing a semiconductor body, wherein the semiconductor body comprises a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer.

[0079] S2, forming a first trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer to the buried layer.

[0080] S3 , forming a first trench structure in the first trench, wherein the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0081] S4, forming a second trench and a third trench in the semiconductor body, the second trench is arranged around the first trench, the second trench extends from the top surface of the epitaxial layer into the substrate and has a first depth, the third trench is located between the first trench and the second trench, the third trench extends from the top surface of the epitaxial layer into the substrate and has a second depth less than the first depth.

[0082] S5 , while forming the second trench structure in the second trench, form a third trench resistor structure in the third trench.

[0083] S6, forming a shallow trench isolation structure in the semiconductor body, wherein the shallow trench isolation structure exposes a portion of the first trench structure, a portion of the second trench structure, and a portion of the third trench resistor structure.

[0084] Figure 6a to Figure 6m is a schematic diagram of the steps of a method for manufacturing a semiconductor device in an embodiment of the present invention, Figure 6a to Figure 6m The process shown can be used to make Figure 1 The semiconductor device shown in the above Figure 1 The description of the semiconductor device may be incorporated herein.

[0085] refer to Figure 6a As shown, a semiconductor body 10 is provided. The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having the first doping type disposed on the buried layer 12. The thickness of the epitaxial layer 13 is 12μm-15μm. Among them, the second doping type is opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. The p-type dopant may include boron (B), aluminum (Al), indium (In) or a combination thereof, while the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. The buried layer 12 may have a blanket structure, which has substantially the same horizontal extension as the substrate 11 and is laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure.

[0086] A hard mask layer 15 is formed on the top surface of the epitaxial layer 13. The hard mask layer 15 may include a first oxide layer 151 with a thickness of 100A to 200A, a first nitride layer 152 with a thickness of 1000A to 2000A, and a TEOS layer 153 with a thickness of 2000A to 3000A. The hard mask layer 15 may also include only a first oxide layer 151 with a thickness of 100A to 200A and a first nitride layer 152 with a thickness of 1000A to 2000A. In some embodiments, the substrate 11, the buried layer 12, and the epitaxial layer 13 are formed of silicon material, the first oxide layer 151 is formed of silicon dioxide, the first nitride layer 152 is formed of silicon nitride, and the TEOS layer 153 is a silicon oxide layer.

[0087] like Figure 6b As shown, the hard mask layer 15 and the semiconductor body 10 can be etched once using a soft mask layer to form a first trench 21 in the hard mask layer 15 and the semiconductor body 10 that penetrates the hard mask layer 15 and goes deep into the semiconductor body 10. The first trench 21 extends from the top surface of the epitaxial layer 13 into the buried layer 12. In some embodiments, the soft mask layer can be a photoresist. After the first trench 21 is etched, the soft mask layer is stripped.

[0088] like Figure 6cAs shown, a barrier layer 212 is grown on the sidewall of the first trench 21. The barrier layer 212 includes an oxide layer and a nitride layer. The thickness of the oxide layer is about 100A to 200A. The thickness of the nitride layer is 100A to 300A.

[0089] It is understandable that when the barrier layer 212 is grown, it will be grown on the sidewalls and bottom wall of the first trench 21, so the barrier layer 212 on the bottom wall of the first trench 21 can be removed by subsequent dry etching to expose the buried layer 12. The etching process will form a V-shape at the top of the first trench 21, which has a better effect on the subsequent filling of the second conductive material 211. The top TEOS layer 153 can be used as an etching stop layer or a protective layer.

[0090] Optionally, before growing the barrier layer 212 on the sidewalls and bottom wall of the first trench 21, a sacrificial oxide layer may be grown on the sidewalls and bottom wall of the first trench 21, and then removed by wet stripping. By stripping the sacrificial oxide layer, damage on the sidewalls and bottom wall generated during the etching process can be removed, the sidewalls of the first trench 21 can be smoothed, and the opening width of the first trench 21 on the top surface of the epitaxial layer 13 can be further widened by stripping the sacrificial oxide layer, so as to facilitate subsequent processes.

[0091] like Figure 6d As shown, a second conductive material 211 having a second doping type is deposited so that the second conductive material 211 fills the first trench 21. The second conductive material 211 is in full contact with the buried layer 12 and is electrically connected. The second conductive material 211 is preferably polysilicon. The second conductive material 211 and the barrier layer 212 together form a first trench structure.

[0092] like Figure 6e As shown, the excess second conductive material 211 and a portion of the TEOS layer 153 can be removed by a chemical mechanical polishing (CMP) process, and the TEOS layer 153 serves as a stop layer for the chemical mechanical polishing (CMP). Subsequently, an etch-back process using anisotropic plasma dry etching is used to keep the top surface of the second conductive material 211 at the same level as the top surface of the first nitride layer 152.

[0093] like Figure 6f As shown, the TEOS layer 153 is removed. Since part of the second conductive material 211 may also be deposited on the substrate 11 of the semiconductor body 10 when the second conductive material 211 is deposited, the second conductive material 211 on the substrate 11 of the semiconductor body 10 is removed while the second conductive material 211 on the TEOS layer 153 is removed, so as to obtain better wafer warpage and less stress.

[0094] like Figure 6gAs shown, a second nitride layer 16 is deposited on the top surface of the first nitride layer 152, with a thickness of about 100A-1000A, to cover the second conductive material 211 in the first trench 21 and prevent it from being oxidized in the subsequent oxidation step. The provision of the second nitride layer 16 can also minimize the probability of cross contamination problems that may occur in subsequent processes.

[0095] like Figure 6h As shown, the semiconductor body 10 is once again etched using the soft mask layer to form a second trench 22 and a third trench 31 in the semiconductor body 10. The second trench 22 is formed at the periphery of the first trench 21. The third trench 31 is formed between the second trench 22 and the first trench 21.

[0096] It is understood that the depth of the groove is related to the width of the groove, and the smaller the width, the shallower the depth. Therefore, the width of the third groove 31 is smaller than the width of the second groove 22, so that when the synchronous etching is performed, the second groove 22 extends from the top surface of the epitaxial layer 13 to the substrate 11 of the semiconductor body 10 and has a first depth D1, and the third groove 31 extends from the top surface of the epitaxial layer 13 to the substrate 11 of the semiconductor body 10 and has a second depth D2 less than the first depth D1. In some embodiments, the soft mask layer can be a photoresist. After the second groove 22 and the third groove 31 are etched, the soft mask layer is stripped.

[0097] like Figure 6i As shown, a liner 52 is grown on the sidewalls and bottom walls of the second trench 22 and the third trench 31 based on the same process. Exemplarily, the sidewalls and bottom walls of the second trench 22 and the third trench 31 are oxidized by a thermal oxidation process, and the thickness of the liner 52 is about 3000A to 5000A. Since the width of the second trench 22 and the third trench 31 is relatively wide, while the sidewalls and bottom walls of the second trench 22 and the third trench 31 are oxidized by a thermal oxidation process, the bottom walls and sidewalls of the second trench 22 and the third trench 31 are covered by thermal oxide, and the middle is still in an open state, and there is a large space that is not filled. It can be understood that since the width of the second trench 22 is greater than the width of the third trench 31, the remaining space in the second trench 22 after oxidation is also much larger than the remaining space in the third trench 31.

[0098] like Figure 6jAs shown, a dielectric layer 53 is deposited on the top of the second trench 22 and the third trench 31, so that the dielectric layer 53 is formed on the sidewalls and bottom walls of the second trench 22 and the third trench 31, and the surface of the second nitride layer 16. The dielectric layer 53 is preferably an oxide layer. The thickness of the dielectric layer 53 can be 5000A to 7000A. The second trench 22 still has a top opening space of about 0.8μm. The third trench 31 still has a top opening space of about 0.1um. An air gap may be formed inside the third trench 31, which helps to minimize mechanical stress.

[0099] like Figure 6k As shown, anisotropic etching is performed to remove the dielectric layer 53 and the liner 52 on the bottom wall of the second trench 22, and at least part of the bottom of the second trench 22 is opened. Since the top opening space of the third trench 31 is too small, the anisotropic etching process will not affect its bottom. The etching process will form a V-shape at the top of the second trench 22, which has a better effect on the subsequent filling of the first conductive material 51. At the same time, the etching process will etch the dielectric layer 53 and the liner 52 at the top of the third trench 31, and form a first opening 311 at the top surface of the epitaxial layer 13. The formation of the first opening 311 can facilitate the subsequent filling of the first conductive material 51, and also enable the third trench 31 to have a larger space to form a resistor.

[0100] Optionally, after the dielectric layer 53 is formed, an annealing process may be performed to densify the dielectric layer 53 to achieve a better isolation effect.

[0101] Optionally, low energy boron implantation (eg, B11-5E15 / 7KeV / 0 degree tilt) may be performed on the bottom of the second trench 22 to increase the doping level at the bottom of the second trench 22 , thereby enabling the first conductive material 51 filled subsequently to be better connected to the substrate 11 .

[0102] like Figure 6l As shown, the first conductive material 51 having the first doping type is deposited so that the first conductive material 51 fills the second trench 22 and at least fills the first opening 311 of the third trench 31. The first conductive material 51 in the second trench 22 is in full contact with the substrate 11 and is electrically connected. In order to better deposit the first conductive material 51, a multiple deposition process may be used. For example, after the first deposition, a dry etch-back process may be performed to further widen the top opening, thereby performing a better second filling and reducing the gaps in the second trench 22 and the third trench 31. The first conductive material 51, the dielectric layer 53, and the liner 52 together form a second trench structure in the second trench 22. The first conductive material 51 forms a resistor in the third trench 31.

[0103] like Figure 6mAs shown, the excess first conductive material 51, the second nitride layer 16 and the first nitride layer 152 can be removed by a chemical mechanical polishing (CMP) process, anisotropic plasma dry etching for etch-back process, H3PO4 wet process, diluted HF wet process, etc., so that the top surface of the first conductive material 51 and the top surface of the second conductive material 211 are kept at the same level as the epitaxial layer 13. The first nitride layer 152 serves as a stop layer for chemical mechanical polishing (CMP). The loss of the first nitride layer 152 depends on the selectivity rate of polishing, and the normal loss is less than 500A. Similarly, since part of the first conductive material 51 may also be deposited on the substrate 11 of the semiconductor body 10 when the first conductive material 51 is deposited, the first conductive material 51 on the substrate 11 of the semiconductor body 10 is removed while removing the first conductive material 51 on the first nitride layer 152, so as to obtain better wafer warpage and less stress.

[0104] like Figure 1 As shown, a shallow trench isolation structure 40 may be formed in the epitaxial layer 13. The shallow trench isolation structure 40 exposes the second conductive material 211 of the first trench structure, the first conductive material 51 of the second trench structure, and the first conductive material of the third trench resistor structure.

[0105] The size of the first conductive material 51 exposed in the third trench resistor structure is limited by the shallow trench isolation structure 40, and the resistance of the third trench resistor structure can be adjusted by adjusting the width of the overlapping area between the shallow trench isolation structure 40 and the third trench resistor structure (affecting the size of the exposed first conductive material 51), or by adjusting the width of the third trench 31.

[0106] Finally, the normal processes of subsequent CMOS devices are carried out: well implantation, gate, LDD implantation, spacer formation, source / drain implantation, silicide formation, ILD (interlayer dielectric layer), metal connection formation, BEoL metal layer and passivation, etc.

[0107] Among them, before the step of forming the metal connection, the first conductive material 51 in the first opening 311 of the third trench 31 can be counter-doped with different doping types or heavily doped with the same doping type using the previous existing process to change the doping concentration of the first conductive material 51 in the first opening 311, thereby adjusting the resistance value of the third trench resistor structure, and finally forming a metal connection on the first conductive material 51 in the third trench 31.

[0108] Compared with the prior art, the semiconductor device and the manufacturing method thereof of the present invention can form an isolation resistor structure in a non-device area of ​​the semiconductor device without increasing the cost of additional masks. The isolation resistor structure has both an isolation effect - it can increase the breakdown voltage between the first trench structure and the second trench structure that isolate different device areas; and a resistance function - it can provide the required resistance value of the device area; and does not occupy the area of ​​the device area.

[0109] The semiconductor device and its manufacturing method of the present invention can adjust the resistance of the isolation resistor structure by changing the width of the third trench and the doping concentration of the first conductive material in the third trench, and can also adjust the resistance of the isolation resistor structure by adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure.

[0110] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0111] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer; An isolation structure is disposed in the semiconductor body, the isolation structure divides the semiconductor body into a plurality of device regions, and the isolation structure includes a first trench and a second trench; The first trench extends from the top surface of the epitaxial layer into the buried layer, a first trench structure is disposed in the first trench, and the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer; The second trench extends from the top surface of the epitaxial layer into the substrate, a second trench structure is disposed in the second trench, and the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer; an isolation resistor structure, disposed in the semiconductor body and between the first trench and the second trench, the isolation resistor structure being at least used to provide a required resistance value for the device region, and the isolation resistor structure being configured to isolate the first trench structure from the second trench structure, and the isolation resistor structure comprising a third trench; The third trench extends from the top surface of the epitaxial layer into the substrate, and the depth of the third trench is less than the depth of the second trench. A third trench resistor structure is disposed in the third trench.

2. The semiconductor device according to claim 1, wherein: The third trench resistor structure comprises: A liner, disposed on an inner wall of the third groove; A dielectric layer is disposed in the third trench and located on the surface of the liner, wherein the dielectric layer and the liner are partially etched at the top surface of the epitaxial layer to form a first opening; A first conductive material is disposed in the third trench and at least fills the first opening.

3. The semiconductor device according to claim 2, characterized in that The first conductive material includes polysilicon having a first doping type.

4. The semiconductor device according to claim 2, characterized in that The resistance value of the isolation resistor structure is adjusted by changing the doping concentration of the first conductive material in the first opening.

5. The semiconductor device according to claim 4, characterized in that The first conductive material is counter-doped with a different doping type, or heavily doped with the same doping type, so as to change the doping concentration of the first conductive material.

6. The semiconductor device according to claim 4, characterized in that The third trench resistor structure is divided into a connection area and a functional area; The connection area is used to form a metal connection electrically connected to the first conductive material; The first conductive material in the functional area is counter-doped with a different doping type, or heavily doped with the same doping type, so as to change the doping concentration of the first conductive material.

7. The semiconductor device according to claim 6, characterized in that The first conductive material in the connection area is counter-doped with a different doping type to change the connection resistance between the metal connection and the first conductive material.

8. The semiconductor device according to claim 1, wherein: The width of the third groove is in the range of 0.6 μm-1.3 μm.

9. The semiconductor device according to claim 1, wherein: It also includes a shallow trench isolation structure, which is formed on the top surface of the epitaxial layer and extends into the epitaxial layer. The shallow trench isolation structure is at least partially overlapped with the third trench resistor structure.

10. The semiconductor device according to claim 9, characterized in that By adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure, the resistance value of the isolation resistor structure is adjusted.

11. The semiconductor device according to claim 9, characterized in that The width of the overlapping area between the shallow trench isolation structure and the third trench resistor structure is in the range of 0 μm-0.4 μm.

12. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer; forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer; forming a second trench and a third trench in the semiconductor body, wherein the second trench is disposed around the first trench, the second trench extends from the top surface of the epitaxial layer into the substrate and has a first depth, and the third trench is located between the first trench and the second trench, the third trench extends from the top surface of the epitaxial layer into the substrate and has a second depth less than the first depth; While forming the second trench structure in the second trench, a third trench resistor structure is formed in the third trench.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: Also includes: A shallow trench isolation structure is formed in the semiconductor body, wherein the shallow trench isolation structure exposes a portion of the first trench structure, a portion of the second trench structure, and a portion of the third trench resistor structure.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The resistance value of the isolation resistor structure is adjusted by adjusting the width of the overlapping area between the shallow trench isolation structure and the third trench resistor structure, or by adjusting the width of the third trench.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: While forming the second trench structure in the second trench, forming the third trench resistor structure in the third trench, comprising: forming a liner on inner walls of the second groove and the third groove; forming a dielectric layer on the surface of the liner in the second trench and the third trench; Etching and removing the liner and the dielectric layer on the bottom wall of the second trench, and forming a first opening at least on the top surface of the third trench; A first conductive material having a first doping type is deposited so that the first conductive material at least fills the second trench and the first opening.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The resistance value of the isolation resistor structure is adjusted by performing counter-doping of a different doping type or heavy doping of the same doping type on the first conductive material in the first opening to change the doping concentration of the first conductive material in the first opening.

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