Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device including an IGBT having improved switching characteristics is provided. A trench gate electrode and a trench emitter electrode are formed through a gate insulating film inside a trench formed inside a semiconductor substrate of an active cell. An n-type hole isolation region is formed inside the semiconductor substrate between the trenches. A p-type base region is formed inside the hole isolation region. An n-type emitter region is formed inside the base region. A p-type floating region is formed inside the semiconductor substrate of the passive cell. A depth of the floating region is shallower than each depth of the trench and deeper than a depth of the base region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-121670 filed on July 26, 2023, including specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device provided with a gate electrode formed inside a trench and a method for manufacturing the same. Background Art

[0004] Gate Electrode In recent years, semiconductor devices equipped with power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) have been widely used. In addition, IGBTs with low on-resistance are known, each of which uses a structure including a gate electrode embedded inside a trench.

[0005] The disclosed techniques are listed below.

[0006] [Patent Document 1] Japanese Laid-Open Patent Application Publication No. 2013-140885

[0007] [Patent Document 2] Japanese Laid-Open Patent Application No. 2017-157733

[0008] For example, IGBTs having a GGEE structure and an EGE structure utilizing the IE (Injection Enhancement) effect are disclosed in Patent Document 1. The IE effect is a technique for increasing the charge concentration accumulated in the drift region by making it difficult for holes to discharge toward the emitter wiring EW side when the IGBT is in an on state.

[0009] Note that the "G" in the GGEE structure means a trench gate electrode embedded in the trench and connected to the gate potential through a gate insulating film. The "E" in the GGEE structure means a trench emitter electrode embedded in the trench and connected to the emitter potential through a gate insulating film. Therefore, the GGEE structure is a structure in which a pair of trench emitter electrodes are formed at a certain distance from a pair of trench gate electrodes.

[0010] In addition, in Patent Document 2, an IGBT having a GGEEs structure is disclosed, in which the cell pitch of the GGEE structure is reduced. In the GGEEs structure, the distance between a pair of trench emitter electrodes is shorter than the distance between a pair of trench gate electrodes, and the trench emitter electrodes and the base region are connected through the same hole. That is, the "s" in the GGEEs structure means that the distance between the pair of trench emitter electrodes is reduced. Summary of the invention

[0011] IGBTs with a GGEE structure are used, for example, in inverters that require large currents. In this case, in order to ensure load short-circuit tolerance, the saturation current density cannot be increased more than necessary. In addition, in the design of such IGBTs, the focus is on reducing the on-voltage by promoting conductivity modulation without increasing the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) component.

[0012] On the other hand, IGBTs for PFC (power factor correction) applications are used in products such as air conditioners. In IGBTs for PFC applications, increasing the switching speed and reducing the switching loss are very important. In addition, since ensuring the load short-circuit tolerance has a low priority, the saturation current density can be increased.

[0013] If the GGEE structure manufacturing process can be used to manufacture IGBTs for PFC applications, the development cycle can be shortened, new manufacturing equipment is not required, and manufacturing costs can be reduced. In this case, it is necessary to design the IGBT to maintain a low on-voltage, increase the switching speed, and reduce the switching loss.

[0014] The main object of the present application is to provide a semiconductor device of an IGBT having improved switching characteristics. Other problems and novel features will become apparent from the description and drawings of this specification.

[0015] Typical embodiments disclosed in this application will be briefly described as follows.

[0016] A semiconductor device according to an embodiment includes: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface opposite to the upper surface; a first trench, a second trench, and a third trench, each of which is formed inside the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate; a trench gate electrode formed inside the first trench through a first insulating film; a first trench emitter electrode formed inside the second trench through a second insulating film; a second trench emitter electrode formed inside the third trench through a third insulating film; a first hole isolation region of the first conductivity type formed inside the semiconductor substrate between the first trench and the second trench; and a first base region of a second conductivity type opposite to the first conductivity type formed in the first hole isolation region. a first emitter region of a first conductivity type formed inside the first base region; a second hole isolation region of a first conductivity type formed inside the semiconductor substrate between the first trench and the third trench; a second base region of a second conductivity type formed inside the second hole isolation region; a second emitter region of a first conductivity type formed inside the second base region; a first floating region of a second conductivity type formed inside the semiconductor substrate on the other side surface side of the two side surfaces of the second trench opposite to the one side surface where the first hole isolation region is formed; and a second floating region of a second conductivity type formed inside the semiconductor substrate on the other side surface side of the two side surfaces of the third trench opposite to the one side surface where the second hole isolation region is formed. Each depth of the first floating region and the second floating region from the upper surface of the semiconductor substrate is shallower than each depth of the first trench, the second trench, and the third trench from the upper surface of the semiconductor substrate, and is deeper than each depth of the first base region and the second base region from the upper surface of the semiconductor substrate.

[0017] A method for manufacturing a semiconductor device according to one embodiment includes the following steps: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface opposite to the upper surface; (b) on the upper surface side of the semiconductor substrate, forming a first hole isolation region of the first conductivity type and a second hole isolation region of the first conductivity type inside the semiconductor substrate; (c) after step (b), forming a first trench and a second trench inside the semiconductor substrate so that the first hole isolation region is sandwiched between them in a plan view, and forming a third trench inside the semiconductor substrate so that the second hole isolation region is sandwiched between the third trench itself and the first trench in a plan view; (d) after step (c), forming a first insulating film inside the first trench, forming a second insulating film inside the second trench, and forming a third insulating film inside the third trench; (e) after step (d), forming a trench gate electrode inside the first trench through the first insulating film, and forming a trench gate electrode inside the second trench through the second insulating film. The insulating film forms a first trench emitter electrode inside the second trench, and a second trench emitter electrode is formed inside the third trench through a third insulating film; (f) after step (e), a first base region of a second conductivity type opposite to the first conductivity type is formed inside the first hole isolation region, a second base region of the second conductivity type is formed inside the second hole isolation region, a first floating region of the second conductivity type is formed inside the semiconductor substrate on the other side surface side of the two side surfaces of the second trench opposite to the one side surface forming the first hole isolation region, and a second floating region of the second conductivity type is formed inside the semiconductor substrate on the other side surface side of the two side surfaces of the third trench opposite to the one side surface forming the second hole isolation region; and (g) after step (f), a first emitter region of the first conductivity type is formed inside the first base region, and a second emitter region of the first conductivity type is formed inside the second base region. Each depth of the first and second floating regions from the upper surface of the semiconductor substrate is shallower than each depth of the first, second and third trenches from the upper surface of the semiconductor substrate, and deeper than each depth of the first and second base regions from the upper surface of the semiconductor substrate.

[0018] A semiconductor device according to an embodiment includes an IGBT, which includes a plurality of cells. Each of the plurality of cells includes: a trench gate electrode, a first trench emitter electrode, and a second trench emitter electrode, which are formed in an n-type semiconductor substrate; a p-type first base region, which is formed inside the semiconductor substrate between the trench gate electrode and the first trench emitter electrode; and a p-type second base region, which is formed inside the semiconductor substrate between the trench gate electrode and the second trench emitter electrode. A p-type floating region is formed inside the semiconductor substrate between the plurality of cells. The depth of the floating region is shallower than each depth of the trench gate electrode, the first trench emitter electrode, and the second trench emitter electrode, and is deeper than each depth of the first base region and the second base region.

[0019] According to one embodiment, a semiconductor device having an IGBT having improved switching characteristics can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a plan view showing the semiconductor device in the first embodiment.

[0021] Figure 2 is a plan view showing a main part of the semiconductor device in the first embodiment.

[0022] Figure 3 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0023] Figure 4 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0024] Figure 5 is a cross-sectional view showing a main part of the semiconductor device in the first embodiment.

[0025] Figure 6 is a graph showing the impurity concentration distribution of the active cell and the passive cell in the first embodiment.

[0026] Figure 7 1 is a cross-sectional view of a main part showing the structure of the first embodiment, the test example 1, and the test example 2.

[0027] Figure 8 is a graph showing the performance of the first embodiment, the inspection example 1, and the inspection example 2.

[0028] Fig. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device in the first embodiment.

[0029] Fig.10 It is shown Fig. 9Cross-sectional view of the subsequent manufacturing process.

[0030] Fig.11 It is shown Fig.10 Cross-sectional view of the subsequent manufacturing process.

[0031] Fig.12 It is shown Fig.11 Cross-sectional view of the subsequent manufacturing process.

[0032] Fig.13 It is shown Fig.12 Cross-sectional view of the subsequent manufacturing process.

[0033] Fig.14 It is shown Fig.13 Cross-sectional view of the subsequent manufacturing process.

[0034] Fig.15 It is shown Fig.14 Cross-sectional view of the subsequent manufacturing process.

[0035] Fig.16 It is shown Fig.15 Cross-sectional view of the subsequent manufacturing process.

[0036] Fig.17 It is shown Fig.16 Cross-sectional view of the subsequent manufacturing process.

[0037] Fig.18 It is shown Fig.17 Cross-sectional view of the subsequent manufacturing process. DETAILED DESCRIPTION

[0038] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated description is omitted. In the following embodiments, unless particularly necessary, the description of the same or similar components will not be repeated in principle.

[0039] In addition, the X direction, Y direction and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the up-down direction, height direction, depth direction or thickness direction of a specific structure. In addition, expressions such as "plan view" or "flat view" used in the present application mean that the surface composed of the X direction and the Y direction is a "plane", and the "plane" is observed in the Z direction.

[0040] (First embodiment)

[0041] <Structure of semiconductor device>

[0042] The following will use Figures 1 to 4The structure of the semiconductor device 100 in the first embodiment is described.

[0043] Figure 1 1 is a plan view showing a semiconductor chip, which is a semiconductor device 100. Figure 1 As shown, most of the semiconductor device 100 is covered by the emitter wiring EW. In a plan view, the gate wiring GW surrounds the emitter wiring EW.

[0044] Although not shown in the figure, the emitter wiring EW and the gate wiring GW are covered with a protective film such as a polyimide film. On the emitter wiring EW and the gate wiring GW, some of the protective film has openings, and the areas exposed at the openings become the emitter pads EP and the gate pads GP. On the emitter pads EP and the gate pads GP, the semiconductor device 100 is electrically connected to other semiconductor chips, lead frames, wiring substrates, etc. by connecting external connection members. Note that the external connection members are, for example, wires made of aluminum, gold, or copper, or clips made of copper plates.

[0045] Figure 2 is corresponding to Figure 1 1A is a plan view of the main part of the region 1A shown. The semiconductor device 100 includes an IGBT formed on a semiconductor substrate SUB. This IGBT is an EGE structure IGBT using the IE effect. The EGE structure IGBT includes a plurality of active cells AC for performing the main operation of the IGBT and a plurality of passive cells IAC arranged between the active cells AC. An active cell AC includes a trench gate electrode GE and two trench emitter electrodes EE. The plurality of active cells AC are adjacent to each other in the X direction. In the semiconductor substrate SUB located between the active cells AC, a p-type floating region PF is provided.

[0046] like Figure 2 As shown, a plurality of trenches TR1 and TR2 extend in the Y direction and are adjacent to each other in the X direction. A plurality of trenches TR1 and TR2 are formed at the same pitch in the X direction. Inside the trench TR1, a trench gate electrode GE is formed through the gate insulating film GI. Inside the trench TR2, a trench emitter electrode EE is formed through the gate insulating film GI.

[0047] In the semiconductor substrate SUB of the active cell AC, a p-type base region PB is formed. In the base region PB, an n-type emitter region NE is formed. In the semiconductor substrate SUB of the passive cell IAC, a floating region PF is formed. The emitter region NE extends intermittently in the Y direction while contacting the trench TR1, but the emitter region NE is not formed near the end of the trench TR1 (near the hole CH2).

[0048] The gate wiring GW is electrically connected to the trench gate electrode GE through the plug PG formed inside the hole CH2, and supplies a gate potential during the operation of the IGBT. The emitter wiring EW is electrically connected to the trench emitter electrode EE, the base region PB, and the emitter region NE through the plug PG formed inside the hole CH1, and supplies an emitter potential during the operation of the IGBT.

[0049] Figure 3 It is along Figure 2 . The semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface opposite to the upper surface. The semiconductor substrate SUB is made of n-type silicon and has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the semiconductor substrate SUB may be a laminated film of an n-type silicon substrate and an n-type silicon layer grown by introducing phosphorus (P) on the silicon substrate by an epitaxial growth method. In this case, the n-type silicon layer having an impurity concentration lower than that of the n-type silicon substrate constitutes the drift region NV.

[0050] An n-type field stop region (impurity region) NS is formed on the lower surface of the semiconductor substrate SUB. The impurity concentration of the field stop region NS is higher than the impurity concentration of the drift region NV. The field stop region NS is provided to prevent the depletion layer extending from the pn junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC during turn-off of the IGBT.

[0051] A p-type collector region (impurity region) PC is formed on the lower surface of the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0052] The collector electrode CE is formed on the lower surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector CE is a single-layer metal film such as an Au film, a Ni film, a Ti film, or an AlSi film, or a laminated metal film appropriately laminated with these.

[0053] Note that the collector electrode CE, the collector region PC, and the field stop region NS are formed over the entire semiconductor substrate SUB of the active cell AC and the passive cell IAC.

[0054] Inside the semiconductor substrate SUB of the active cell AC, trenches TR1 and TR2 are formed to reach a predetermined depth from the upper surface of the semiconductor substrate SUB. The trenches TR1 and TR2 penetrate the emitter region NE, the base region PB, and the floating region PF to be described later. Each depth of the trenches TR1 and TR2 is, for example, 2 μm or more and 6 μm or less.

[0055] A gate insulating film (insulating film) GI is formed inside the trenches TR1 and TR2. A trench gate electrode GE is formed inside the trench TR1 through the gate insulating film GI. A trench emitter electrode EE is formed inside the trench TR2 through the gate insulating film (insulating film) GI. The gate insulating film GI is an insulating film such as a silicon oxide film. Each of the trench gate electrode GE and the trench emitter electrode EE is a conductive film such as a polysilicon film into which n-type impurities have been introduced. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.

[0056] In the active cell AC, an n-type hole isolation region (impurity region) NHB is formed inside the semiconductor substrate SUB between the trench TR1 and the trench TR2 (between the trench gate electrode GE and the trench emitter electrode EE). The impurity concentration of the hole isolation region NHB is higher than the impurity concentration of the drift region NV and lower than the impurity concentration of the emitter region NE. The depth of the hole isolation region NHB from the upper surface of the semiconductor substrate SUB is deeper than the depth of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB. During the operation of the IGBT, the hole isolation region NHB suppresses the discharge of holes reaching the base region PB. That is, it acts as a potential barrier for holes.

[0057] Inside the hole isolation region NHB, a p-type base region (impurity region) PB is formed. Inside the p-type base region PB, an n-type emitter region (impurity region) NE is formed. The impurity concentration of the emitter region NE is higher than the impurity concentration of the drift region NV. The depth of the base region PB from the upper surface of the semiconductor substrate SUB is shallower than the depth of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB. The base region PB that is in contact with the trench TR1 and is located below the emitter region NE is used as a channel region.

[0058] An active cell AC of the IGBT includes a trench TR1, two trenches TR2, gate insulating films GI in the trenches TR1 and TR2, a trench gate electrode GE, two trench emitter electrodes EE, two hole isolation regions NHB, two base regions PB, two emitter regions NE and a collector region PC.

[0059] On the upper surface side of the semiconductor substrate SUB, a p-type floating region (impurity region) PF is formed inside the semiconductor substrate SUB between the active cells AC (inside the semiconductor substrate SUB of the passive cell IAC). The floating region PF is not electrically connected to the gate wiring GW and the emitter wiring EW, no potential is supplied, and the floating region PF is in an electrically floating state.

[0060] On the upper surface of the semiconductor substrate SUB of the active cell AC and the passive cell IAC, an interlayer insulating film IL is formed so as to cover the trenches TR1, TR2. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600nm or more and 1500nm or less.

[0061] A hole CH1 is formed inside the interlayer insulating film IL. The hole CH1 is formed to penetrate the interlayer insulating film IL to a depth deeper than the emitter region NE, and is formed not to penetrate the base region PB. In other words, the hole CH1 includes an opening formed in the interlayer insulating film IL and a recess formed inside the semiconductor substrate SUB to span between the trench emitter electrode EE and the emitter region NE. That is, the hole CH1 penetrates the interlayer insulating film IL and reaches the trench emitter electrode EE, the base region PB, and the emitter region NE. In other words, in a plan view, the hole CH1 is formed to overlap the trench emitter electrode EE, the base region PB, and the emitter region NE.

[0062] In the base region PB around the bottom of the hole CH1, a p-type high concentration diffusion region (impurity region) PR is formed. The impurity concentration of the high concentration diffusion region PR is higher than that of the base region PB. The high concentration diffusion region PR is provided mainly to reduce the contact resistance with the plug PG and prevent latch-up.

[0063] The plug PG is embedded in the hole CH1. The plug PG contacts the trench emitter electrode EE, the base region PB, the emitter region NE and the high concentration diffusion region PR. The plug PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.

[0064] At the upper part of the hole CH1, the interlayer insulating film IL is retreated. That is, the opening size of the hole CH1 above the upper surface of the semiconductor substrate SUB is larger than the opening size of the hole CH1 below the upper surface of the semiconductor substrate SUB. Therefore, a part of the upper surface of each of the emitter region NE and the trench emitter electrode EE is exposed from the interlayer insulating film IL. Therefore, inside the hole CH1, the plug PG is in contact with not only the side surface of each of the emitter region NE and the trench emitter electrode EE, but also a part of the upper surface of each of the emitter region NE and the trench emitter electrode EE. This allows the contact resistance between the plug PG and the emitter region NE and the trench emitter electrode EE to be reduced.

[0065] Although not shown here, Figure 2The hole CH2 shown is also formed in the interlayer insulating film IL. The hole CH2 is formed to overlap with the trench gate electrode GE in a plan view, penetrate the interlayer insulating film IL and reach the trench gate electrode GE. Inside the hole CH2, a plug PG is also formed. In addition, at the upper part of the hole CH2, the interlayer insulating film IL is retreated. That is, the opening size of the hole CH2 above the upper surface of the semiconductor substrate SUB is larger than the opening size of the hole CH2 below the upper surface of the semiconductor substrate SUB.

[0066] Inside the interlayer insulating film IL located on the floating region PF, holes such as CH1 and CH2 are not formed.

[0067] On the interlayer insulating film IL, an emitter wiring EW is formed. The emitter wiring EW is electrically connected to the trench emitter electrode EE, the base region PB, the emitter region NE, and the high-concentration diffusion region PR through the plug PG inside the hole CH1, and supplies an emitter potential to these components. Although not shown here, on the interlayer insulating film IL, a gate wiring GW is also formed, which is formed by the same manufacturing process as the emitter wiring EW. The gate wiring GW is electrically connected to the trench gate electrode GE through the plug PG inside the hole CH2, and supplies a gate potential to the trench gate electrode GE.

[0068] Such emitter wiring EW and gate wiring GW include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film to which copper or silicon is added. The aluminum alloy film is the main conductor film of the emitter wiring EW and the gate wiring GW, and is sufficiently thicker than the TiW film.

[0069] <Details of the impurity region around the trench>

[0070] exist Figure 3 In the cross-sectional structure, Figure 4 Only the trench TR1 , the trench TR2 , and the main impurity regions around them are shown. Figure 5 The cross-sectional directions of the impurity concentration distribution Pac of the active cell AC and the impurity concentration distribution Piac of the passive cell IAC are shown. Figure 6 It is shown Figure 5 Shown is a graph of impurity concentration distribution Pac and Piac.

[0071] use Figures 4 to 6 , a detailed relationship between one trench TR1, two trenches TR2, and impurity regions around them included in one active cell AC will be described.

[0072] like Figure 4As shown, the trench TR1 has a side surface SS1, a side surface SS2 opposite to the side surface SS1, and a bottom surface BS1 connecting the side surfaces SS1 and SS2. One of the trenches TR2 has a side surface SS3, a side surface SS4 opposite to the side surface SS3, and a bottom surface BS2 connecting the side surfaces SS3 and SS4. The other trench TR2 has a side surface SS5, a side surface SS6 opposite to the side surface SS5, and a bottom surface BS3 connecting the side surfaces SS5 and SS6.

[0073] One of the trench TR1 and the trench TR2 is disposed at an interval so that the side surfaces SS1 and SS4 are adjacent to each other. The trench TR1 and the other trench TR2 are disposed at an interval so that the side surfaces SS2 and SS5 are adjacent to each other.

[0074] A hole isolation region NHB, a base region PB, and an emitter region NE are provided in the semiconductor substrate SUB between the side surfaces SS1 and SS4. A hole isolation region NHB contacts the side surfaces SS1, SS4, the bottom surface BS1, and the bottom surface BS2, but does not contact the side surface SS3. A base region PB contacts the side surfaces SS1 and SS4, but does not contact the bottom surfaces BS1 and BS2. An emitter region NE contacts the side surface SS1.

[0075] Another hole isolation region NHB, another base region PB, and another emitter region NE are provided in the semiconductor substrate SUB between the side surfaces SS2 and SS5. Another hole isolation region NHB is in contact with the side surfaces SS2 and SS5 and the bottom surfaces BS1 and BS3, but not in contact with the side surface SS6. Another base region PB is in contact with the side surfaces SS2 and SS5, but not in contact with the bottom surfaces BS1 and BS3. Another emitter region NE is in contact with the side surface SS2.

[0076] Each floating region PF is disposed in the semiconductor substrate SUB between the side surfaces SS3 and SS6 , in contact with the side surfaces SS3 and SS6 , but not in contact with the bottom surfaces BS2 and BS3 .

[0077] like Figure 4 As shown, a depth Dpb of the base region PB from the upper surface of the semiconductor substrate SUB and a depth Dpf of the floating region PF from the upper surface of the semiconductor substrate SUB are shallower than respective depths of the trenches TR1 and TR2 from the upper surface of the semiconductor substrate SUB.

[0078] from Figure 6 It can be seen from the impurity concentration distribution in that the floating region PF is formed at a deeper position than the base region PB. That is, the depth Dpf of the floating region PF is deeper than the depth Dpb of the base region PB. In addition, the impurity concentration of the floating region PF is actually higher than the impurity concentration of the base region PB.

[0079] Inside the semiconductor substrate SUB of the active cell AC, a hole isolation region NHB is formed. However, inside the semiconductor substrate SUB of the passive cell IAC, a high-concentration n-type impurity region such as the hole isolation region NHB having a concentration higher than that of the semiconductor substrate SUB (drift region NV) is not formed. In other words, in the active cell AC, the base region PB forms a pn junction with the hole isolation region NHB and the emitter region NE. In addition, in the passive cell IAC, the floating region PF forms a pn junction with the semiconductor substrate SUB (drift region NV).

[0080] Since the p-type base region PB is formed inside the high-concentration n-type hole isolation region NHB having a higher concentration than the semiconductor substrate SUB, the proportion of the p-type conductivity offset by the n-type conductivity in the base region PB is greater than that in the floating region PF. Therefore, the impurity concentration of the base region PB formed inside the hole isolation region NHB is substantially lower than the impurity concentration of the floating region PF. In addition, the depth Dpb of the base region PB is shallower than the depth Dpf of the floating region PF.

[0081] <Verification Example and Main Features of First Embodiment>

[0082] The following will use Figure 7 and Figure 8 The main features of the semiconductor device 100 of the first embodiment are described, and when necessary, compared with semiconductor device test examples 1 and 2. Note that the semiconductor devices of test examples 1 and 2 are based on the technology disclosed in Patent Document 1 or 2, and were tested by the present inventors. Figure 8 is a graph showing turn-off waveforms of the first embodiment, the inspection example 1, and the inspection example 2.

[0083] Test Example 1 Refer to the GGEE structure technology described in Patent Document 1, etc. Figure 7 As shown, inside the semiconductor substrate SUB of the passive cell IAC, a p-type impurity region PFa is formed instead of the floating region PF of the first embodiment. The impurity region PFa is in an electrically floating state. The impurity region PFa is formed deeper than the floating region PF and is formed to cover the bottom surface (BS2, BS3) of the trench TR2.

[0084] Verification Example 2 is an example in which the impurity structure of the passive cell IAC is made the same as the impurity structure of the active cell AC except that the emitter region NE does not exist. Figure 7 As shown, an n-type hole isolation region NHB is formed inside the semiconductor substrate SUB of the passive cell IAC, and a p-type impurity region PFb is formed inside the hole isolation region NHB. The impurity region PFb is formed by the same manufacturing process as the base region PB, but the impurity region PFb is in an electrically floating state.

[0085] In an IGBT for PFC application, the priority of ensuring load short-circuit tolerance is low, so the saturation current density can be increased. Therefore, it is necessary to increase the MOSFET component per unit area of ​​the IGBT. In the GGEE structure, the MOSFET component is formed on one side surface of each of the two trench gate electrodes GE. In the EGE structure of the first embodiment, the MOSFET component can be formed on both side surfaces of one trench gate electrode GE. Therefore, the MOSFET component per unit area of ​​the IGBT can be increased.

[0086] Furthermore, in the GGEE structure, the distance between the trench gate electrode GE and the trench emitter electrode EE is relatively long. However, in the first embodiment, the plurality of trenches TR1, TR2 are formed at the same pitch. Also in this regard, the MOSFET components per unit area of ​​the IGBT can be additionally increased.

[0087] Furthermore, since the connections between the trench emitter electrode EE, the base region PB, the emitter region NE and the emitter wiring EW are common in one hole CH1 (one plug PG), miniaturization of the IGBT can be achieved. This allows the MOSFET components per unit area of ​​the IGBT to be additionally increased.

[0088] In addition, if Figure 2 As shown, the emitter region NE extends intermittently in the Y direction while being in contact with the trench TR1. This widens the gate width of the MOSFET component and allows the saturation current density to be additionally increased.

[0089] However, by increasing the MOSFET components, the parasitic capacitance between the trench gate electrode GE and the drift region NV increases, the switching speed decreases, and the switching loss increases. Therefore, the floating region PF is provided between the trench emitter electrodes EE to accumulate holes to be injected from the bottom surface of the semiconductor substrate SUB.

[0090] Here, the parasitic PMOS is configured to include a floating region PF as a source, a base region PB as a drain, a drift region NV and a hole isolation region NHB as a channel, and a trench emitter electrode EE at an emitter potential as a gate. When enough holes are accumulated in the floating region PF and the potential becomes high, the parasitic PMOS is turned on. Then, the holes move from the floating region PF to the base region PB and are automatically discharged to the emitter wiring EW. Therefore, the reduction in switching speed and the increase in switching loss can be suppressed. In addition, due to the above-mentioned function of the parasitic PMOS, the potential fluctuation of the floating region PF is suppressed, and therefore, the potential of the trench gate electrode GE can be stabilized, and the switching loss during switching can be suppressed.

[0091] like Figure 7As shown, in Test Example 1, a relatively deep impurity region PFa is formed instead of the floating region PF. In this case, holes are accumulated in the impurity region PFa, and the depletion layer cannot diffuse between the trench emitter electrode EE and the trench gate electrode GE until all the holes in the impurity region PFa are discharged. Figure 8 As shown, in the test example 1, the rise of the collector voltage Vc is slow, and the flow time of the collector current Ic is later than that of the first embodiment. That is, in the test example 1, the turn-off is delayed, and the switching speed is reduced.

[0092] In addition, as described in the GGEE structure, when the distance between the trench emitter electrode EE and the trench gate electrode GE is relatively large, a deep p-type impurity region such as the impurity region PFa is required because the breakdown voltage BVCES (withstand voltage between the collector region PC and the emitter region NE) is reduced. However, as described in the first embodiment, in the case where a plurality of trenches TR1, TR2 are formed at the same pitch, the trench emitter electrodes EE at the emitter potential are uniformly arranged, and therefore, there is no need to worry about a reduction in the breakdown voltage BVCES. Therefore, the depth of the floating region PF in the first embodiment can be shallower than the depth of the trench TR2.

[0093] Note that the distance between two trenches TR2 (trench emitter electrodes EE) adjacent to each other across the floating region PF can be narrower than the distance between the trench TR1 (trench gate electrode GE) and the trench TR2 (trench emitter electrode EE). This allows the proportion of MOSFET components inside the semiconductor device 100 to be increased. Therefore, it may be possible to achieve a reduction in on-voltage or an improvement in switching characteristics.

[0094] like Figure 7 As shown, in Test Example 2, the hole isolation region NHB is formed below the p-type impurity region PFb. In this case, holes injected from the bottom surface of the semiconductor substrate SUB are suppressed by the hole isolation region NHB, and as shown in FIG. Figure 8 As shown, in the test example 2, the rise of the collector voltage Vc is slow, and the flow time of the collector current Ic is later than those of the first embodiment. That is, in the test example 2, the turn-off is delayed, and the switching speed is reduced.

[0095] As described above, in the first embodiment, by applying the EGE type IGBT to the active cell AC and providing the floating region PF in the passive cell IAC, it is possible to maintain a low on-voltage while achieving a high switching speed and reducing switching loss. In other words, according to the first embodiment, a semiconductor device 100 equipped with an IGBT having improved switching characteristics can be provided.

[0096] <Method of Manufacturing Semiconductor Device>

[0097] In the following, we will use Figures 9 to 18 Each manufacturing process included in the method of manufacturing the semiconductor device 100 in the first embodiment is described.

[0098] like Fig. 9 As shown, first, an n-type semiconductor substrate SUB having an upper surface and a lower surface is prepared. The semiconductor substrate SUB is made of silicon. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown by introducing phosphorus (P) on the silicon substrate by an epitaxial growth method.

[0099] Next, by using a photolithography technique and an ion implantation method, on the upper surface side of the semiconductor substrate SUB, a hole isolation region NHB is selectively formed inside the semiconductor substrate SUB.

[0100] like Fig.10 As shown, trenches TR1 and TR2 are formed inside the semiconductor substrate SUB so that the hole isolation region NHB is located between the trenches TR1 and TR2 on the upper surface side of the semiconductor substrate SUB. In other words, trenches TR1 and TR2 are formed inside the semiconductor substrate SUB to sandwich the hole isolation region NHB in a plan view.

[0101] First, for example, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method. Next, a resist pattern having an opening is formed on the silicon oxide film. Then, by performing anisotropic etching using the resist pattern as a mask, the silicon oxide film is patterned to form a hard mask HM. Then, the resist pattern is removed by ashing.

[0102] Next, by performing anisotropic etching using the hard mask HM as a mask, trenches TR1 and TR2 reaching a predetermined depth from the upper surface of the semiconductor substrate SUB are formed inside the semiconductor substrate SUB Then, the hard mask HM is removed by, for example, wet etching using a solution including hydrofluoric acid.

[0103] like Fig.11 As shown, a sacrificial oxide film IF1 is formed inside the trench TR1, inside the trench TR2, and on the upper surface of the semiconductor substrate SUB. This removes the damaged layer formed inside the semiconductor substrate SUB. Then, the sacrificial oxide film IF1 is removed by isotropic etching using, for example, a solution including hydrofluoric acid.

[0104] Note that the sacrificial oxide film IF1 is formed by heat treating the semiconductor substrate SUB in an atmosphere filled with oxygen at, for example, 1100° C. for 30 minutes or more and 60 minutes or less.

[0105] Through this heat treatment, impurities included in the hole isolation region NHB are diffused. The depth of the hole isolation region NHB from the upper surface of the semiconductor substrate SUB becomes deeper than each of the depths of the trench TR1 and the trench TR2 from the upper surface of the semiconductor substrate SUB.

[0106] like Fig.12 As shown, a gate insulating film (insulating film) GI and a conductive film CF1 are formed inside the trenches TR1 and TR2.

[0107] First, by heat treatment using oxygen and hydrogen under conditions of, for example, 950° C. for 60 minutes, a gate insulating film GI is formed inside the trenches TR1 and TR2 and on the upper surface of the semiconductor substrate SUB.

[0108] Next, a conductive film CF1 is formed on the gate insulating film GI by, for example, a CVD method to fill the insides of the trenches TR1 and TR2 through the gate insulating film GI. The conductive film CF1 is, for example, a polysilicon film into which an n-type impurity is introduced.

[0109] like Fig.13 As shown, the trench gate electrode GE is formed inside the trench TR1 through the gate insulating film GI, and the trench emitter electrode EE is formed inside the trench TR2 through the gate insulating film GI.

[0110] First, the conductive film CF1 formed outside the trenches TR1 and TR2 is removed by anisotropic etching. The conductive film CF1 formed inside the trench TR1 is left as a trench gate electrode GE, and the conductive film CF1 formed inside the trench TR2 is left as a trench emitter electrode EE. Next, the gate insulating film GI formed outside the trenches TR1 and TR2 is removed by isotropic etching, anisotropic etching, or a combination of these etching processes.

[0111] like Fig.14 As shown, the p-type base region PB is formed inside the hole isolation region NHB by ion implantation. At the same time, the p-type floating region PF is formed inside the semiconductor substrate SUB, which is located on the other side surface of the two side surfaces of the trench TR2 opposite to the one side surface where the hole isolation region NHB is formed. Note that the p-type base region PB and the floating region PF can be formed by multiple ion implantations. By appropriately adjusting the implantation energy each time, the floating region PF of a desired depth can be formed.

[0112] That is to say, reference Figure 4, the base region PB is formed inside the semiconductor substrate SUB between the side surfaces SS1 and SS4 and between the side surfaces SS2 and SS5, and the floating region PF is formed inside the semiconductor substrate SUB between the side surfaces SS3 and SS6. In other words, the base region PB is formed inside the semiconductor substrate SUB of the active cell AC, and the floating region PF is formed inside the semiconductor substrate SUB of the passive cell IAC.

[0113] like Fig.15 As shown, the n-type emitter region NE is selectively formed inside the base region PB by a photolithography technique and an ion implantation method. Then, a heat treatment is performed to activate the impurities included in the hole isolation region NHB, the floating region PF, the base region PB, and the emitter region NE. The heat treatment is performed under the conditions of, for example, 900° C. or higher and 1000° C. or lower, and 30 seconds or longer and 50 seconds or shorter in an atmosphere filled with an inert gas such as nitrogen.

[0114] At this point, the Figure 6 The impurity concentration distribution shown. Inside the semiconductor substrate SUB forming the base region PB, a hole isolation region NHB is formed. However, inside the semiconductor substrate SUB forming the floating region PF, there is no n-type impurity region with a higher concentration than the semiconductor substrate SUB (drift region NV), such as the hole isolation region NHB. Therefore, the proportion of p-type conductivity offset by n-type conductivity is higher in the base region PB than in the floating region PF. Therefore, although the base region PB and the floating region PF are formed in the same ion implantation process, the impurity concentration of the base region PB is actually lower than the impurity concentration of the floating region PF. In addition, the depth Dpb of the base region PB is shallower than the depth Dpf of the floating region PF.

[0115] like Fig.16 As shown, first, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trenches TR1 and TR2. The interlayer insulating film IL is, for example, a silicon oxide film.

[0116] Next, a hole CH1 is formed inside the interlayer insulating film IL by photolithography and anisotropic etching. The hole CH1 reaches the trench emitter electrode EE, the base region PB, and the emitter region NE. Next, a p-type high concentration diffusion region PR is selectively formed inside the base region PB at the bottom of the hole CH1 by ion implantation.

[0117] Next, although not shown here, holes CH2 reaching the trench gate electrode GE are formed inside the interlayer insulating film IL by photolithography and anisotropic etching processes. The process of forming the holes CH1 and the process of forming the holes CH2 may be performed in any order.

[0118] Not only during the process of forming the holes CH1 and CH2 but also in the subsequent manufacturing processes, no holes are formed inside the interlayer insulating film IL located on the floating region PF. Therefore, the floating region PF becomes a region not supplied with a potential and is electrically in a floating state.

[0119] like Fig.17 As shown, by performing an isotropic etching process on the interlayer insulating film IL, the interlayer insulating film IL retreats. As a result, the opening width of the hole CH1 located on the upper surface of the semiconductor substrate SUB becomes larger than the opening width of the hole CH1 located inside the semiconductor substrate SUB. Note that the interlayer insulating film IL of the hole CH2 also retreats by this isotropic etching process.

[0120] like Fig.18 As shown, the plug PG is formed inside the hole CH1 , and the emitter wiring EW is formed on the interlayer insulating film IL.

[0121] First, a barrier metal film is formed inside the hole CH1 and on the interlayer insulating film IL. The barrier metal film can be formed by forming a titanium film inside the hole CH1 and on the interlayer insulating film IL by, for example, a sputtering method, and forming a titanium nitride film on the titanium film by, for example, a sputtering method. Next, a conductive film made of, for example, a tungsten film is formed on the barrier metal film by, for example, a CVD method to fill the inside of the hole CH1. Then, the conductive film and the barrier metal film formed outside the hole CH1 are removed by an anisotropic etching process. As a result, a plug PG is formed to fill the inside of the hole CH1. Note that during these manufacturing processes, the plug PG is also formed inside the hole CH2.

[0122] Next, the emitter wiring EW is formed on the interlayer insulating film IL. First, a TiW film is formed on the interlayer insulating film IL by, for example, a sputtering method, and an aluminum alloy film is formed on the TiW film by, for example, a sputtering method. Then, the TiW film and the aluminum alloy film are patterned by a photolithography technique and a dry etching process to form the emitter wiring EW. Note that during these manufacturing processes, the gate wiring GW is also formed on the interlayer insulating film IL.

[0123] After that, the following manufacturing process is used to obtain Figure 3The structure shown. First, the wafer is ground to be extremely thin as needed. Then, by performing ion implantation from the lower surface of the semiconductor substrate SUB, an n-type field stop region NS and a p-type collector region PC are formed inside the semiconductor substrate SUB. After these ion implantations, the impurities included in the field stop region NS and the collector region PC are activated by laser annealing. Then, a metal film, such as an Au film, a Ni film, a Ti film or an AlSi film, is formed on the lower surface of the semiconductor substrate SUB by, for example, a sputtering method. The metal film becomes the collector CE. The collector CE can be a laminated film formed by appropriately laminating metal films.

[0124] Therefore, according to the manufacturing method of the first embodiment, the semiconductor device 100 can be manufactured using the same manufacturing process as the manufacturing process for manufacturing an IGBT having a GGEE structure and an EGE structure described in Patent Document 1. Therefore, the development period can be shortened, new manufacturing equipment is not required, and the manufacturing cost can be reduced.

[0125] Furthermore, according to the manufacturing method of the first embodiment, the floating region PF can be formed in the process of forming the base region PB. Therefore, it is possible to omit the formation of the deep floating region shown in Patent Document 1 and the like and reduce the manufacturing cost accordingly.

[0126] Although the present invention has been specifically described based on the embodiments, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit thereof.

Claims

1. A semiconductor device, comprising: A semiconductor substrate of a first conductivity type having an upper surface and a lower surface opposite to the upper surface; A first trench, a second trench, and a third trench, each formed inside the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate; A trench gate electrode formed inside the first trench through a first insulating film; a first trench emitter electrode formed inside the second trench through a second insulating film; a second trench emitter electrode formed inside the third trench through a third insulating film; The first hole isolation region of the first conductivity type is formed inside the semiconductor substrate between the first trench and the second trench; A first base region of a second conductivity type opposite to the first conductivity type is formed inside the first hole isolation region; The first emitter region of the first conductivity type is formed inside the first base region; The second hole isolation region of the first conductivity type is formed inside the semiconductor substrate between the first trench and the third trench; The second base region of the second conductivity type is formed inside the second hole isolation region; The second emitter region of the first conductivity type is formed inside the second base region; a first floating region of the second conductivity type formed inside the semiconductor substrate, the first floating region being located on the other side surface side of the two side surfaces of the second trench opposite to the one side surface where the first hole isolation region is formed; as well as a second floating region of the second conductivity type formed inside the semiconductor substrate, the second floating region being located on the other side surface side of the two side surfaces of the third trench opposite to the one side surface where the second hole isolation region is formed, Wherein each depth of the first floating region and the second floating region from the upper surface of the semiconductor substrate is shallower than each depth of the first trench, the second trench and the third trench from the upper surface of the semiconductor substrate, and is deeper than each depth of the first base region and the second base region from the upper surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, Wherein each impurity concentration of the first floating region and the second floating region is higher than each impurity concentration of the first base region and the second base region.

3. The semiconductor device according to claim 1, Each depth of the first hole isolation region and the second hole isolation region from the upper surface of the semiconductor substrate is deeper than each depth of the first trench, the second trench, and the third trench from the upper surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, further comprising: an interlayer insulating film formed on the upper surface of the semiconductor substrate to cover the first trench, the second trench, and the third trench; a first hole that penetrates the interlayer insulating film and reaches the first trench emitter electrode, the first base region, and the first emitter region; second holes that penetrate the interlayer insulating film and reach the second trench emitter electrode, the second base region, and the second emitter region; a third hole that penetrates the interlayer insulating film and reaches the trench gate electrode; a first plug formed inside the first cavity; a second plug formed inside the second cavity; A third plug formed inside the third cavity; and An emitter wiring and a gate wiring are formed on the interlayer insulating film, wherein the first trench emitter electrode, the first base region, and the first emitter region are electrically connected to the emitter wiring through the first plug, wherein the second trench emitter electrode, the second base region, and the second emitter region are electrically connected to the emitter wiring through the second plug, wherein the trench gate electrode is electrically connected to the gate wiring through the third plug, and Each of the first floating region and the second floating region is in an electrically floating state.

5. The semiconductor device according to claim 4, No voids are formed inside the interlayer insulating film located on the first floating region and the second floating region.

6. The semiconductor device according to claim 1, wherein the first groove, the second groove and the third groove extend in a first direction in a plan view and are adjacent to each other in a second direction orthogonal to the first direction, and The first emitter region and the second emitter region extend intermittently in the first direction while contacting the first trench.

7. The semiconductor device according to claim 6, further comprising: The collector region of the second conductivity type is formed on the lower surface of the semiconductor substrate, The active unit of the IGBT includes the trench gate electrode, the first trench emitter electrode, the second trench emitter electrode, the first hole isolation region, the second hole isolation region, the first base region, the second base region, the first emitter region, the second emitter region and the collector region.

8. The semiconductor device according to claim 7, further comprising: a plurality of said active units, wherein the plurality of active cells are adjacent to each other in the second direction, and The first floating region or the second floating region is formed inside the semiconductor substrate between the plurality of active cells.

9. The semiconductor device according to claim 8, The first trench, the second trench, and the third trench included in each of the plurality of active cells are formed at the same pitch in the second direction.

10. The semiconductor device according to claim 1, Each of the first floating region and the second floating region forms a pn junction with the semiconductor substrate.

11. The semiconductor device according to claim 1, wherein the other side surface of the second trench does not contact the first hole isolation region, and The other side surface of the third trench does not contact the second hole isolation region.

12. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a semiconductor substrate of a first conductivity type, the semiconductor substrate having an upper surface and a lower surface opposite to the upper surface; (b) forming a first hole isolation region of the first conductivity type and a second hole isolation region of the first conductivity type on the upper surface of the semiconductor substrate; (c) after step (b), forming a first trench and a second trench inside the semiconductor substrate so that the first hole isolation region is sandwiched between the first trench and the second trench in a plan view, and forming a third trench inside the semiconductor substrate so that the second hole isolation region is sandwiched between the third trench itself and the first trench in a plan view; (d) after step (c), forming a first insulating film inside the first trench, forming a second insulating film inside the second trench, and forming a third insulating film inside the third trench; (e) after step (d), forming a trench gate electrode inside the first trench through the first insulating film, forming a first trench emitter electrode inside the second trench through the second insulating film, and forming a second trench emitter electrode inside the third trench through the third insulating film; (f) after step (e), forming a first base region of a second conductivity type opposite to the first conductivity type inside the first hole isolation region, forming a second base region of the second conductivity type inside the second hole isolation region, forming a first floating region of the second conductivity type inside the semiconductor substrate, the first floating region being located on the other side surface side of the two side surfaces of the second trench opposite to the one side surface on which the first hole isolation region is formed, and forming a second floating region of the second conductivity type inside the semiconductor substrate, the second floating region being located on the other side surface side of the two side surfaces of the third trench opposite to the one side surface on which the second hole isolation region is formed; and (g) after step (f), forming a first emitter region of the first conductivity type inside the first base region, and forming a second emitter region of the first conductivity type inside the second base region, Wherein each depth of the first floating region and the second floating region from the upper surface of the semiconductor substrate is shallower than each depth of the first trench, the second trench and the third trench from the upper surface of the semiconductor substrate, and is deeper than each depth of the first base region and the second base region from the upper surface of the semiconductor substrate.

13. The method for manufacturing a semiconductor device according to claim 12, Wherein each impurity concentration of the first floating region and the second floating region is higher than each impurity concentration of the first base region and the second base region.

14. The method for manufacturing a semiconductor device according to claim 11, further comprising the following steps: (h) performing a heat treatment between the step (b) and the step (c), wherein the first hole isolation region and the second hole isolation region are diffused by the heat treatment, and Wherein, after step (c), each depth of the first hole isolation region and the second hole isolation region from the upper surface of the semiconductor substrate is deeper than each depth of the first trench, the second trench and the third trench from the upper surface of the semiconductor substrate.

15. The method for manufacturing a semiconductor device according to claim 11, further comprising the following steps: (i) after step (g), forming an interlayer insulating film on the upper surface of the semiconductor substrate to cover the first trench, the second trench and the third trench; (j) after the step (i), forming a first hole penetrating the interlayer insulating film and reaching the first trench emitter electrode, the first base region, and the first emitter region, and forming a second hole penetrating the interlayer insulating film and reaching the second trench emitter electrode, the second base region, and the second emitter region; (k) after the step (i), forming a third hole penetrating the interlayer insulating film and reaching the trench gate electrode; (l) after step (k), forming a first plug inside the first cavity, forming a second plug inside the second cavity, and forming a third plug inside the third cavity; as well as (m) after the step (l), forming an emitter wiring and a gate wiring on the interlayer insulating film, wherein the first trench emitter electrode, the first base region, and the first emitter region are electrically connected to the emitter wiring through the first plug, wherein the second trench emitter electrode, the second base region, and the second emitter region are electrically connected to the emitter wiring through the second plug, wherein the trench gate electrode is electrically connected to the gate wiring through the third plug, and Each of the first floating region and the second floating region is in an electrically floating state.

16. A semiconductor device comprising a plurality of IGBT units, Each of the plurality of units comprises: A trench gate electrode, a first trench emitter electrode, and a second trench emitter electrode are formed in an n-type semiconductor substrate; A p-type first base region is formed inside the semiconductor substrate, and the p-type first base region is located between the trench gate electrode and the first trench emitter electrode; and The p-type second base region is formed inside the semiconductor substrate, and the p-type second base region is located between the trench gate electrode and the second trench emitter electrode. wherein the p-type floating region is formed inside the semiconductor substrate between the plurality of cells, and The depth of the floating region is shallower than each of the depths of the trench gate electrode, the first trench emitter electrode, and the second trench emitter electrode, and is deeper than each of the depths of the first base region and the second base region.

17. The semiconductor device according to claim 16, Each of the plurality of units further comprises: An n-type first emitter region is formed inside the first base region; The n-type second emitter region is formed inside the second base region; The n-type first hole isolation region is formed inside the semiconductor substrate, and the first hole isolation region is located between the trench gate electrode and the first trench emitter electrode; and The n-type second hole isolation region is formed inside the semiconductor substrate, and the second hole isolation region is located between the trench gate electrode and the second trench emitter electrode. wherein the first base region is formed inside the first hole isolation region, wherein the second base region is formed inside the second hole isolation region, wherein each impurity concentration of the first hole isolation region and the second hole isolation region is higher than the impurity concentration of the semiconductor substrate, wherein the first base region forms a pn junction with the first emitter region and the first hole isolation region, wherein the second base region forms a pn junction with the second emitter region and the second hole isolation region, and The floating region forms a pn junction with the semiconductor substrate.

18. The semiconductor device according to claim 17, The impurity concentration of the floating region is higher than each of the impurity concentrations of the first base region and the second base region.

19. The semiconductor device according to claim 17, further comprising: an interlayer insulating film formed on the semiconductor substrate to cover the trench gate electrode, the first trench emitter electrode and the second trench emitter electrode; a first hole that penetrates the interlayer insulating film and reaches the first trench emitter electrode, the first base region, and the first emitter region; second holes that penetrate the interlayer insulating film and reach the second trench emitter electrode, the second base region, and the second emitter region; a third hole that penetrates the interlayer insulating film and reaches the trench gate electrode; a first plug formed inside the first cavity; a second plug formed inside the second cavity; A third plug formed inside the third cavity; and An emitter wiring and a gate wiring are formed on the interlayer insulating film, wherein the first trench emitter electrode, the first base region, and the first emitter region are electrically connected to the emitter wiring through the first plug, wherein the second trench emitter electrode, the second base region, and the second emitter region are electrically connected to the emitter wiring through the second plug, wherein the trench gate electrode is electrically connected to the gate wiring through the third plug, and Each of the first floating region and the second floating region is in an electrically floating state.

20. The semiconductor device according to claim 16, The trench gate electrode, the first trench emitter electrode, and the second trench emitter electrode included in each of the plurality of cells are formed at the same pitch.

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