Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a charge storage layer on the substrate; forming a gate structure on the charge storage layer; forming a source electrode and a drain electrode in the substrate at two sides of the gate structure; and carrying out hot carrier injection treatment on the charge storage layer to enable electrons or holes to enter the charge storage layer. According to the forming method provided by the embodiment of the invention, the carrier transport channel can be far away from the surface of the substrate, the influence of a substrate bonding interface on the channel carrier is reduced, the mobility of the channel carrier is improved, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to the smaller feature size, the channel length of semiconductor devices is also continuously shortened accordingly.

[0003] The semiconductor structure includes a substrate, a gate structure located on the substrate, and source-drain doped layers located in the substrate on both sides of the gate structure. As the channel length continues to shorten, the gate dielectric layer of the gate structure is easily broken down, and the semiconductor device is prone to leakage and other problems.

[0004] Therefore, the performance of current semiconductor structures still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the efficiency of carrier migration, reduce device leakage, and improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a charge storage layer on the substrate; forming a gate structure on the charge storage layer; forming a source and a drain in the substrate on both sides of the gate structure; and performing hot carrier injection treatment on the charge storage layer to allow electrons or holes to enter the charge storage layer.

[0007] Optionally, the material of the charge storage layer includes silicon nitride or nitrogen-doped silicon carbide.

[0008] Optionally, the method for performing hot carrier injection treatment on the charge storage layer includes: the method for performing hot carrier injection treatment on the charge storage layer includes: applying different voltages to the gate structure, the source, the drain and the substrate to form an electric field force, and the electric field force causes electrons or holes to enter the charge storage layer.

[0009] Optionally, the substrate is a P-type substrate, and a hot carrier injection process is performed on the charge storage layer to allow electrons to enter the charge storage layer.

[0010] A first voltage is applied to the gate structure, where the first voltage is equal to a first preset multiple of a positive power supply voltage; and a second voltage is applied to the drain, where the second voltage is equal to a second preset multiple of the positive power supply voltage.

[0011] Optionally, the substrate is an N-type substrate, and a hot carrier injection process is performed on the charge storage layer to allow holes to enter the charge storage layer.

[0012] A first voltage is applied to the gate structure, where the first voltage is equal to a negative power supply voltage of a first preset multiple; and a second voltage is applied to the drain, where the second voltage is equal to a negative power supply voltage of a second preset multiple.

[0013] The value of the first preset multiple is 1 to 1.5, and the value of the second preset multiple is 1.1 to 1.5.

[0014] Optionally, the gate structure includes a gate dielectric layer located on the charge storage layer, and a gate layer located on the gate dielectric layer.

[0015] Optionally, a method of forming the charge storage layer and the gate dielectric layer includes chemical vapor deposition or atomic layer deposition.

[0016] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above-mentioned formation method, comprising: a substrate; a charge storage layer, the charge storage layer is located on the substrate, and electrons or holes are stored in the charge storage layer; a gate structure, the gate structure is located on the charge storage layer; a source and a drain, the source and the drain are respectively located in the substrate on both sides of the gate structure.

[0017] Optionally, the substrate is a P-type substrate, and electrons are stored in the charge storage layer.

[0018] Optionally, the substrate is an N-type substrate, and holes are stored in the charge storage layer.

[0019] Optionally, the material of the charge storage layer includes silicon nitride or nitrogen-doped silicon carbide.

[0020] Optionally, the gate structure includes a gate dielectric layer located on the charge storage layer, and a gate layer located on the gate dielectric layer.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] The formation method provided by the technical solution forms a charge storage layer on a substrate, and through hot carrier injection treatment, electrons or holes are injected into the charge storage layer according to the type of semiconductor device. The electrons or holes in the charge storage layer generate electrostatic repulsion on the channel carriers in the substrate. The electrostatic repulsion is utilized to keep the carrier transport channel away from the junction between the substrate and the charge storage layer, thereby reducing the influence of the junction on the carrier transport channel and improving the carrier mobility. In addition, a charge storage layer is added between the gate structure and the substrate, which can reduce the occurrence of leakage, and is beneficial to improving the performance of the finally formed semiconductor device.

[0023] The semiconductor structure provided by the technical solution has a charge storage layer between the substrate and the gate structure. Depending on the type of semiconductor device, the carriers stored in the charge storage layer are electrons or holes. The charge storage layer will generate electrostatic repulsion on the channel carriers in the substrate. The electrostatic repulsion is used to push the channel carriers away from the substrate surface, thereby reducing the adverse effects of the interface between the substrate and the charge storage layer on the channel carrier transport, improving the carrier mobility, and improving the source-drain conduction current of the device; and the channel layer is far away from the gate structure, which is beneficial to improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 4 is a schematic structural diagram of a semiconductor forming process in one embodiment of the present invention;

[0025] Figure 5 It is a schematic structural diagram of applying voltage to a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0026] As described in the background technology, with the development of semiconductor technology, the characteristic size of semiconductor devices continues to decrease, the distance between the source and drain is also shortened accordingly, and the thickness of the gate dielectric layer of the gate structure is gradually thinner, which makes the device prone to leakage and has an adverse effect on the performance of the device.

[0027] At present, the commonly used material for the gate dielectric layer is silicon dioxide. Although silicon dioxide has good bonding with the substrate and forms fewer interface defects, the dielectric constant of silicon dioxide is low. As the gate dielectric layer becomes thinner, leakage and other situations are prone to occur. In order to reduce the leakage of devices, high-k dielectric materials with high dielectric constants or materials such as silicon nitride are used as gate dielectric layers. However, high-k dielectric materials and silicon nitride have poor interface compatibility with the substrate, resulting in poor interface performance and more defects between the gate dielectric layer and the substrate, which affects the mobility of channel carriers in the substrate and further affects the performance of semiconductor devices.

[0028] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, wherein a charge storage layer is formed on a substrate, and after the charge storage layer is treated with hot carrier injection, electrons or holes enter the charge storage layer, making the charge storage layer positively or negatively charged, and the charges in the charge storage layer have an electrostatic repulsive force on the channel carriers in the substrate. Under the action of the electrostatic repulsion, the channel carriers in the substrate will move away from the substrate surface, thereby reducing the adverse effects of interface defects between the substrate and the charge storage layer on the transport of channel carriers, and improving the carrier mobility; and, the charge storage layer is increased, and at the same time, the channel carriers are away from the gate dielectric layer of the gate structure, thereby reducing the possibility of the gate dielectric layer being broken down, and improving the reliability of the gate dielectric layer and the performance of the semiconductor structure.

[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 1 to 4 is a schematic structural diagram of a semiconductor forming process in one embodiment of the present invention; Figure 5 It is a schematic structural diagram of applying voltage to a semiconductor structure in one embodiment of the present invention.

[0031] refer to Figure 1 , providing a substrate 100.

[0032] The substrate 100 is one of monocrystalline silicon, polycrystalline silicon, amorphous silicon or silicon on insulator; the substrate 100 may also be a Si substrate, a Ge substrate, a GeSi substrate or a GaAs substrate. In this embodiment, the substrate 100 is a Si substrate.

[0033] The substrate 100 may be an N-type substrate or a P-type substrate.

[0034] In this embodiment, the formed semiconductor structure is an NMOS device, and the substrate 100 is a P-type substrate.

[0035] In other embodiments, a PMOS device is formed using an N-type substrate.

[0036] refer to Figure 2 , a charge storage layer 101 is formed on the substrate 100 .

[0037] In this embodiment, a charge storage layer 101 is first formed on the substrate 100 , and then a gate dielectric layer is formed on the charge storage layer 101 .

[0038] In this embodiment, the method for forming the charge storage layer 101 includes: forming a charge storage material layer (not shown) on the substrate 100 ; and patterning the charge storage material layer to form the charge storage layer 101 on the substrate 100 .

[0039] In this embodiment, a charge storage material layer is formed on the substrate 100 by chemical vapor deposition; in other embodiments, an atomic layer deposition method may also be used to form the charge storage material layer on the substrate 100.

[0040] In this embodiment, the material of the charge storage layer 101 is silicon nitride. The reason for using silicon nitride is that, firstly, silicon nitride has a high dielectric constant of 6 to 9, is an ideal dielectric material, and has excellent insulation properties. The silicon nitride layer is located between the gate structure and the substrate 100 to be formed subsequently, which can reduce the occurrence of device leakage and improve device reliability. Secondly, the silicon nitride material itself has a large number of defects such as vacancies, which can be used as a charge storage medium, which is conducive to capturing and storing charges during the subsequent hot carrier injection process, thereby forming an electrostatic repulsion force between the charge storage layer and the carriers in the substrate.

[0041] In other embodiments, nitrogen-doped silicon carbide may also be used as the charge storage layer.

[0042] The thickness of the charge storage layer 101 is 5 angstroms to 100 angstroms. With this thickness, the charge storage layer 101 can, on the one hand, capture sufficient charges to generate a strong electrostatic repulsion force on the channel carriers in the substrate 100, and can prevent the carriers captured by the charge storage layer 101 from entering the gate dielectric layer 102 formed subsequently. On the other hand, the device conduction speed will not be slowed down due to the thickness of the charge storage layer 101 being too thick.

[0043] refer to Figure 3 , a gate dielectric layer 102 is formed on the charge storage layer 101 .

[0044] In this embodiment, the method for forming the gate dielectric layer 102 includes: forming a gate dielectric material layer (not shown) on the charge storage layer 101 ; and patterning the gate dielectric material layer to form the gate dielectric layer 102 on the charge storage layer 101 .

[0045] In other embodiments, a charge storage material layer may be formed on the substrate 100, and a gate dielectric material layer may be formed on the charge storage material layer; the gate dielectric material layer and the charge storage layer may be graphically processed to form a charge storage layer 101 and a gate dielectric layer 102 located on the charge storage layer 101 on the substrate 100.

[0046] In this embodiment, the gate dielectric material layer is formed by chemical vapor deposition process; in other embodiments, the gate dielectric material layer may also be formed by atomic layer deposition method.

[0047] In this embodiment, the gate dielectric layer 102 is made of silicon dioxide, which can increase the bonding force between the silicon nitride layer and the subsequently formed gate layer, and improve the performance of the bonding interface between the silicon nitride layer and the gate layer.

[0048] Continue to refer Figure 3 After forming the gate dielectric layer 102 , a gate layer 103 is formed on the gate dielectric layer 102 .

[0049] In this embodiment, the method for forming the gate layer 103 includes: forming a gate material layer (not shown) on the gate dielectric layer 102 , wherein the gate material layer also covers the surface of the substrate 100 ; and patterning the gate material layer to form the gate layer 103 on the gate dielectric layer 102 .

[0050] In this embodiment, the gate structure includes a gate dielectric layer 102 and a gate layer 103 located on the gate dielectric layer 102 .

[0051] In this embodiment, the material of the gate layer 103 is polysilicon.

[0052] In this embodiment, sidewall spacers 104 are formed on both sides of the gate layer 103 and the gate dielectric layer 102 .

[0053] The material of the sidewall spacer 104 includes one or more of silicon nitride, silicon oxide and silicon oxynitride. In this embodiment, the material of the sidewall spacer 104 is silicon nitride.

[0054] refer to Figure 4 After forming the sidewall 104 , the method further includes forming a source 105 and a drain 106 in the substrate 100 on both sides of the gate layer 103 .

[0055] In this embodiment, the doping ions of the source 105 and the drain 106 are N-type ions, such as P, As or Sb. In other embodiments, the doping ions of the source 105 and the drain 106 may also be P-type ions, which may be determined according to the type of semiconductor device.

[0056] After the source electrode 105 and the drain electrode 106 are formed, a hot carrier injection process is performed on the charge storage layer 101 , so that electrons or holes enter the charge storage layer 101 and are captured by the charge storage layer 101 .

[0057] In this embodiment, different voltages are applied to the gate layer 103 , the source 105 , the drain 106 and the substrate 100 to generate an electric field force, and the electric field force performs a hot carrier injection process on the charge storage layer 101 .

[0058] refer to Figure 5, a first voltage V is applied to the gate structure, specifically to the gate layer 103 gs , a second voltage V is applied to the drain 106 ds , apply voltage V to the source s , and applying a voltage V to the substrate 100 sub .

[0059] In this embodiment, the polarity of the voltage applied to the gate layer 103 and the drain electrode 106 is the same.

[0060] In this embodiment, taking the NMOS device as an example, the substrate 100 is a P-type substrate, the source 105 and the drain 106 are N-type doped, and an appropriate voltage is applied to the drain 106, and a transverse electric field is generated in the channel region. The electrons in the substrate 100 are accelerated under the action of the transverse electric field to form high-energy carriers. The high-energy carriers collide with the silicon lattice to generate ionized electron-hole pairs. At this time, the electrons have sufficiently high energy, and the voltage applied to the gate layer 103 generates a longitudinal electric field. Under the action of the longitudinal electric field, the electrons overcome the interface potential between the substrate 100 and the charge storage layer 101, are injected into the charge storage layer 101, and are captured by defects in the charge storage layer 101.

[0061] In this embodiment, the first voltage V gs A positive power supply voltage V dd , the second voltage V ds A positive power supply voltage V dd , the source 105 and the substrate 100 are grounded.

[0062] In this embodiment, the first voltage V gs and the second voltage V ds are all smaller than the breakdown voltage of the formed semiconductor device.

[0063] In this embodiment, the power supply voltage V dd It is the operating voltage when the formed semiconductor device is working.

[0064] The first preset multiple is 1 to 1.5, and the second preset multiple is 1.1 to 1.5. Using this voltage range can accelerate the generation of hot carriers and the process of hot carrier injection, and the breakdown voltage of the semiconductor device is not reached to avoid damage to the semiconductor device.

[0065] In this embodiment, the first voltage V gs Equal to the power supply voltage V dd , the second voltage V ds Equal to 1.1 times the power supply voltage V dd .

[0066] In this embodiment, the first voltage V is applied gs and the second voltage V ds The time is the same, which can make the electron injection sufficient and make the charge storage layer 101 store charges to saturation, thereby having a stronger electrostatic repulsion effect.

[0067] In this embodiment, the substrate current is detected to determine whether the charge in the charge storage layer 101 is saturated. During the hot carrier injection process, the substrate current will increase. When the detected substrate current tends to be stable, the carrier injection of the charge storage layer 101 reaches saturation, and the voltage applied to the gate layer 103, the source 105, the drain 106 and the substrate 100 can be stopped.

[0068] In this embodiment, in the NMOS device, hot carrier injection processing allows electrons to enter the charge storage layer 101, so that the charge storage layer 101 is negatively charged. The NMOS device has an N-type channel, and the channel carriers are electrons. The polarity of the charge storage layer 101 is consistent with the polarity of the channel carriers, which can produce an electrostatic repulsion effect on the channel carriers. Under the electrostatic repulsion force, the channel carriers move away from the surface of the substrate 100. The channel carriers are transported deep away from the surface of the substrate 100, and the influence of the interface between the substrate 100 and the charge storage layer 101 becomes smaller, and the carrier mobility is increased, which is beneficial to improving the performance of the semiconductor device.

[0069] It should be noted that when a forward voltage is applied to the gate layer 103, the electrons in the substrate 100 are affected by the longitudinal electric field and gather near the surface of the substrate 100. The position of the channel carriers when the attraction of the gate voltage on the electrons and the repulsion of the charges in the charge storage layer 101 on the electrons reach a balance is the position of the channel region when the semiconductor device is turned on.

[0070] In another embodiment, in a PMOS device, the substrate 100 is an N-type substrate, the source 105 and the drain 106 are P-type doped, and when an appropriate voltage is applied to the drain 106 and the gate layer 103, holes enter the charge storage layer 101, making the charge storage layer 101 positively charged, thereby generating an electrostatic repulsion effect on the carriers of the P-type channel.

[0071] In a PMOS device, the first voltage V gs A negative power supply voltage V dd , the second voltage V ds The negative power supply voltage V is equal to the second preset multiple dd , the source 105 and the substrate 100 are grounded.

[0072] The value of the first preset multiple is 1 to 1.5, and the value of the second preset multiple is 1.1 to 1.5.

[0073] refer to Figure 4 Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate 100; a charge storage layer 101, wherein the charge storage layer 101 is located on the substrate 100, and wherein electrons or holes are stored in the charge storage layer 101; a gate structure, wherein the gate structure is located on the charge storage layer 101; a source 105 and a drain 106, wherein the source 105 and the drain 106 are respectively located in the substrate 100 on both sides of the gate structure.

[0074] In this embodiment, the gate structure includes a gate dielectric layer 102 located on the charge storage layer 101 , and a gate layer 103 located on the gate dielectric layer 102 .

[0075] In this embodiment, the substrate 100 is a P-type substrate, and electrons are stored in the charge storage layer 101 .

[0076] In other embodiments, the substrate 100 is an N-type substrate, and holes are stored in the charge storage layer 101 .

[0077] In this embodiment, the material of the charge storage layer 101 is silicon nitride.

[0078] In other embodiments, nitrogen-doped silicon carbide may also be used as the charge storage layer.

[0079] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a charge storage layer on the substrate; forming a gate structure on the charge storage layer; forming a source and a drain in the substrate on both sides of the gate structure; The charge storage layer is subjected to hot carrier injection treatment to allow electrons or holes to enter the charge storage layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the charge storage layer includes silicon nitride or nitrogen-doped silicon carbide.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for performing hot carrier injection treatment on the charge storage layer comprises: applying different voltages to the gate structure, the source, the drain and the substrate to form an electric field force, wherein the electric field force causes electrons or holes to enter the charge storage layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The substrate is a P-type substrate, and a hot carrier injection process is performed on the charge storage layer to allow electrons to enter the charge storage layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: A first voltage is applied to the gate structure, where the first voltage is equal to a first preset multiple of a positive power supply voltage; and a second voltage is applied to the drain, where the second voltage is equal to a second preset multiple of the positive power supply voltage.

6. The method for forming a semiconductor structure according to claim 3, wherein: The substrate is an N-type substrate, and a hot carrier injection process is performed on the charge storage layer to allow holes to enter the charge storage layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: A first voltage is applied to the gate structure, where the first voltage is equal to a negative power supply voltage of a first preset multiple; and a second voltage is applied to the drain, where the second voltage is equal to a negative power supply voltage of a second preset multiple.

8. The method for forming a semiconductor structure according to claim 5 or 7, characterized in that: The value of the first preset multiple is 1 to 1.5, and the value of the second preset multiple is 1.1 to 1.

5.

9. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure includes a gate dielectric layer located on the charge storage layer, and a gate layer located on the gate dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method of forming the charge storage layer and the gate dielectric layer includes chemical vapor deposition or atomic layer deposition.

11. A semiconductor structure, characterized in that: include: substrate; A charge storage layer, the charge storage layer is located on the substrate, and electrons or holes are stored in the charge storage layer; a gate structure, the gate structure being located on the charge storage layer; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located in the substrate at two sides of the gate structure.

12. The semiconductor structure according to claim 11, wherein: The substrate is a P-type substrate, and electrons are stored in the charge storage layer.

13. The semiconductor structure according to claim 11, wherein: The substrate is an N-type substrate, and holes are stored in the charge storage layer.

14. The semiconductor structure according to claim 11, wherein: The material of the charge storage layer includes silicon nitride or nitrogen-doped silicon carbide.

15. The semiconductor structure according to claim 11, wherein: The gate structure includes a gate dielectric layer located on the charge storage layer, and a gate layer located on the gate dielectric layer.

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