Solid-state imaging device, method for manufacturing solid-state imaging device, imaging apparatus, and electronic apparatus

Abstract

The present invention relates to a back-irradiation-type solid-state imaging device, a method for manufacturing the back-irradiation-type solid-state imaging device, an imaging apparatus, and an electronic apparatus capable of reducing manufacturing cost. The memory circuit and the logic circuit, which have been singulated, are horizontally arranged, embedded with an oxide film to be planarized, and stacked so as to be included in the planar direction below the solid-state imaging element. The present invention can be applied to an imaging device.

Description

[0001] This application is a divisional application of patent application No. 201880068715.7, whose application date is October 16, 2018 and whose invention name is "Back-illuminated solid-state imaging device, method for manufacturing back-illuminated solid-state imaging device, imaging device and electronic device". Technical Field

[0002] The present invention relates to a back-illuminated solid-state imaging device, a method for manufacturing a back-illuminated solid-state imaging device, an imaging device and an electronic device, and in particular, to a back-illuminated solid-state imaging device, a method for manufacturing a back-illuminated solid-state imaging device, an imaging device and an electronic device capable of reducing manufacturing costs. Background Art

[0003] Solid-state imaging devices achieve high image quality in the form of HD, 4k×2k super HD, and super slow motion functions while increasing the number of pixels and achieving high frame rates and high grayscale.

[0004] Since the transmission rate is calculated by the number of pixels × frame rate × grayscale, for example, in the case of 4k×2k=8M pixels, 240f / s frame rate and 14-bit grayscale, the transmission rate is 8M×240f / s×14bit=26Gbps.

[0005] After signal processing is performed at the next stage of the solid-state imaging element, since RGB signals of color coordinates are output, high-speed transmission of 26G×3=78Gbps is required.

[0006] If high-speed transmission is performed with a small number of connection terminals, the signal rate of each connection terminal becomes higher, and the difficulty of impedance matching of the high-speed transmission path becomes greater. In addition, since not only the clock frequency increases but also the loss increases, power consumption increases.

[0007] To avoid this, it is sufficient to increase the number of connection terminals so that the transmission is divided to reduce the signal rate. However, since the terminals required for the connection between the solid-state imaging element and the signal processing circuit or storage circuit of the next stage are arranged, the increase in the number of connection terminals increases the package size of each circuit.

[0008] Furthermore, as a substrate for electric wiring required for a signal processing circuit or a memory circuit at the next stage, a substrate with a finer wiring density based on stacked wiring is required, which further increases the length of the wiring path. At the same time, power consumption increases.

[0009] If the package size of each circuit becomes larger, the size of the substrate itself used for mounting also becomes larger, and the configuration of the imaging device itself on which the solid-state imaging element is mounted eventually becomes larger.

[0010] Therefore, as a technology for constructing a miniaturized camera device, the following technology has been proposed, by which a solid-state camera element and a circuit such as a signal processing circuit or a storage circuit are stacked by stacking wafers (WoW: Wafer on Wafer), which is used to connect the circuit in the form of a wafer (see Patent Document 1).

[0011] By using the stacking technology of WoW, since semiconductors can be connected by many fine wirings, the transmission speed of each wiring becomes low and power consumption can be suppressed.

[0012] Reference List

[0013] Patent Literature

[0014] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-099582 Summary of the invention

[0015] Technical Problems to be Solved by the Invention

[0016] However, in the case of WoW, if the chips of the wafers to be stacked have the same size, there is no problem. However, if the sizes of the chips constructed as wafers are different from each other, the size must be adjusted to the size of the largest chip, the theoretical yield of each circuit decreases and the cost increases.

[0017] In addition, regarding the yield of each wafer to be stacked, because of the defects of the chips of each wafer, the chips of the stacked wafers will also be regarded as defects, and since the yield of the wafers in the entire stacked layer is given by the product (multiplication) of the yield of each wafer, the yield decreases and the cost increases.

[0018] In addition, a technology has been proposed in which chips are connected to each other by forming small bumps on chips of different sizes. In this case, since the chips selected as good products and having different sizes are connected by bumps, the difference in theoretical yield between wafers and the influence of chip yield are small.

[0019] However, since it is difficult to form small bumps and the connection pitch is limited, it is not possible to obtain a larger number of connection terminals than WoW. In addition, since the connection is performed by the mounting process, if the number of connection terminals increases, the cost increases due to the decrease in yield caused by the connection. In addition, since each wiring is also connected in the mounting process, the connection takes a long time and the process cost increases.

[0020] The present invention has been made in view of such circumstances as described above, and in particular, the present invention can reduce the manufacturing cost of a solid-state imaging device.

[0021] Technical solutions to technical problems

[0022] A solid-state imaging element according to one aspect of the present invention is a back-illuminated solid-state imaging device, comprising: a first semiconductor element, which includes an imaging element configured to generate a pixel signal in units of pixels; a second semiconductor element, in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component; and wiring, which electrically connects the first semiconductor element and the second semiconductor element, and the first semiconductor element and the second semiconductor element are stacked by oxide film bonding.

[0023] The first semiconductor element may be larger than the second semiconductor element.

[0024] The first semiconductor element may be smaller than the second semiconductor element.

[0025] The back-illuminated solid-state imaging device may be configured such that the signal processing circuit includes a first signal processing circuit and a second signal processing circuit, and the first signal processing circuit and the second signal processing circuit are arranged in parallel in a horizontal direction and embedded by the embedding member.

[0026] The back-illuminated solid-state imaging device can be constructed so that the signal processing circuit includes a first signal processing circuit and a second signal processing circuit, the wiring includes a first wiring and a second wiring, in the second semiconductor element, the first signal processing circuit is embedded by the embedded component, the solid-state imaging device includes a third semiconductor element, in the third semiconductor element, the second signal processing circuit is embedded by the embedded component, the first wiring electrically connects the first semiconductor element and the second semiconductor element to each other, the second wiring electrically connects the second semiconductor element and the third semiconductor element to each other, and the second semiconductor element and the third semiconductor element are stacked by oxide film bonding.

[0027] The wiring may be bonded by CuCu bonding.

[0028] The wirings may be electrically connected via through-holes.

[0029] The wiring may be electrically connected via a through hole formed from the imaging surface side of the imaging element.

[0030] The wiring may be electrically connected via a through hole formed from a surface on the opposite side to the imaging surface of the imaging element.

[0031] The embedded member may include an oxide film.

[0032] The embedded member may include an organic material.

[0033] The back-illuminated solid-state imaging device may be configured such that, in the second semiconductor element, the signal processing circuits are laid out in such a manner as to minimize gaps between the signal processing circuits, and the signal processing circuits are embedded in the embedding member containing the organic material.

[0034] In the second semiconductor element, in addition to the signal processing circuit, a dummy circuit may be embedded by the embedding member, the dummy circuit being constituted by a semiconductor element and including a dummy line.

[0035] On a surface of the second semiconductor element opposite to a surface on which the first semiconductor element is stacked, a heat dissipation member including a member having a thermal conductivity higher than a predetermined thermal conductivity and used to dissipate heat may be stacked.

[0036] The heat dissipation member may include SiC, AlN, SIN, Cu, Al, or C.

[0037] The heat dissipating member may include a water path for circulating cooling water.

[0038] The signal processing circuit may include a logic circuit, a storage circuit, a power supply circuit, an image signal compression circuit, a clock circuit, and an optical communication conversion circuit.

[0039] The signal processing circuit may be embedded in the first semiconductor element via the embedding member.

[0040] After the signal processing circuit is brought into contact with the first semiconductor element in a positioned state at a portion thereof and is gradually joined to the first semiconductor element from a peripheral portion of the contact portion, the signal processing circuit may be respectively embedded by the embedding member.

[0041] The portion thereof may include end edges and end points of the signal processing circuit.

[0042] The signal processing circuit may be smaller than the first semiconductor element.

[0043] After the signal processing circuit is brought into contact with the second semiconductor element in a positioned state at a portion thereof and is gradually joined to the second semiconductor element from a peripheral portion of the contact portion, the signal processing circuit may be respectively embedded by the embedding member.

[0044] The portion thereof may include end edges and end points of the signal processing circuit.

[0045] A method for manufacturing a solid-state imaging device according to one aspect of the present invention is a method for manufacturing a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels; a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedding member; and wiring that electrically connects the first semiconductor element and the second semiconductor element, the first semiconductor element and the second semiconductor element being stacked by oxide film bonding. A first wafer and a second wafer are stacked by oxide film bonding in such a manner that the wiring between the first semiconductor element and the second semiconductor element is electrically connected, and then singulated, the first wafer including the imaging element formed by a semiconductor process, the signal processing circuit confirmed as a good product by electrical inspection among the signal processing circuits formed by the semiconductor process being further arranged in the second wafer, and the signal processing circuit is embedded by the embedding member.

[0046] An imaging device according to one aspect of the present invention is an imaging device including a back-illuminated solid-state imaging device, the solid-state imaging device including: a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels; a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component; and wiring that electrically connects the first semiconductor element and the second semiconductor element, the first semiconductor element and the second semiconductor element being stacked by being bonded by an oxide film.

[0047] An electronic device according to one aspect of the present invention is an electronic device including a back-illuminated solid-state imaging device, the solid-state imaging device including: a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels; a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component; and wiring that electrically connects the first semiconductor element and the second semiconductor element, the first semiconductor element and the second semiconductor element being stacked by being bonded by an oxide film.

[0048] According to one aspect of the present invention, the first semiconductor element includes an imaging element configured to generate a pixel signal in units of pixels, in the second semiconductor element, a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component, the first semiconductor element and the second semiconductor element are electrically connected by wiring, and the first semiconductor element and the second semiconductor element are stacked by oxide film bonding.

[0049] Effects of the Invention

[0050] According to one aspect of the present invention, it is possible to reduce the manufacturing cost of a solid-state imaging device in particular. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a graph illustrating the yield rate.

[0052] Figure 2 is a graph illustrating the reduction in theoretical yield.

[0053] Figure 3 is a diagram illustrating connection using a bump.

[0054] Figure 4 It is a diagram illustrating an outline of a method for manufacturing a solid-state imaging device according to the first embodiment of the present invention.

[0055] Figure 5 is a diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment of the present invention.

[0056] Figure 6 It's a picture. Figure 5 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0057] Figure 7 It's a picture. Figure 5 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0058] Figure 8 It's a picture. Figure 5 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0059] Fig. 9 It's a picture. Figure 5 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0060] Fig.10 It is a diagram illustrating an outline of a method for manufacturing a solid-state imaging device according to a second embodiment of the present invention.

[0061] Fig.11 is a diagram illustrating a configuration example of a solid-state imaging device according to a second embodiment of the present invention.

[0062] Fig.12 It's a picture. Fig.10 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0063] Fig.13 It's a picture. Fig.10 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0064] Fig.14 is a diagram illustrating a configuration example of a solid-state imaging device according to a third embodiment of the present invention.

[0065] Fig.15 It's a picture. Fig.14 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0066] Fig.16 It's a picture. Fig.14 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0067] Fig.17 is a diagram illustrating a configuration example of a solid-state imaging device according to a fourth embodiment of the present invention.

[0068] Fig.18 is a diagram illustrating a configuration example of a solid-state imaging device according to a fifth embodiment of the present invention.

[0069] Fig.19 It's a picture. Fig.18 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0070] Fig. 20 It's a picture. Fig.18 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0071] Fig.21 It's a picture. Fig.18 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0072] Fig. 22 It's a picture. Fig.18 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0073] Fig.23 is a diagram illustrating a configuration example of a solid-state imaging device as a modification example of the fifth embodiment of the present invention.

[0074] Fig.24 It is a diagram illustrating an outline of a method for manufacturing a solid-state imaging device according to a sixth embodiment of the present invention.

[0075] Fig.25 is a diagram illustrating a configuration example of a solid-state imaging device according to a sixth embodiment of the present invention.

[0076] Fig.26 It's a picture. Fig.25 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0077] Fig. 27 It's a picture. Fig.25 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0078] Fig.28 It's a picture. Fig.25 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0079] Fig.291 is a diagram illustrating a first connection example of a solid-state imaging element.

[0080] Fig.30 It's a picture. Fig.29 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0081] Fig.31 It's a picture. Fig.29 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0082] Fig.32 It's a picture. Fig.29 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0083] Fig.33 2 is a diagram illustrating a second connection example of the solid-state imaging element.

[0084] Fig.34 It's a picture. Fig.33 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0085] Fig.35 It's a picture. Fig.33 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0086] Fig.36 It's a picture. Fig.33 FIG. 1 is a diagram of a method for manufacturing a solid-state imaging device.

[0087] Fig.37 1 is a diagram illustrating a first modification of the connection example of the solid-state imaging element.

[0088] Fig.38 1 is a diagram illustrating a second modification of the connection example of the solid-state imaging element.

[0089] Fig.39 FIG. 1 is a diagram illustrating a third modification of the connection example of the solid-state imaging element.

[0090] Fig.40 1 is a diagram illustrating a fourth modification of the connection example of the solid-state imaging element.

[0091] Fig.41 FIG. 5 is a diagram illustrating a fifth modification of the connection example of the solid-state imaging element.

[0092] Fig.42 1 is a diagram illustrating a sixth modification of the connection example of the solid-state imaging element.

[0093] Fig.43 is a diagram illustrating a heat dissipation structure of a solid-state imaging device.

[0094] Fig.44 It is a diagram illustrating a method of manufacturing a solid-state imaging device.

[0095] Fig.45 1 is a diagram illustrating a first modification of the heat dissipation structure of the solid-state imaging device.

[0096] Fig.46 1 is a diagram illustrating a second modification of the heat dissipation structure of the solid-state imaging device.

[0097] Fig.47 1 is a diagram illustrating a third modification of the heat dissipation structure of the solid-state imaging device.

[0098] Fig.48 1 is a diagram illustrating a fourth modification of the heat dissipation structure of the solid-state imaging device.

[0099] Fig.49 : is a block diagram showing a configuration example of an imaging device of an electronic device as a configuration of an imaging device to which the present invention is applied.

[0100] Fig.50 This is a diagram illustrating a usage example of an imaging device to which the technology of the present invention is applied.

[0101] Fig.51 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0102] Fig.52 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU: camera control unit).

[0103] Fig.53 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0104] Fig.54 It is a diagram for assisting in explaining an example of the placement positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0105] Hereinafter, an embodiment for carrying out the present invention is described. Note that, in this specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and their repeated description is omitted.

[0106] The description is given in the following order.

[0107] 1. Summary of the Invention

[0108] 2. First embodiment

[0109] 3. Second embodiment

[0110] 4. Third embodiment

[0111] 5. Fourth embodiment

[0112] 6. Fifth embodiment

[0113] 7. Modification of the Fifth Embodiment

[0114] 8. Sixth embodiment

[0115] 9. Connection example of solid-state imaging element

[0116] 10. Modification of the connection example of the solid-state imaging element

[0117] 11. Heat dissipation structure

[0118] 12. Application examples of electronic equipment

[0119] 13. Example of using imaging element

[0120] 14. Application examples of endoscopic surgery systems

[0121] 15. Application examples of mobile objects

[0122] <<1. Overview of the present invention>>

[0123] The present invention reduces the manufacturing cost of a solid-state imaging device.

[0124] Here, before describing the present invention, WoW (Stacked Wafer) disclosed in Patent Document 1 is described.

[0125] For example, Figure 1 As shown, WoW is a technology for bonding and stacking a solid-state imaging device, a signal processing circuit, and a circuit including an IC such as a memory circuit, which are each in the form of a wafer.

[0126] Figure 1 WoW is schematically shown in which a wafer W1 formed with a plurality of solid-state imaging elements 11, a wafer W2 formed with a plurality of memory circuits 12, and a wafer W3 formed with a plurality of logic circuits 13 are bonded to each other and stacked in a state in which they are accurately positioned relative to each other.

[0127] By singulating the wafers stacked in this manner, for example Figure 2 The solid-state imaging device shown.

[0128] Figure 2 The solid-state imaging device 1 is structured such that an on-chip lens and on-chip color filter 10 , a solid-state imaging element 11 , a memory circuit 12 , a logic circuit 13 , and a supporting substrate 14 are stacked in this order from the top.

[0129] Here, by applying the WoW technique, the wiring 21 - 1 for electrically connecting the solid-state imaging element 11 and the memory circuit 12 and the wiring 21 - 2 for electrically connecting the memory circuit 12 and the logic circuit 13 can be connected at a fine pitch.

[0130] As a result, since the number of wirings can be increased, the transmission speed in the signal line can be lowered, and power saving can be expected.

[0131] However, since the areas required for the solid-state imaging element 11, the memory circuit 12, and the logic circuit 13 to be stacked are different from each other, a space Z1 where neither a circuit nor a wiring is formed appears on the left and right sides in the figure of the memory circuit 12 having an area smaller than that of the largest solid-state imaging element 11. Furthermore, a space Z2 where neither a circuit nor a wiring is formed appears on the left and right sides of the logic circuit having an area smaller than that of the memory circuit 12.

[0132] In particular, since the areas required for the solid-state imaging element 11, the storage circuit 12, and the logic circuit 13 are different from each other, and Figure 2 In the diagram, since they are stacked with reference to the solid-state imaging element 11 which requires the largest area, spaces Z1 and Z2 appear.

[0133] This reduces the theoretical yield associated with the manufacture of the solid-state imaging device 1 , and as a result, the cost required for the manufacture increases.

[0134] In addition, Figure 1 In FIG. 1 , defective elements in the solid-state imaging element 11, the storage circuit 12, and the logic circuit 13 formed on the wafers W1 to W3, respectively, are represented by filled cells. In particular, Figure 1 It is shown that two defective elements occur in each of the wafers W1 to W3.

[0135] like Figure 1 As shown in FIG. 1 , defective elements occurring in the solid-state imaging element 11, the memory circuit 12, and the logic circuit 13 formed on the wafers W1 to W3, respectively, are not necessarily formed at the same position. Figure 1 As shown, in the solid-state imaging device 1 formed of the stacked body, there are six defects indicated by cross marks in the wafer W1 applied to the solid-state imaging element 11 .

[0136] Therefore, among the six defective solid-state imaging devices 1, they are regarded as six defects even though at least two of the three parts of the solid-state imaging element 11, the storage circuit 12, and the logic circuit 13 are not defective. Therefore, even though two good yields are sufficient for each part, the good yield for each part becomes six, which is equal to the integration number multiplied by the number of wafers.

[0137] As a result, the yield rate of the solid-state imaging device 1 decreases and the manufacturing cost increases.

[0138] In addition, if Figure 3 As shown, it is conceivable to monolithically form the solid-state imaging element 11, the memory circuit 12, and the logic circuit 13 having chip sizes different from each other, selectively arrange only good products, and form small bumps to connect them.

[0139] exist Figure 3 In the solid-state imaging device 1, an on-chip lens and an on-chip color filter 10 and a solid-state imaging element 11 are stacked from above, and below them, a memory circuit 12 and a logic circuit 13 are stacked in the same layer, and below this layer, a support substrate 14 is provided and stacked. In addition, the solid-state imaging element 11 and the memory circuit 12 and the logic circuit 13 arranged in the same layer are electrically connected to each other through small bumps 31.

[0140] exist Figure 3 In the solid-state imaging device 1, chips of different sizes selected as good products are connected through the bumps 31, and the theoretical yield difference between wafers and the influence of reducing the chip yield rate are reduced.

[0141] However, it is difficult to form the small bump 31, and as Figure 3 As shown, since there is a limit to the reduction of the connection distance d2, when using WoW, the connection distance d2 cannot be less than Figure 2 The connection spacing d1.

[0142] Therefore, with the stacking of Figure 2 Compared with the solid-state imaging device 1, the bump stack chip Figure 3 The solid-state imaging device 1 cannot have a large number of connection terminals. Figure 3 In the solid-state imaging device 1, in the case of connection using bumps, if the number of connection terminals increases, since the connection terminals are bonded by a mounting process, the yield rate related to bonding decreases and the cost increases. In addition, since the connection of the bumps is performed by a separate work in the mounting process, each process takes a long time and the process cost also increases.

[0143] In summary, the imaging element of the present invention reduces manufacturing costs in terms of theoretical output, implementation costs and process costs.

[0144] <<2. First embodiment>>

[0145] Figure 4 WOW is a diagram illustrating a structure in which a plurality of wafers are stacked by the WoW technology applied when manufacturing the solid-state imaging device of the present invention.

[0146] When manufacturing the solid-state imaging device of the present invention, two wafers including wafer 101 and wafer 102 are stacked in a state where the wiring is precisely positioned relative to each other, wherein wafer 101 has multiple solid-state imaging elements (complementary metal oxide semiconductor (CMOS: Complementary Metal Oxide Semiconductor)) image sensors and charge coupled devices (CCD: Charge Coupled Device) 120 formed thereon, and on wafer 102, storage circuits 121 and logic circuits 122 are reconfigured.

[0147] The wafer 101 has a plurality of solid-state imaging elements 120 formed thereon by a semiconductor process.

[0148] On the wafer 102 , a plurality of memory circuits 121 are arranged. The memory circuits 121 are formed on the wafer 103 by a semiconductor process and separated into individual pieces. After that, the memory circuits 121 are electrically inspected and confirmed to be good chips.

[0149] On the wafer 102 , a plurality of logic circuits 122 are arranged. The logic circuits 122 are formed on the wafer 104 by a semiconductor process and separated into chips. After that, the logic circuits 122 are electrically inspected and confirmed to be good chips.

[0150] <Including through Figure 4 Example of a solid-state imaging device using WoW technology stacked wafers>

[0151] In passing Figure 4 After stacking a plurality of wafers in the WoW technology shown, the wafers are singulated to construct the solid-state imaging device 111 ( Figure 5 ).

[0152] The solid-state imaging device of the present invention has, for example, Figure 5 This structure is shown. It should be noted that Figure 5 , the upper stage is a side cross-sectional view, and the lower stage is a diagram illustrating the arrangement relationship in the horizontal direction when the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122 are viewed from above.

[0153] exist Figure 5 In the solid-state imaging device 111 in the upper section of the figure, an on-chip lens and an on-chip color filter 131 and a solid-state imaging element 120 are stacked from the top in the figure, and below them, a storage circuit 121 and a logic circuit 122 are arranged and stacked on the left and right in the same layer, and a support substrate 132 is formed below this layer. In other words, as Figure 5 As shown in the above paragraph, Figure 5The solid-state imaging device 111 has a semiconductor element layer E1 including a solid-state imaging element 120 having a wafer 101 , and a semiconductor element layer E2 formed on the wafer 102 and including a memory circuit 121 and a logic circuit 122 .

[0154] Among the terminals 120 a of the solid-state imaging element 120 , the terminal 120 a on the memory circuit 121 is electrically connected to the wiring 134 , and the wiring 134 is connected to the terminal 121 a of the memory circuit 121 by CuCu connection.

[0155] Furthermore, among the terminals 120 a of the solid-state imaging element 120 , the terminal 120 a on the logic circuit 122 is electrically connected to the wiring 134 , and the wiring 134 is connected to the terminal 122 a of the logic circuit 122 by CuCu connection.

[0156] The space around the memory circuit 121 and the logic circuit 122 in the semiconductor element layer E2 where the memory circuit 121 and the logic circuit 122 are formed is in a state filled with the oxide film 133. Therefore, in the semiconductor element layer E2, the memory circuit 121 and the logic circuit 122 are in a state embedded in the oxide film 133. In addition, an oxide film bonding layer 135 is formed on the boundary between the semiconductor element layer E1 where the solid-state imaging element 120 is formed and the semiconductor element layer E2 where the memory circuit 121 and the logic circuit 122 are formed, and the oxide film bonding layer 135 bonds the semiconductor element layer E1 and the semiconductor element layer E2 together by oxide film bonding. In addition, the oxide film bonding layer 135 formed between the semiconductor element layer E2 and the support substrate 132 bonds the semiconductor element layer E2 of the memory circuit 121 and the logic circuit 122 to the support substrate 132 by oxide film bonding.

[0157] In addition, if Figure 5 As shown in the lower section of FIG. 1 , when viewed from above, the memory circuit 121 and the logic circuit 122 are arranged so that they are included in the range including the uppermost solid-state imaging element 120. With this arrangement, in the layer of the memory circuit 121 and the logic circuit 122, free space other than the memory circuit 121 and the logic circuit 122 is reduced, and therefore, theoretical yield can be improved.

[0158] exist Figure 4 On the wafer 102, when each solid-state imaging device 111 is singulated, the memory circuit 121 and the logic circuit 122 are finely adjusted and reconfigured in such a manner that both are arranged within the range of the solid-state imaging element 120 when viewed from above.

[0159] < Figure 5 Method for manufacturing a solid-state imaging device>

[0160] Now, refer to Figures 6 to 9 describe Figure 5 A method for manufacturing a solid-state imaging device 111. Note that Figures 6 to 9 Side view of Figure 6 A to 6L show side cross-sectional views of the solid-state imaging device 111 .

[0161] In the first step, if Figure 6 Side view of Figure 6 As shown in FIG. 1A, after electrical inspection, the memory circuit 121 and the logic circuit 122 that have been confirmed as good products are reconfigured on the reconfiguration substrate 151 so that they have the following characteristics: Figure 5 The layout is shown in the lower section of FIG. 1. On the reconfiguration substrate 151, an adhesive 152 is applied, and the memory circuit 121 and the logic circuit 122 are reconfigured and fixed on the reconfiguration substrate 151 by the adhesive 152.

[0162] In the second step, if Figure 6 Side view of Figure 6 As shown in B, the side view cross section Figure 6 The storage circuit 121 and the logic circuit 122 shown in A are inverted so that their upper surfaces become lower surfaces, and an oxide film bonding layer 135 is formed on the supporting substrate 161 and the oxide film bonding layer 135 is bonded by oxide film bonding, and the supporting substrate 161 is flattened by the oxide film formed thereon.

[0163] In the third step, if Figure 6 Side view of Figure 6 As shown in C, the reconfigured substrate 151 and the adhesive 152 are debonded, peeled off, and removed.

[0164] In the fourth step, if Figure 7 Side view of Figure 6 As shown in FIG. 2D , the silicon layer of the memory circuit 121 and the logic circuit 122 located at the upper surface portion in the figure is thinned to a height A that has no effect on the performance of the device.

[0165] In the fifth step, if Figure 7 Side view of Figure 6 As shown in FIG. E, an oxide film 133 serving as an insulating film is formed to embed the chip including the reconfigured memory circuit 121 and logic circuit 122. At this time, the surface of the oxide film 133 is flattened at a height corresponding to the memory circuit 121 and the logic circuit 122.

[0166] In the sixth step, if Figure 7 Side view of Figure 6 As shown in FIG. 5F , an oxide film bonding layer 135 is formed on the planarized oxide film 133 , and the support substrate 171 is bonded to the oxide film 133 by oxide film bonding.

[0167] In the seventh step, if Figure 8 Side view of Figure 6 As shown in FIG. G, the support substrate 171 is removed by debonding or etching. Through the processing from the first step to the seventh step, the wafer 102 is placed in a completed state, in which the memory circuit 121 and the logic circuit 122 are formed in a manner as shown in FIG. Figure 5 The layout reconfiguration shown in the lower section is filled with an insulating film including an oxide film 133, and has an oxide film bonding layer 135 formed on the planarized uppermost surface.

[0168] In the eighth step, if Figure 8 Side view of Figure 6 As shown in FIG. 1H, wiring 134 for the terminal 121a of the memory circuit 121 and the terminal 122a of the logic circuit 122 is formed so as to be electrically connected to the solid-state imaging element 120.

[0169] In the ninth step, if Figure 8 Side view of Figure 6 As shown in FIG. 1 , positioning is performed so that the wiring 134 from the terminal 121a of the memory circuit 121 and the terminal 122a of the logic circuit 122 of the wafer 102 and the wiring 134 from the terminal 120a of the solid-state imaging element 120 of the wafer 101 are positioned in an appropriate relative relationship to each other.

[0170] In the tenth step, if Fig. 9 Side view of Figure 6 As shown in FIG. 1 , the wafers 101 and 102 are attached to each other by WoW so that the wiring 134 from the terminal 121a of the memory circuit 121 and the terminal 122a of the logic circuit 122 of the wafer 102 and the wiring 134 from the terminal 120a of the solid-state imaging element 120 of the wafer 101 are connected by CuCu bonding. By this process, the memory circuit 121 and the logic circuit 122 of the wafer 102 are placed in a state of being electrically connected to each solid-state imaging element 120 of the wafer 101.

[0171] In the eleventh step, if Fig. 9 Side view of Figure 6 As shown in K, the silicon layer which is the upper layer in the figure of the solid-state imaging element 120 is thinned.

[0172] In the twelfth step, if Fig. 9 Side view of Figure 6 As shown in FIG. 1L , an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120 and are singulated to form a solid-state imaging device 111 .

[0173] Through such steps as described above, the solid-state imaging device 111 including the first layer in which the solid-state imaging element 120 is formed and the second layer in which the memory circuit 121 and the logic circuit 122 are formed is manufactured.

[0174] By such a configuration as described above, since the circuit connection between the solid-state imaging element 120, the storage circuit 121, and the logic circuit 122 can be established by terminals formed with a wiring density of fine wiring using the same semiconductor photolithography technology as in WoW, the number of connection terminals can be increased, and the signal processing speed per wiring can be reduced. Therefore, a reduction in power consumption can be expected.

[0175] Furthermore, since the memory circuit 121 and the logic circuit 122 are connected only when they are good chips, defective wafers which are defects of WoW are reduced, and therefore, the occurrence of yield loss can be reduced.

[0176] Furthermore, unlike WoW, the size of the connected memory circuit 121 and logic circuit can be made as small as possible regardless of the chip size of the solid-state imaging element 120, and Figure 5 As shown in the lower section of , the memory circuit 121 and the logic circuit can be arranged into independent islands, respectively, thereby improving the theoretical yield of the connected memory circuit 121 and the logic circuit 122.

[0177] In this regard, since the solid-state imaging element 120 requires a minimum pixel size necessary for reacting to optical light, the manufacturing process of the solid-state imaging element 120 does not necessarily require a fine wiring process, and therefore, the process cost can be reduced. In addition, if the manufacturing process of the logic circuit 122 uses the most advanced fine wiring process, power consumption can be reduced. In addition, the theoretical yield of the memory circuit 121 and the logic circuit 122 can be increased. As a result, the cost required to manufacture the solid-state imaging device 111 can be reduced.

[0178] In addition, since the solid-state imaging element 120 is constructed so that the chip can be reconfigured and bonded to the wafer, stacking can be performed in one chip even if there is a heterogeneous process that makes it difficult to manufacture circuits constructed by a process completely different from that of analog circuits such as power supply ICs and clock circuits and logic circuits 122 in the same wafer or even if there is a difference in wafer size.

[0179] Furthermore, although the foregoing description is directed to an example in which the memory circuit 121 and the logic circuit 122 are used as circuits connected to the solid-state imaging element 120, any signal processing circuit other than the memory circuit 121 and the logic circuit 122 may be connected as long as it is a signal processing circuit required for the operation of the solid-state imaging element 120, such as a circuit related to the control of the solid-state imaging element 120 or a circuit related to the processing of captured pixel signals. The signal processing circuit required for the operation of the solid-state imaging element 120 may be, for example, a power supply circuit, an image signal compression circuit, a clock circuit, or an optical communication conversion circuit.

[0180] <<3. Second embodiment>>

[0181] Although a description has been given above of the solid-state imaging device 111 having a two-layer structure in which a layer formed with the solid-state imaging element 120 and a layer further configured with the memory circuit 121 and the logic circuit 122 are stacked, the solid-state imaging device 111 may alternatively have a three-layer configuration.

[0182] Fig.10 1 is a diagram illustrating a stacked structure of wafers constructed by the WoW technology applied when manufacturing the three-layer structure solid-state imaging device of the present invention.

[0183] exist Fig.10 In the embodiment, a wafer 101 on which a solid-state imaging element 120 is formed, a wafer 201 on which a memory circuit 121 is further arranged, and a wafer 202 on which a logic circuit 122 is further arranged are stacked in order from the top.

[0184] Wafer 101 is similar to Figure 4 A wafer 101 is provided, and a plurality of solid-state imaging elements 120 are formed on the wafer 101 by a semiconductor process.

[0185] On the wafer 201 , a plurality of memory circuits 121 that have been electrically inspected and confirmed to be good chips after the memory circuits 121 are formed on the wafer 103 by a semiconductor process and separated into chips are selected and rearranged.

[0186] On the wafer 202 , a plurality of logic circuits 122 that have been electrically inspected and confirmed to be good chips after the logic circuits 122 are formed on the wafer 104 by a semiconductor process and separated into chips are selected and rearranged.

[0187] <Including through Fig.10 Example of a solid-state imaging device using WoW technology stacked wafers>

[0188] The solid-state imaging device of the present invention is a device that Fig.10The solid-state imaging device of the present invention is formed by singulating such wafers stacked by the WoW technology. Fig.11 The way shown is constructed. Note that Fig.11 , the upper stage is a side cross-sectional view, and the lower stage is a layout diagram of the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122 when viewed from above.

[0189] In particular, Fig.11 In the solid-state imaging device 111 in the upper section, an on-chip lens and an on-chip color filter 131, a solid-state imaging element 120, a storage circuit 121, a logic circuit 122, and a support substrate 132 are formed in this order from the top in the figure. In particular, as Fig.11 As shown in the above paragraph, Fig.11 The solid-state imaging device 111 has: a semiconductor element layer E11 including a solid-state imaging element 120 having a wafer 101; a semiconductor element layer E12 including a storage circuit 121 formed on the wafer 201; and a semiconductor element layer E13 including a logic circuit 122 formed on the wafer 202.

[0190] The terminal 120a of the solid-state imaging element 120 is electrically connected to the terminal 121a-1 of the memory circuit 121 via the wiring 134-1, and the wiring 134-1 is connected to the terminal 121a-1 via CuCu connection.

[0191] Meanwhile, the terminal 121 a - 2 of the memory circuit 121 is electrically connected to the terminal 122 a of the logic circuit 122 through the wiring 134 - 2 , and the wiring 134 - 2 is connected to the terminal 122 a through a CuCu connection.

[0192] In the space around the solid-state imaging element 120, the memory circuit 121, the logic circuit 122, and the support substrate 132, an oxide film 133 is formed. In addition, an oxide film bonding layer 135 is formed on the boundary between the semiconductor element layer E11 on which the solid-state imaging element 120 is formed and the semiconductor element layer E12 on which the memory circuit 121 is formed in such a manner that the memory circuit 121 is embedded in the oxide film 133, and these layers are bonded together by oxide film bonding. In addition, an oxide film bonding layer 135 is formed on the boundary between the semiconductor element layer E12 on which the memory circuit 121 is formed in an embedded relationship in the oxide film 133 and the semiconductor element layer E13 on which the logic circuit 122 is formed in an embedded relationship in the oxide film 133, and these layers are bonded together by oxide film bonding. An oxide film bonding layer 135 is formed on the boundary between the semiconductor element layer E13 on which the logic circuit 122 is formed and the support substrate 132, and these layers are bonded together by oxide film bonding.

[0193] In addition, if Fig.11 As shown in the lower section of , when viewed from above, the storage circuit 121 is formed at a substantially central position in a layer lower than the solid-state imaging element 120 , and the logic circuit 122 is arranged at a substantially central position in a layer lower than the storage circuit 121 .

[0194] In particular, Fig.10 On the wafer 201, when each solid-state imaging device 111 is singulated, the storage circuit 121 is reconfigured in a manner consistent with the central position of the solid-state imaging element 120, and on the wafer 202, the logic circuit 122 is reconfigured in a manner consistent with the central position of the solid-state imaging element 120.

[0195] < Fig.11 Method for manufacturing a solid-state imaging device>

[0196] Now, refer to Fig.12 and Fig.13 describe Fig.11 A method for manufacturing a solid-state imaging device 111. Note that Fig.12 and Fig.13 Side view of the Fig.12 A to 12F show side cross-sectional views of the solid-state imaging device 111 .

[0197] In the first step, Fig.12 Side view of Fig.12 As shown in A, on a supporting substrate 132-1, a solid-state imaging element 120 and a storage circuit 121 are stacked from the top, and the space between the solid-state imaging element 120 and the storage circuit 121 and the periphery of the storage circuit 121 are in a state of being filled with an oxide film 133, so that the storage circuit 121 is buried in the oxide film 133.

[0198] Please note that until Fig.12 Side view of Fig.12 The steps up to A are similar to those in Figure 6 Side view of Figure 6 A to Fig. 9 Side view of Figure 6 The steps of J are steps only in the case of forming the storage circuit 121, and thus their description is omitted.

[0199] In the second step, if Fig.12 Side view of Fig.12 As shown in FIG. 1B , the support substrate 132 - 1 is removed, and a wiring 134 - 2 is formed at the terminal 121 a - 2 of the memory circuit 121 .

[0200] In the third step, if Fig.12 Side view of Fig.12As shown in the range surrounded by alternating long and short dashed lines in C, the logic circuit 122 is positioned in such a manner that the storage circuit 121 and the wiring 134-2 are opposite to each other, wherein on the logic circuit 122, the wiring 134-2 is formed at the terminal 122a, and the logic circuit 122 is set on the supporting substrate 132-2.

[0201] Note that the portion surrounded by the alternating long and short dashed lines in which the memory circuit 121 is constructed on the support substrate 132-2 is similar to that in the Figure 6 Side view of Figure 6 A to Figure 8 Side view of Figure 6 The steps of H form only a part of the case of the logic circuit 122, and thus their description is omitted.

[0202] In the fourth step, if Fig.13 Side view of Fig.12 As shown in FIG. 1 , the lower surface portion of the memory circuit 121 and the upper surface portion of the logic circuit 122 are bonded to each other by oxide film bonding, and the terminal 121a-2 of the memory circuit 121 and the terminal 122a of the logic circuit 122 are connected to each other via the wiring 134-2. Therefore, the memory circuit 121, the logic circuit 122, and the solid-state imaging element 120 are electrically connected to each other.

[0203] In the fifth step, if Fig.13 Side view of Fig.12 As shown in E, the silicon layer of the solid-state imaging element 120 is thinned.

[0204] In the sixth step, if Fig.13 Side view of Fig.12 As shown in FIG. 5F, an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120 and are integrated into one chip, thereby completing the solid-state imaging device 111.

[0205] In this manner, the solid-state imaging device 111 having a total three-layer structure including a first layer having the solid-state imaging element 120 formed therein, a second layer having the memory circuit 121 formed therein, and a third layer having the logic circuit 122 formed therein is manufactured.

[0206] In addition, in such a configuration as described above, since the circuit connection between the solid-state imaging element 120, the storage circuit 121, and the logic circuit 122 can be established by using the same semiconductor lithography technology as in WoW through terminals formed with a fine wiring density, the number of connection terminals can be increased and a reduction in power consumption can be expected.

[0207] Furthermore, since the memory circuit 121 and the logic circuit 122 are connected only when they are good chips, the wafer yield which is a defect of WoW can be reduced, and the occurrence of yield loss can be reduced.

[0208] In addition, as mentioned above Fig.12 Side view of Fig.12 As shown in FIGS. 12A to 12C , a structure of three or more layers can be realized by forming wiring (back surface wiring) on ​​the lower surface in the figure.

[0209] <<4. Third embodiment>>

[0210] <Structural Example of Solid-State Imaging Device When Solid-State Imaging Element is Smaller than Memory Circuit or Logic Circuit>

[0211] Although the foregoing description has been given of an example in which the solid-state imaging element 120 is larger than both the storage circuit 121 and the logic circuit 122 , it may be alternatively constructed so that the solid-state imaging element 120 is smaller than at least any one of the storage circuit 121 and the logic circuit 122 .

[0212] Fig.14 A configuration example of the solid-state imaging device 111 having a two-layer configuration is shown in the case where the solid-state imaging element 120 is smaller than the memory circuit 121 but larger than the logic circuit 122 .

[0213] In particular, if Fig.14 As shown in the upper section of , the solid-state imaging element 120 is formed on a structure in which a layer in which a memory circuit 121 and a logic circuit 122 are formed is provided on a support substrate 132, and wiring 134 is formed at terminals 121a and 122a. Fig.14 As shown in the lower section of FIG. 1 , when viewed from above, the solid-state imaging element 120 is provided at a position straddling the storage circuit 121 and the logic circuit 122. In particular, as shown in FIG. Fig.14 As shown in the above paragraph, Fig.14 The solid-state imaging device 111 includes a semiconductor element layer E1 including a solid-state imaging element 120 having a wafer 101 , and a semiconductor element layer E2 including a memory circuit 121 and a logic circuit 122 formed on the wafer 102 .

[0214] Note that an insulating film including an oxide film 133 is formed around the solid-state imaging element 120 .

[0215] < Fig.14 Method for manufacturing a solid-state imaging device>

[0216] Now, refer to Fig.15 and Fig.16 describe Fig.14A method for manufacturing a solid-state imaging device 111. Note that Fig.15 and Fig.16 Side view of Fig.15 A to 15F show side cross-sectional views of the solid-state imaging device 111 .

[0217] In the first step, if Fig.15 Side view of Fig.15 As shown in FIG. 1A , the memory circuit 121 and the logic circuit 122 are formed on a support substrate 132, the memory circuit 121 and the logic circuit 122 are embedded in an insulating film including an oxide film 133, and an oxide film bonding layer 135 is formed on the uppermost layer. In addition, wiring 134 is formed at the terminals 121a and 122a.

[0218] Need to pay attention until the formation Fig.15 Side view of Fig.15 The steps of A are similar to those in Figure 6 Side view of Figure 6 A to Fig. 9 Side view of Figure 6 Steps H are steps in the case of forming the memory circuit 121 and the logic circuit 122 on the support substrate 132, and thus their description is omitted.

[0219] In the second step, if Fig.15 Side view of Fig.15 As shown in FIG. 2B , the solid-state imaging element 120 which has been singulated is re-arranged on the re-arrangement substrate 211 to which the adhesive 212 is applied so that the imaging surface side of the solid-state imaging element 120 faces the re-arrangement substrate 211. Fig.14 As shown in the lower section of FIG. 1 , the solid-state imaging element 120 is reconfigured on the reconfiguration substrate 211 at a position straddling the memory circuit 121 and the logic circuit 122 along the planar direction.

[0220] In the third step, if Fig.15 Side view of Fig.15 As shown in C, the side view cross section Fig.15 The solid-state imaging element 120 in the state of B is reversed and connected by CuCu bonding. Fig.15 In addition to the memory circuit 121 of A and the wiring 134 of the logic circuit 122, opposing layers are bonded together by oxide film bonding.

[0221] In the fourth step, if Fig.16 Side view of Fig.15 As shown in D, the rearrangement substrate 211 is removed.

[0222] In the fifth step, if Fig.16 Side view of Fig.15As shown in E, the silicon layer of the solid-state imaging element 120 is thinned.

[0223] In the sixth step, if Fig.16 Side view of Fig.15 F, an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120, and thereby the solid-state imaging device 111 is completed. Note that in this example, the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122 are all monolithic at the stage before being assembled.

[0224] In this way, even when the size of the solid-state imaging element 120 is smaller than the size of the storage circuit 121 but larger than the size of the logic circuit 122, a solid-state imaging device 111 with a total two-layer structure is manufactured, which includes a first layer formed with the solid-state imaging element 120 and a second layer formed with the storage circuit 121 and the logic circuit 122.

[0225] In addition, in such a configuration as described above, since the circuit connection between the solid-state imaging element 120, the storage circuit 121, and the logic circuit 122 can be established by terminals formed with a fine wiring density using the same semiconductor lithography technology as in WoW, the number of connection terminals can be increased and a reduction in power consumption can be expected.

[0226] Furthermore, since the memory circuit 121 and the logic circuit 122 are connected only when they are good chips, the wafer yield which is a defect of WoW can be reduced, and the occurrence of yield loss can be reduced.

[0227] It should be noted that, in the case where the solid-state imaging element 120 is smaller than the logic circuit 122 but larger than the memory circuit 121, the solid-state imaging device 111 can be manufactured through similar steps. Similarly, in the case where the solid-state imaging element 120 is smaller than both the logic circuit 122 and the memory circuit 121, the solid-state imaging device 111 can be manufactured through similar steps.

[0228] <<5. Fourth embodiment>>

[0229] <Configuration Example of a Three-Layer Solid-State Imaging Device in Which the Solid-State Imaging Element is Smaller Than the Memory Circuit and the Logic Circuit>

[0230] Although the foregoing description is directed to a construction example of a two-layer structure of a solid-state imaging device 111 in which the solid-state imaging element 120 is smaller than the storage circuit 121 but larger than the logic circuit 122, the solid-state imaging device 111 may have a three-layer structure even in a case where the solid-state imaging element 120 is smaller than the storage circuit 121 but larger than the logic circuit 122.

[0231] Fig.17 A configuration example of the solid-state imaging device 111 having a three-layer structure is shown in the case where the solid-state imaging element 120 is smaller than the memory circuit 121 but larger than the logic circuit 122 .

[0232] In particular, if Fig.17 As shown in the upper part of , the logic circuit 122 is formed on the support substrate 132 in such a manner that the logic circuit 122 is bonded by an oxide film through an oxide film bonding layer 135, and the memory circuit 121 is formed on the logic circuit 122 in such a manner that the memory circuit 121 is bonded by an oxide film through an oxide film bonding layer 135. In addition, the solid-state imaging element 120 is formed on the memory circuit 121 in such a manner that the solid-state imaging element 120 is bonded by an oxide film through an oxide film bonding layer 135, and an on-chip lens and an on-chip color filter 131 are formed on the solid-state imaging element 120. In particular, as Fig.17 As shown in the above paragraph, Fig.17 The solid-state imaging device 111 has: a semiconductor element layer E11 including a solid-state imaging element 120 having a wafer 101; a semiconductor element layer E12 including a storage circuit 121 formed on a wafer 201; and a semiconductor element layer E13 including a logic circuit 122 formed on a wafer 202.

[0233] In addition, the terminal 120a of the solid-state imaging element 120 and the terminal 121a-1 of the storage circuit 121 are electrically connected to each other through the CuCu bonding of the wiring 134-1, and the terminal 121a-2 of the storage circuit 121 and the terminal 122a of the logic circuit 122 are electrically connected through the CuCu bonding of the wiring 134-2.

[0234] In this case, if Fig.17 As shown in the lower part of , the solid-state imaging element 120, the storage circuit 121, and the logic circuit 122 are formed in such a manner that the center positions of the three are aligned with each other.

[0235] Note that an insulating film including an oxide film 133 is formed around the solid-state imaging element 120 .

[0236] As Fig.17 The method for manufacturing the solid-state imaging device 111 in Figure 6 Side view of Figure 6 A to Figure 8 Side view of Figure 6 H step to form the logic circuit 122, then, as Fig.15 Side view of Fig.15 As shown in B, the memory circuit 121 is placed on the reconfiguration substrate 211, and Fig.15 Side view of Fig.15C, the memory circuit 121 is connected to the logic circuit 122, and then the solid-state imaging element 120 is formed by a similar method. Therefore, the description with reference to the drawings is omitted.

[0237] In addition, in such a configuration as described above, since the circuit connection between the solid-state imaging element 120, the storage circuit 121, and the logic circuit 122 can be established by terminals formed with a fine wiring density using the same semiconductor lithography technology as in WoW, the number of connection terminals can be increased and a reduction in power consumption can be expected.

[0238] Furthermore, since the memory circuit 121 and the logic circuit 122 are connected only when they are good chips, the wafer yield which is a defect of WoW can be reduced, and the occurrence of yield loss can be reduced.

[0239] It should be noted that, in the case where the solid-state imaging element 120 is smaller than the logic circuit 122 but larger than the memory circuit 121, the solid-state imaging device 111 can be manufactured through similar steps. Similarly, in the case where the solid-state imaging element 120 is smaller than both the logic circuit 122 and the memory circuit 121, the solid-state imaging device 111 can be manufactured through similar steps.

[0240] <<6. Fifth embodiment>>

[0241] <Structural Example of Solid-State Imaging Device in Which Memory Circuit and Logic Circuit Are Directly Formed on Wafer of Solid-State Imaging Element>

[0242] The foregoing description is directed to an example in which the memory circuit 121 and the logic circuit 122 are formed on the wafer 102 (support substrate 132) after being singulated and confirmed to be good chips. However, the memory circuit 121 and the logic circuit 122 that have been singulated and confirmed to be good chips may be formed directly on the solid-state imaging element 120 on the wafer 101.

[0243] Fig.18 1 is a diagram illustrating a method of manufacturing a solid-state imaging device in which a memory circuit 121 and a logic circuit 122 that have been singulated and confirmed to be good chips are directly formed on the solid-state imaging element 120 on the wafer 101 .

[0244] In particular, refer to Fig.18, a plurality of solid-state imaging elements 120 are formed on the wafer 101 by a semiconductor process. In addition, a plurality of memory circuits 121 that are electrically inspected and confirmed as good chips by the electrical inspection after the memory circuits 121 are formed on the wafer 103 by a semiconductor process and singulated, and a plurality of logic circuits 122 that are electrically inspected and confirmed as good chips by the electrical inspection after the logic circuits 122 are formed on the wafer 104 by a semiconductor process and singulated, are selected and reconfigured on the solid-state imaging element 120 formed on the wafer 101. In other words, since the memory circuits 121 and the logic circuits 122 that have been confirmed as good chips are reconfigured on the solid-state imaging element 120, the memory circuits 121 and the logic circuits 122 here are constructed to be smaller than the solid-state imaging element 120. .

[0245] Note that the configuration example of the solid-state imaging device 111 having a two-layer structure is similar to that in the case where the memory circuit 121 and the logic circuit 122 that have been singulated and confirmed as good chips are directly formed on the solid-state imaging element 120 on the wafer 101. Figure 5 Therefore, the description of this example is omitted.

[0246] < Fig.14 Method for manufacturing a solid-state imaging device>

[0247] Now, refer to Fig.19 and Fig. 20 describe Fig.18 A method for manufacturing the solid-state imaging device 111. Fig.19 and Fig. 20 Side view of Fig.19 A to 19E show side cross-sectional views of the solid-state imaging device 111 .

[0248] In the first step, if Fig.19 Side view of Fig.19 As shown in FIG. 1A, a memory circuit 121 and a logic circuit 122, which have been confirmed as good chips through electrical inspection, are formed on the solid-state imaging element 120 on the wafer 101 so that they have the following characteristics: Figure 5 , and wiring 134 is formed on terminals 120a and 121a. Furthermore, positioning is performed so that wiring 134 from terminal 121a of storage circuit 121 and terminal 122a of logic circuit 122, and wiring 134 from terminal 120a of solid-state imaging element 120 of wafer 101 are positioned in appropriate relative relationship to each other and connected by CuCu bonding, and in addition, opposing layers are bonded together by oxide film bonding to form oxide film bonding layer 135.

[0249] In the second step, if Fig.19 Side view of Fig.19 As shown in B, the silicon layer at the upper surface portion of the storage circuit 121 and the logic circuit 122 in the figure is thinned to a height that has no effect on the performance of the device, and an oxide film 133 that acts as an insulating film is formed, so that the chip including the reconfigured storage circuit 121 and the logic circuit 122 is embedded in the oxide film 133.

[0250] In the third step, if Fig.19 Side view of Fig.19 C, the support substrate 132 is bonded to the upper portions of the memory circuit 121 and the logic circuit 122. At this time, the support substrate 132 and the mutually opposing layers of the memory circuit 121 and the logic circuit 122 are bonded together by oxide film bonding to form an oxide film bonding layer 135.

[0251] In the fourth step, if Fig. 20 Side view of Fig.19 As shown in D, the solid-state imaging element 120 is turned upside down so that the solid-state imaging element 120 is at the upper part, and the silicon layer which is the upper layer in the figure of the solid-state imaging element 120 is thinned.

[0252] In the fifth step, if Fig. 20 Side view of Fig.19 As shown in FIG. 8E, an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120, and the solid-state imaging device 111 is completed by single-chip processing.

[0253] Note that in the first step, when the memory circuit 121 and the logic circuit 122 are reconfigured and bonded to the solid-state imaging element 120, after they are respectively subjected to hydrophilic treatment, they are, for example, Fig.21 The memory circuit 121 or logic circuit 122 shown in the upper section of the monolithic structure is in contact with each other in a state where a portion (such as an edge or an end point) is positioned with certainty relative to the solid-state imaging element 120. Then, as shown in FIG. Fig.21 As shown in the lower part of , in the portion of the storage circuit 121 or the logic circuit 122, those portions close to the portion in contact with the solid-state imaging element 120 gradually come into contact with the solid-state imaging element 120 until the storage circuit 121 or the logic circuit 122 is completely in contact and joined through the oxide film.

[0254] After a portion such as an end edge or an end point of the memory circuit 121 or the logic circuit 122 is positioned with high precision and contacts the solid-state imaging element 120, the memory circuit 121 or the logic circuit 122 gradually contacts from a portion close to the contact portion until the two are reconfigured in this manner. Therefore, the alignment accuracy of the memory circuit 121 and the logic circuit 122 with the solid-state imaging element 120 can be improved.

[0255] In addition, since the storage circuit 121 or the logic circuit 122 is gradually and completely joined after part of the storage circuit 121 or the logic circuit 122 contacts the solid-state imaging element 120 in this positioned state, they can be joined while gradually squeezing out the gaps (bubbles) appearing in the joining surface.

[0256] As a result, since the occurrence of voids in the bonding surface can be suppressed, even if the solid-state imaging device 111 is placed in a high temperature state in a different manufacturing step or during operation, the expansion and explosion of air in the voids (bubbles) can be suppressed, and the product accuracy can be improved. Figure 6 Side view of Figure 6 In the first step of the first embodiment described in A, after part of the memory circuit 121 or the logic circuit 122 is brought into contact with the solid-state imaging element 120 in a positioned state, the entire memory circuit 121 or the logic circuit 122 may be gradually joined.

[0257] Furthermore, in the second step, Fig. 22 The upper part (similar to Fig.21 As shown in the lower part of FIG. 1 , after the storage circuit 121 and the logic circuit 122 are connected to the solid-state imaging element 120, as shown in FIG. Fig. 22 As shown in the lower section of FIG. 1 , the silicon layer of the memory circuit 121 and the logic circuit 122 located at the upper surface portion in the figure is thinned to a height that does not affect the performance of the device. Then, the memory circuit 121 and the logic circuit 122 are embedded in an insulating film including an oxide film 133, and an oxide film bonding layer 135 is formed on the flattened uppermost surface, thereby obtaining a device as shown in FIG. Fig.19 Side view of Fig.19 This structure is shown in B.

[0258] Through such manufacturing steps as described above, the solid-state imaging device 111 including the first layer in which the solid-state imaging element 120 is formed and the second layer in which the memory circuit 121 and the logic circuit 122 are formed is manufactured.

[0259] As a result, since the memory circuit 121 and the logic circuit 122 are connected to the solid-state imaging element 120, the step of arranging the memory circuit 121 and the logic circuit 122 on the support substrate is omitted, and the man-hours can be reduced. In addition, since the support substrate becomes partially unnecessary at the time of manufacturing, the manufacturing cost can be reduced. In addition, since the memory circuit 121 and the logic circuit 122 are reconfigured on the solid-state imaging element 120 in a state directly positioned relative to each other, the alignment accuracy of the memory circuit 121 and the logic circuit 122 relative to the solid-state imaging element 120 can be improved.

[0260] <<7. Modification of the Fifth Embodiment>>

[0261] <Modification of Solid-State Imaging Device in Which Memory Circuit and Logic Circuit Are Directly Formed on Wafer of Solid-State Imaging Element>

[0262] Although the above-described solid-state imaging device is constructed such that the memory circuit 121 and the logic circuit 122 are embedded in the insulating film including the oxide film 133 and the oxide film bonding layer 135 is formed on the planarized uppermost surface, so as to have Fig.19 Side view of Fig.19 The structure shown in B can be replaced by applying or laminating a high heat-resistant resin.

[0263] In particular, if Fig.23 As shown in the upper part of , after the storage circuit 121 and the logic circuit 122 are formed on the solid-state imaging element 120 on the wafer 101 , a high heat-resistant resin 251 including an organic film or the like may be applied or laminated on the storage circuit 121 and the logic circuit 122 .

[0264] like Fig.23 As shown in the lower part, by joining the support substrate 132 while the high heat-resistant resin 251 is maintained in a coated state or a laminated state, the support substrate 132 can be pasted without thinning the silicon layer at the upper surface portion of the storage circuit 121 and the logic circuit 122, and the working hours can be reduced.

[0265] It should be noted that the oxide film 133 used as an insulating film for the memory circuit 121 and the logic circuit 122 and as an embedded member is preferably a Si-based oxide film such as SiO2, SiO, and SRO. In addition, for the high heat-resistant resin 241, a polyimide-based film or a polyamide-based film such as PI or PBO is preferably used as a high heat-resistant material including an organic film.

[0266] <<8. Sixth embodiment>>

[0267] <Structural Example of Solid-State Imaging Device Where Memory Circuit and Logic Circuit Are Formed in Multiple Layers on Wafer Having Solid-State Imaging Element Formed>

[0268] The foregoing description is directed to an example in which a solid-state imaging device is formed by configuring a memory circuit 121 and a logic circuit 122 that are monolithic and confirmed as good chips in one layer on the solid-state imaging element 120 formed on the wafer 101. However, the memory circuit 121 and the logic circuit 122 that are confirmed as good chips may be configured in multiple layers to form a solid-state imaging device.

[0269] Fig.24The diagram illustrates a stacked structure of a wafer constructed by the WoW technology applied to a solid-state imaging device, wherein the solid-state imaging device is manufactured by forming two layers of a storage circuit 121 and a logic circuit 122 that have been monolithicized and confirmed to be good chips on a solid-state imaging element 120 formed on the wafer 101 of the present invention.

[0270] exist Fig.24 In the figure, wafer 102 and wafer 101 are stacked from the top, on wafer 102, storage circuit 121 and logic circuit 122 are reconfigured, and on wafer 101, storage circuit 121 and logic circuit 122 are reconfigured on solid-state imaging element 120. It should be noted that Fig.24 In the embodiment, the wafer 102 and the wafer 101 are configured so that the respective surfaces on which the memory circuit 121 and the logic circuit 122 are reconfigured face each other. Fig.24 In the figure, the memory circuit 121 and the logic circuit 122 on the wafer 102 indicated by the dotted line indicate that the surface of the memory circuit 121 and the logic circuit 122 is opposite to the wafer 101.

[0271] <Including through Fig.24 Example of a solid-state imaging device structure using wafers stacked using the WoW technology>

[0272] Through Fig.24 Such wafers stacked by the WoW technology shown in FIG. are singulated to form the solid-state imaging device of the present invention. The solid-state imaging device of the present invention has, for example, Fig.25 This construction is shown in the side cross-sectional view.

[0273] In particular, Fig.25 The solid-state imaging device 111 includes: an on-chip lens and an on-chip color filter 131 in the first layer from the top, a solid-state imaging element 120, a storage circuit 121-11 and a logic circuit 122-11; a storage circuit 121-11 and a logic circuit 122-12 in the second layer from the top; and a supporting substrate 132.

[0274] In particular, if Fig.25 As shown in Fig.24 The solid-state imaging device 111 includes: a semiconductor element layer E31, which includes a solid-state imaging element 120 having a wafer 101; a semiconductor element layer E32, which includes a first-layer storage circuit 121-11 and a logic circuit 122-11 directly formed by reconfiguration on the solid-state imaging element 120; and a semiconductor element layer E33, which includes a second-layer storage circuit 121-12 and a logic circuit 122-12 formed on the wafer 102.

[0275] The terminal 120a of the solid-state imaging element 120 is electrically connected to the terminal 121a-11 of the memory circuit 121-11 and the terminal 122a-11 of the logic circuit 122-11 of the semiconductor element layer E32 via the wiring 134-11 connected by CuCu connection. In addition, the terminal 121a-11 of the memory circuit 121-11 and the terminal 122a-11 of the logic circuit 122-11 of the semiconductor element layer E32 are electrically connected to the terminal 121a-12 of the memory circuit 121-12 and the terminal 122a-12 of the logic circuit 122-12 of the semiconductor element layer E33 via the wiring 134-12 connected by CuCu connection.

[0276] An oxide film 133 is formed in the space around the solid-state imaging element 120, the memory circuits 121-11 and 121-12 and the logic circuits 122-11 and 122-12 of the semiconductor element layers E32 and E33, and the supporting substrate 132. In addition, an oxide film bonding layer 135 is formed on the boundary between the semiconductor element layer E31 on which the solid-state imaging element 120 is formed and the semiconductor element layer E32 in which the memory circuit 121-11 and the logic circuit 122-11 are formed and embedded in the oxide film 133, and these layers are bonded together by oxide film bonding. Furthermore, an oxide film bonding layer 135 is formed on a boundary between the semiconductor element layer E32 in which the memory circuit 121-11 and the logic circuit 122-11 are formed and embedded in the oxide film 133, and the semiconductor element layer E33 in which the memory circuit 121-12 and the logic circuit 122-12 are formed and embedded in the oxide film 133, and the layers are bonded together by oxide film bonding. An oxide film bonding layer 135 is formed on a boundary between the support substrate 132 and the semiconductor element layer E33 in which the memory circuit 121-12 and the logic circuit 122-12 are formed and embedded in the oxide film 133, and the layers are bonded together by oxide film bonding.

[0277] < Fig.25 Method for manufacturing a solid-state imaging device>

[0278] Now, refer to Figure 26 to Figure 28 describe Fig.25 A method for manufacturing a solid-state imaging device 111. Note that Figure 26 to Figure 28 Side view of Fig.26 A to 26G show side cross-sectional views of the solid-state imaging device 111 .

[0279] In the first step, if Fig.26 Side view of Fig.26 As shown in FIG. 1A, after the solid-state imaging element 120 on the wafer 101 is electrically inspected, the memory circuit 121 and the logic circuit 122 that are confirmed to be good are formed as shown in FIG. Figure 5 1 and the wiring 134-11 is formed to the terminals 120a and 121a. Furthermore, positioning is performed so that the wiring 134-11 from the terminal 121a-11 of the storage circuit 121-11 and the terminal 122a-11 of the logic circuit 122-11 and the wiring 134-11 from the terminal 120a of the solid-state imaging element 120 in the wafer 101 are positioned in an appropriate relative relationship to each other, and they are connected to each other by CuCu bonding, and the opposing layers are bonded together by an oxide film bonding layer 135 formed by oxide film bonding.

[0280] In the second step, if Fig.26 Side view of Fig.26 As shown in FIG. 1B , a wiring 134 - 12 formed of, for example, a through-hole via (TSV) is formed for the terminal 121 a - 11 of the memory circuit 121 - 11 and the terminal 122 a - 11 of the logic circuit 122 - 11 .

[0281] In the third step, if Fig.26 Side view of Fig.26 As shown in C, a PAD (pad) for connection and an oxide film bonding layer 135 for connection are formed for the wiring 134 - 12 .

[0282] In the fourth step, if Fig. 27 Side view of Fig.26 D, by referring to the above Fig.19 Side view of Fig.19 A and Fig.19 B and Fig.21 and Fig. 22 In a similar manner to the described method, the terminal 121a-12 of the memory circuit 121-12 and the terminal 122a-12 of the logic circuit 122-12 are formed in an electrically connected state through the wiring 134-12.

[0283] In the fifth step, if Fig. 27 Side view of Fig.26 E, the support substrate 132 is bonded to the upper portions of the memory circuit 121-12 and the logic circuit 122-12. At this time, the support substrate 132 and the opposing layers of the memory circuit 121-12 and the logic circuit 122-12 are bonded together via an oxide film bonding layer 135 formed by oxide film bonding.

[0284] In the sixth step, if Fig. 27 Side view of Fig.26 As shown in F, the solid-state imaging element 120 is turned upside down so that the solid-state imaging element 120 is at the upper part, and the silicon layer, which is the layer at the top of the solid-state imaging element 120 in the figure, is thinned.

[0285] In the seventh step, if Fig.28 Side view of Fig.26 As shown in FIG. 1G , an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120 , and the solid-state imaging device 111 is completed by single-chip processing.

[0286] By such bonding as described above, the memory circuit 121 and the logic circuit 122 can be stacked in multiple layers.

[0287] Note that although the foregoing description is directed to an example in which the memory circuit 121 and the logic circuit 122 are formed in two layers, the memory circuit 121 and the logic circuit 122 may alternatively be stacked in three or more layers by using a similar method.

[0288] <<9. Connection example of solid-state imaging element>>

[0289] <First Connection Example>

[0290] Although the foregoing description is directed to an example in which, regarding bonding, oxide film bonding is applied to portions other than terminals, and CuCu bonding is applied to the terminals to form the wiring 134 for establishing electrical connection, other connection methods may be used.

[0291] Fig.29 Connection examples 29A to 29D are shown in the case where the terminals 120 a and 122 a of the solid-state imaging element 120 and the logic circuit 122 are connected to each other within the range indicated by the block Z11 of the solid-state imaging device 111 in the upper left stage.

[0292] In connection example 29A, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged at the same position in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is provided in a relationship offset to the boundary side with the solid-state imaging element 120 in the vertical direction in the figure. In addition, through holes are formed so as to extend from the back side (lower side in the figure) of the solid-state imaging device 111 through the terminals 122a and 120a, and wiring 134A is formed in each through hole.

[0293] In connection example 29B, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged in a relationship offset from each other in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is arranged in a relationship offset to the boundary side with the solid-state imaging element 120 in the vertical direction in the figure. In addition, through holes are formed so that the through holes extend through the terminals 122a and 120a independently of each other from the back side (lower side in the figure) of the solid-state imaging device 111. In addition, wiring 134B is formed in the through hole, and the wiring is connected on the surface of the back side.

[0294] In connection example 29C, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged at the same position in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is arranged in a relationship offset to the back side (lower side in the figure) of the solid-state imaging element 120 in the vertical direction in the figure. In addition, a through hole is formed so that the through hole extends from the back side (lower side in the figure) of the solid-state imaging device 111 through the terminals 122a and 120a, and a wiring 134C is formed in the through hole.

[0295] In connection example 29D, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged in a relationship offset from each other in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is arranged in a relationship offset to the back side (lower side in the figure) of the solid-state imaging element 120 in the vertical direction in the figure. In addition, via holes are formed so that the via holes extend through the terminals 122a and 120a independently of each other from the back side (lower side in the figure) of the solid-state imaging device 111, and wiring 134D is formed in the via holes, and the wiring is connected on the surface of the back side.

[0296] <Use Fig.29 Method for manufacturing a solid-state imaging device according to a connection example of a solid-state imaging element>

[0297] Now, refer to Figure 30 to Figure 32 Describe the use Fig.29 A method for manufacturing a solid-state imaging device 111 according to a connection example. Note that Figure 30 to Figure 32 Side view of Fig.30 A to 30H show side cross-sectional views of the solid-state imaging device 111. Here, connection example 29A is described.

[0298] In the first step, if Fig.30 Side view of Fig.30As shown in A, the memory circuit 121 and the logic circuit 122 that are confirmed as good products after electrical inspection are reconfigured on the reconfiguration substrate 151 corresponding to the wafer 102. The reconfiguration substrate 151 is coated with an adhesive 152, and the memory circuit 121 and the logic circuit 122 are reconfigured and fixed on the reconfiguration substrate 151 by the adhesive 152. It should be noted that, as mentioned above, Fig. 22 As described above, after a portion such as an end face or an end point of the storage circuit 121 or the logic circuit 122 contacts the solid-state imaging element 120, other portions of the storage circuit 121 or the logic circuit 122 gradually contact, join, and reconfigure starting from the portion close to the contact portion.

[0299] In the second step, if Fig.30 Side view of Fig.30 As shown in B, it is inverted so that the side view cross section Fig.30 The upper surfaces of the memory circuit 121 and the logic circuit 122 shown in A become the lower part, and an oxide film bonding layer 135 is formed on the solid-state imaging element 120 to bond the memory circuit 121 and the logic circuit 122 to the solid-state imaging element 120 by oxide film bonding.

[0300] In the third step, if Fig.30 Side view of Fig.30 As shown in C, the reconfigured substrate 151 and the adhesive 152 are debonded, peeled off, and removed.

[0301] In the fourth step, if Fig.31 Side view of Fig.30 As shown in FIG. 2D , the silicon layer of the memory circuit 121 and the logic circuit 122 located at the upper surface portion in the figure is thinned to a level that has no effect on the performance of the device.

[0302] In the fifth step, if Fig.31 Side view of Fig.30 As shown in FIG. E, an oxide film 133 serving as an insulating film is formed so that the chip including the reconfigured memory circuit 121 and the logic circuit 122 is embedded in the oxide film 133, and then the oxide film 133 is flattened. In addition, the terminal 121a of the memory circuit 121 and the terminal 120a of the solid-state imaging element 120 are arranged at the same position in the horizontal direction, and a through hole is formed so as to extend through the terminals 120a and 121a. Thereafter, a metal is embedded in the through hole to form a wiring 134A in each through hole.

[0303] In the sixth step, if Fig.31 Side view of Fig.30 As shown in F, the side view cross section Fig.30The configuration shown in E is reversed, and an oxide film bonding layer 135 is formed on the support substrate 132, and then the configuration is bonded to the support substrate 132 by oxide film bonding.

[0304] In the seventh step, if Fig.32 Side view of Fig.30 As shown in G, the silicon layer of the solid-state imaging element 120 is thinned.

[0305] In the eighth step, if Fig.32 Side view of Fig.30 As shown in FIG. 1H, an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120 and integrated into one chip, thereby completing the solid-state imaging device 111.

[0306] By such steps as described above, the wiring 134A is formed in the through hole formed to extend from the back side to establish a state in which the solid-state imaging element 120 and the memory circuit 121 and the logic circuit 122 are electrically connected to each other, thereby manufacturing the solid-state imaging device 111.

[0307] Note that, although the wirings 134B to 134D shown in connection examples 29B to 29C are different in the positions, depths, and numbers of through holes, the wirings 134B to 134D can also be manufactured through similar steps.

[0308] In addition, in such a configuration as described above, since the circuit connection between the solid-state imaging element 120 and the storage circuit 121 and the logic circuit 122 can be established by terminals formed with a fine wiring density using the same semiconductor lithography technology as in WoW, the number of connection terminals can be increased and a reduction in power consumption can be expected.

[0309] <Second connection example>

[0310] Although the foregoing description is directed to an example in which through holes are formed from the back side (the side opposite to the imaging surface) of the solid-state imaging device 111 and wiring for electrical connection terminals is formed, wiring can be formed by forming through holes from the front side (the imaging surface side) and pouring metal into the through holes.

[0311] Fig.33 Connection examples 33A to 33D are shown in the case where the terminals 120 a and 122 a of the solid-state imaging element 120 and the logic circuit 122 are connected to each other within the range indicated by the block Z21 of the solid-state imaging device 111 in the upper left stage.

[0312] In connection example 33A, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged at the same position in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is provided in a relationship offset to the boundary side with the solid-state imaging element 120 in the vertical direction in the figure. In addition, a through hole is formed so as to extend through the terminals 122a and 120a from the front side (upper side in the figure) of the solid-state imaging device 111 in a piercing state, and a wiring 134E is formed in the through hole.

[0313] In connection example 33B, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged in a relationship offset from each other in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is provided in a relationship offset to the boundary side with the solid-state imaging element 120 in the vertical direction in the figure. In addition, through holes are formed so as to extend through the terminals 122a and 120a independently of each other from the front side (upper side in the figure) of the solid-state imaging device 111, and wiring 134F is formed in the through holes, and the wiring is connected on the surface of the front side.

[0314] In connection example 33C, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged at the same position in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is provided in a relationship offset in the vertical direction in the figure to the back side (lower side in the figure) of the solid-state imaging element 120. In addition, a through hole is formed so that the through hole extends from the front side (upper side in the figure) of the solid-state imaging device 111 through the terminals 122a and 120a in a piercing state, and a wiring 134G is formed in the through hole.

[0315] In connection example 33D, the terminal 122a of the logic circuit 122 and the terminal 120a of the solid-state imaging element 120 are arranged in a relationship offset from each other in the horizontal direction in the figure, and the terminal 122a of the logic circuit 122 is arranged in a relationship offset to the back side (lower side in the figure) of the solid-state imaging element 120 in the vertical direction in the figure. In addition, through holes are formed so that the through holes extend through the terminals 122a and 120a independently of each other from the front side (upper side in the figure) of the solid-state imaging device 111, and wiring 134H is formed in the through holes, and the wiring is connected on the surface of the back side.

[0316] Note that, since it is necessary to form a through hole from the imaging plane, all the wirings 134E to 134H are formed outside the pixel region of the solid-state imaging element 120 in the horizontal direction.

[0317] <Use Fig.33 Method for manufacturing a solid-state imaging device according to a connection example of a solid-state imaging element>

[0318] Now, refer to Figure 34 to Figure 36 Describe the use Fig.33 A method for manufacturing a solid-state imaging device 111 according to a connection example. Note that Figure 34 to Figure 36 Side view of Fig.34 A to 34H show side cross-sectional views of the solid-state imaging device 111. In addition, a description is given here of the connection example 33A.

[0319] In the first step, if Fig.34 Side view of Fig.34 As shown in A, the memory circuit 121 and the logic circuit 122 that are confirmed as good products after electrical inspection are reconfigured on the reconfiguration substrate 151 corresponding to the wafer 102. The reconfiguration substrate 151 is coated with an adhesive 152, and the memory circuit 121 and the logic circuit 122 are reconfigured and fixed on the reconfiguration substrate 151 by the adhesive 152. It should be noted that, as mentioned above, Fig. 22 As described above, after a portion such as an end face or an end point of the storage circuit 121 or the logic circuit 122 contacts the solid-state imaging element 120, other portions of the storage circuit 121 or the logic circuit 122 gradually contact, join, and reconfigure starting from the portion close to the contact portion.

[0320] In the second step, if Fig.34 Side view of Fig.34 As shown in B, it is inverted so that the side view cross section Fig.34 The upper surfaces of the memory circuit 121 and the logic circuit 122 shown in A now become the lower surfaces, and an oxide film bonding layer 135 is formed on the solid-state imaging element 120 to achieve oxide film bonding.

[0321] In the third step, if Fig.34 Side view of Fig.34 As shown in C, the reconfigured substrate 151 and the adhesive 152 are debonded, peeled off, and removed.

[0322] In the fourth step, if Fig.35 Side view of Fig.34 As shown in FIG. 2D , the silicon layer of the memory circuit 121 and the logic circuit 122 located at the upper surface portion in the figure is thinned to a level that has no effect on the performance of the device.

[0323] In the fifth step, if Fig.35 Side view of Fig.34 As shown in FIG. 8E, an oxide film 133 serving as an insulating film is formed so that the chip including the reconfigured memory circuit 121 and the logic circuit 122 is embedded in the oxide film 133 and the oxide film 133 is planarized.

[0324] In the sixth step, if Fig.35 Side view of Fig.34 As shown in F, the side view cross section Fig.34 The configuration shown in E is reversed, and an oxide film bonding layer 135 is formed on the support substrate 132 to achieve oxide film bonding.

[0325] In the seventh step, if Fig.36 Side view of Fig.34 G, the silicon layer of the solid-state imaging element 120 is thinned. In addition, the terminal 121a of the storage circuit 121 and the terminal 120a of the solid-state imaging element 120 are arranged at the same position in the horizontal direction, and a through hole is formed so as to extend through the terminals 120a and 121a from the front side so that the terminals 120a and 121a are placed in a pierced state. Then, a metal is embedded in the through hole to form the wiring 134E.

[0326] In the eighth step, if Fig.36 Side view of Fig.34 As shown in FIG. 1H , an on-chip lens and an on-chip color filter 131 are provided on the solid-state imaging element 120 , and the solid-state imaging device 111 is completed by single-chip processing.

[0327] Through such steps as described above, wiring 134A is formed through a through hole formed from the front side (imaging surface side) to establish a state in which the solid-state imaging element 120 and the storage circuit 121 and the logic circuit 122 are electrically connected to each other, thereby manufacturing the solid-state imaging device 111.

[0328] Note that although the wirings 134F to 134H shown in the connection examples 33B to 33C are different in the positions, depths, and numbers of through holes, the wirings 134F to 134H can also be manufactured by similar steps.

[0329] In addition, in such a configuration as described above, since the circuit connection between the solid-state imaging element 120 and the storage circuit 121 and the logic circuit 122 can be established by terminals formed with a fine wiring density using the same semiconductor lithography technology as in WoW, the number of connection terminals can be increased and a reduction in power consumption can be expected.

[0330] <<10. Modification of the connection example of the solid-state imaging element>>

[0331] <First Modification of Connection Example of Solid-State Image Sensor>

[0332] The electrical connection between the solid-state imaging element 120, the storage circuit 121 and the logic circuit 122 can be as follows: Fig.29 and Fig.33 The connection examples are different.

[0333] Fig.37A modification of the electrical connection example among the solid-state imaging element 120 , the memory circuit 121 , and the logic circuit 122 of the solid-state imaging device 111 is shown.

[0334] exist Fig.37 , a first semiconductor substrate 321, a second semiconductor substrate 322, and a third semiconductor substrate 323 are stacked from the top, and it is assumed that the solid-state imaging element 120 is formed in the first semiconductor substrate 321, while the memory circuit 121 is formed in the second semiconductor substrate 322 and the logic circuit 122 is formed in the third semiconductor substrate 323. It is to be noted that the substrates on which the memory circuit 121 and the logic circuit 122 are formed may be interchangeable.

[0335] Furthermore, in the first semiconductor substrate 321, the second semiconductor substrate 322, and the third semiconductor substrate 323, multilayer wiring layers 331, 332, and 333 for the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122 are formed, respectively. Fig.37 In the embodiment, the multilayer wiring layer 332 faces the third semiconductor substrate 323 , and the multilayer wiring layers 332 and 333 are configured such that they are pasted to each other on the boundary between the second semiconductor substrate 322 and the third semiconductor substrate 323 .

[0336] Furthermore, pads 341 and 342 for external connection including metal such as aluminum are provided, and a signal is input and output to and from an external device connected through a pad hole 350 through the pad 341 connected to the pad 342 .

[0337] like Fig.37 As shown, the pad hole 350 is formed in the first semiconductor substrate 321 so that the pad hole 350 extends from the back side (light receiving surface side) of the first semiconductor substrate 321 to the pad 341. In addition, the pad 342 is formed in the multilayer wiring layer 331 of the first semiconductor substrate 321.

[0338] In addition, Fig.37 In the configuration of , there are provided a contact 351 for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322 and a contact 352 for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323. The contact 351 and the contact 352 are configured as double contacts.

[0339] In particular, if Fig.37 As shown, for the electrical connection between the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122, double contacts 351 and 352 can be used.

[0340] <Second Modification of Connection Example of Solid-State Image Sensor>

[0341] like Fig.38 As shown, the multilayer wiring layer 331 of the first semiconductor substrate 321 can face the second semiconductor substrate 322 side (upper side in the figure) so that the multilayer wiring layers 331 and 332 are attached to each other on the boundary between the first semiconductor substrate 321 and the second semiconductor substrate 322.

[0342] exist Fig.38 In the structure, different from Fig.37 In the case of , the pad 342 is provided in the multilayer wiring layer 332 of the second semiconductor substrate 322. Further, in the first semiconductor substrate 321, the pad hole 350 is formed to extend from the back side (light receiving surface side) of the first semiconductor substrate 321 to the pad 341.

[0343] In addition, Fig.38 In the configuration of , there are provided a contact 361 for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322 and a contact 362 for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323. The contacts 361 and 362 are configured as double contacts.

[0344] exist Fig.38 In the case of the construction, different from Fig.37 In the case of FIG. 34 , the contact 362 extends through the first semiconductor substrate 321 and the second semiconductor substrate 322 to reach the multilayer wiring layer 333 of the third semiconductor substrate 323 .

[0345] In particular, if Fig.38 As shown, for the electrical connection between the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122, double contacts 361 and 362 can be used.

[0346] <Third Modification of Connection Example of Solid-State Image Sensor>

[0347] exist Fig.39 In the structure, the first semiconductor substrate 321 and the second semiconductor substrate 322 are attached to each other so that the insulating film layer 371 of the second semiconductor substrate 322 faces the third semiconductor substrate 323 side (the lower side in the figure).

[0348] In addition, Fig.39 In the construction of Fig.37 A contact 351 for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322 and a contact 352 for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323 are provided. The contacts 351 and 352 are configured as double contacts.

[0349] In addition, Fig.39 In the structure, different from Fig.37In the case of, the insulating film layer 371 is formed between the first semiconductor substrate 321 and the second semiconductor substrate 322. In addition, the pad 341 is arranged in the insulating film layer 371, and the pad 341 is connected to the contact 372, and the contact 372 is connected to the multilayer wiring layer 332 of the second semiconductor substrate 322.

[0350] In addition, Fig.39 In the configuration, the pad hole 350 is formed in the first semiconductor substrate 321 such that the pad hole 350 extends from the back side (light receiving surface side) of the first semiconductor substrate 321 to the pad 341 in the insulating film layer 371 .

[0351] In particular, if Fig.39 As shown, double contacts 351 and 352 can be used for electrical connection between the solid-state imaging element 120, the storage circuit 121, and the logic circuit 122. In addition, the pad 341 can be configured to be connected to the insulating film layer 372, which is connected to the multilayer wiring layer 332 of the second semiconductor substrate 322.

[0352] <Fourth Modification of Connection Example of Solid-State Image Sensor>

[0353] exist Fig.40 In the construction of Fig.37 In the case of the first semiconductor substrate 321, the pad hole 350 is formed in the first semiconductor substrate 321 so that the pad hole 350 extends from the back side (light receiving surface side) of the first semiconductor substrate 321 to the pad 341. In addition, the pad 342 is formed in the multilayer wiring layer 331 of the first semiconductor substrate 321.

[0354] exist Fig.40 In the construction of Fig.37 In this case, the first semiconductor substrate 321 and the second semiconductor substrate 322 are pasted to each other so that the multilayer wiring layer 332 of the second semiconductor substrate 322 faces the third semiconductor substrate 323 side (the lower side in the figure).

[0355] In addition, Fig.40 In the construction of Fig.37 In the case of the first semiconductor substrate 321 and the second semiconductor substrate 322, a contact 351 is provided for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322. The contact 351 is configured as a double contact.

[0356] exist Fig.40 In the structure, different from Fig.37 In the case of , the contact 352 for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323 is not provided. On the other hand, contacts 381 and 382 for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323 are provided.

[0357] Each of the contacts 381 and 382 is formed by providing a through hole extending through the second semiconductor substrate 322 to the multilayer wiring layer 333 of the third semiconductor substrate 323 and embedding a conductor in the through hole. In particular, each of the contacts 381 and 382 is configured to connect the multilayer wiring layer 332 of the second semiconductor substrate 322 and the multilayer wiring layer 333 of the third semiconductor substrate 323 by providing only one through hole.

[0358] In short, the contacts 381 and 382 are respectively constructed as shared contacts.

[0359] In addition, with the above reference Figure 37 to Figure 39 In the solid-state imaging device 111 of the described configuration, a shared contact can be used for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322 or for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323 .

[0360] In particular, if Fig.40 As shown, the dual contacts 351 and the contacts 381 and 382 can be used for electrical connection between the solid-state imaging element 120 , the memory circuit 121 , and the logic circuit 122 .

[0361] <Fifth Modification of Connection Example of Solid-State Image Sensor>

[0362] exist Fig.41 In the construction of Fig.37 In the case of the first semiconductor substrate 321, the pad hole 350 is formed in the first semiconductor substrate 321 so that the pad hole 350 extends from the back side (light receiving surface side) of the first semiconductor substrate 321 to the pad 341. In addition, the pad 342 is formed in the multilayer wiring layer 331 of the first semiconductor substrate 321.

[0363] In addition, Fig.41 In the construction of Fig.37 In this case, the first semiconductor substrate 321 and the second semiconductor substrate 322 are pasted to each other so that the multilayer wiring layer 332 of the second semiconductor substrate 322 faces the third semiconductor substrate 323 side (the lower side in the figure).

[0364] In addition, Fig.41 In the configuration of , a contact 391 is provided for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322. The contact 391 is configured as a double contact.

[0365] In addition, Fig.41In the structure of the second semiconductor substrate 322, the metal wiring 332a in the multilayer wiring layer 332 and the metal wiring 333a in the multilayer wiring layer 333 of the third semiconductor substrate 323 are directly bonded to each other. In addition, the metal wiring 332b in the multilayer wiring layer 332 and the metal wiring 333b in the multilayer wiring layer 333 are directly bonded to each other. Therefore, the second semiconductor substrate 322 and the third semiconductor substrate 323 are electrically connected to each other.

[0366] In short, Fig.41 In the case of the structure of FIG. 3 , direct bonding is used instead of contacts for electrical connection between the second semiconductor substrate 322 and the third semiconductor substrate 323. Therefore, the manufacturing steps can be simplified and the area on the substrate can be reduced.

[0367] In particular, if Fig.41 As shown, for electrical connection among the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122, a double contact 391 and metal wirings 332a, 333a and 332b, 333b can be used.

[0368] <Modification of the Connection Example of the Solid-State Image Pickup Element of the Sixth Embodiment>

[0369] exist Fig.42 In the structure, different from Fig.41 In the case of the first semiconductor substrate 321 and the second semiconductor substrate 322, contacts 401 and 402 are provided for electrical connection between the first semiconductor substrate 321 and the second semiconductor substrate 322. Fig.42 In the case of the configuration, the lower end of the left side in the figure of the contact 401 is connected to the upper end of the figure of the contact 402 to electrically connect the first semiconductor substrate 321 and the second semiconductor substrate 322 to each other. It should be noted that the contact 401 is configured as a double contact.

[0370] exist Fig.42 In the construction, for example, Fig.43 The formation of the contact 391 does not require the provision of a hole extending from the light receiving surface to the multilayer wiring layer 332. Therefore, the formation of the contact can be performed more simply.

[0371] Fig.42 The other parts of the structure are similar to Fig.41 , so its detailed description is omitted.

[0372] In particular, if Fig.42 As shown, for electrical connection among the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122, double contacts 401 and 402 and metal wirings 332a, 333a and 332b, 333b can be used.

[0373] <<11. Heat dissipation structure>>

[0374] Since the solid-state imaging element 120 with high image quality and high frame rate tends to generate heat, heat dissipation measures are required. Since the solid-state imaging element 120 performs optical sensing, the surface to be sensed absorbs light, so, for example, Fig.43 Side view of Fig.43 As shown in A, a lens 431 is arranged at a stage preceding the solid-state imaging element 120, and an air space 432 exists.

[0375] The heat generated in the solid-state imaging element 120 moves in response to the thermal conductivity of the material. Since the thermal conductivity of air is about 7000 times that of silicon, almost all of the generated heat is not dissipated through the air space 432 but through the material in contact with the solid-state imaging element 120. Therefore, for example, in Fig.43 Side view of Fig.43 In the structure shown in A, the heat generated by the solid-state imaging element 120 moves to the oxide film 133, the logic circuit 122, and the supporting substrate 132 as indicated by arrows and is dissipated.

[0376] like Fig.43 Side view of Fig.43 As shown in FIG. 1A , in order to fill the height for planarization, the logic circuit 122 (or the memory circuit 121 ) is covered with an oxide film 133 around it.

[0377] Since the thickness of the oxide film bonding layer 135 of each substrate is very small, the heat resistance is low. However, the height of the logic circuit 122 (or the memory circuit 121) is large compared to the thickness of the oxide film bonding layer 135, and the thermal conductivity of the oxide film 133 is lower than that of silicon which is the material of the logic circuit 122 (or the memory circuit 121). Therefore, the thermal mobility between the region where the logic circuit 122 (or the memory circuit 121) is connected and another region covered with the oxide film 133 is different.

[0378] Note that Fig.43 Side view of Fig.43 In A, the size of the arrow mark indicates the size of the thermal mobility, and this indicates that as the arrow mark becomes larger, the thermal mobility becomes higher and the heat dissipation efficiency becomes higher. Fig.43 Side view of Fig.43 In A, it is shown that since the thermal conductivity of the logic circuit 122 (or the memory circuit 121) is higher than the thermal conductivity of the oxide film 133, the heat dissipation efficiency of the logic circuit 122 (or the memory circuit 121) is higher.

[0379] Therefore, if Fig.43 Side view of Fig.43As shown in FIG. 1B, a dummy circuit 441 including silicon similar to a member constituting the logic circuit 122 (or the memory circuit 121) may be provided in a region of the oxide film 133 where the logic circuit 122 (or the memory circuit 121) is not formed. Since the thermal conductivity of silicon constituting the dummy circuit 441 is higher than that of the oxide film 133, as indicated by arrows, heat can be dissipated more effectively than when heat is dissipated through the oxide film 133.

[0380] like Fig.43 Side view of Fig.43 As shown in B, in the case of setting a dummy circuit 441, when the WoW technology is applied to manufacturing, as shown in FIG. Fig.44 As shown, among the logic circuits 122 formed on the wafer 104 by the semiconductor process, those logic circuits 122 determined to be good by electrical inspection are re-arranged on the wafer 451 .

[0381] Therefore, on the wafer 451, the dummy circuit 441 is pre-configured around the logic circuit 122 (or the storage circuit 121) on the wafer 451 so as to obtain Fig.43 Side view of Fig.43 This arrangement is shown in A. Then, after the wafer 101 on which the solid-state imaging element 120 is formed by a semiconductor process is positioned and stacked on the wafer 451 , singulation is performed to complete the solid-state imaging device 111 .

[0382] <First Modification of Heat Dissipation Structure>

[0383] Although the foregoing description is directed to an example in which the dummy circuit 441 is arranged instead of the oxide film 133 around the logic circuit 122 or the memory circuit 121 , the dummy circuit 441 may include a dummy wire including a metal having a higher thermal conductivity.

[0384] For example, Fig.45 As shown, the dummy circuit 441 may further include a dummy line 441 a .

[0385] In particular, Fig.45 In this case, since the dummy circuit 441 includes the dummy wire 441 a including a metal having a higher thermal conductivity than silicon, heat can be dissipated with higher efficiency.

[0386] <Second Modification of Heat Dissipation Structure>

[0387] Although the foregoing description is directed to an example in which a dummy circuit 441 including a pseudo wire 441a is provided instead of the oxide film 133 around the logic circuit 122 or the memory circuit 121, a high thermal conductivity material member may be attached to the back side of the support substrate 132 to improve heat dissipation efficiency.

[0388] Fig.46 A configuration example of the solid-state imaging device 111 in which a high thermal conductivity material is pasted to the back side of the supporting substrate 132 is shown.

[0389] In particular, as shown in the side cross-section Fig.46 As shown in FIG. 1A , a high thermal conductivity material member 471 containing a high thermal conductivity material is attached to the back side (lower side in the figure) of the support substrate 132. The high thermal conductivity material member 471 is, for example, SiC, AlN, SIN, Cu, Al, C, or the like.

[0390] In the case where the high thermal conductivity material member 471 is pasted to the back side of the support substrate 132, when the WoW technology is used for manufacturing, such as stereolithography Fig.46 As shown in FIG. 4B , a wafer 481 including a high thermal conductivity material member 471 is stacked below the wafer 201 , and among the logic circuits 122 formed on the wafer 104 by the semiconductor process, those logic circuits 122 that are considered to be good due to electrical inspection are reconfigured on the wafer 201 .

[0391] In particular, in this case, three wafers including wafer 101, wafer 201 and wafer 481 are stacked from the top in the figure, wherein a solid-state imaging element 120 is formed on wafer 101 through a semiconductor process, a good logic circuit 122 is configured on wafer 201, and wafer 481 includes a high thermal conductivity material component 471.

[0392] In addition, if Fig.46 Side view of Fig.46 As shown in FIG. 3C , a high thermal conductivity material member 471 may be formed in a space around the logic circuit 122 and may be embedded in the oxide film 133 .

[0393] <Third Modification of Heat Dissipation Structure>

[0394] Although the foregoing description is directed to an example of pasting the high thermal conductivity material member 471 to the back side of the support substrate 132 to improve heat dissipation efficiency, a water-cooled heat dissipation mechanism can be further provided by providing a water path for circulating cooling water in the high thermal conductivity material member 471 .

[0395] Fig.47 A configuration example of the solid-state imaging device 111 is shown in which a water-cooling type heat dissipation mechanism is formed to further improve heat dissipation efficiency.

[0396] In particular, despite Fig.47 Side view of Fig.47 As shown in A, Fig.47 The solid-state imaging device 111 has the same Fig.46The configuration of the solid-state imaging device 111 described above is a similar basic configuration, but a water path 491 for cooling water is further provided in the high thermal conductivity material member 471 .

[0397] By circulating cooling water in the water path 491 , a water-cooling type heat dissipation mechanism is formed, which enables the heat generated by the solid-state imaging element 120 to be dissipated through the cooling water and to be dissipated more efficiently.

[0398] In the case of a water-cooled heat dissipation mechanism, such as Fig.47 The three-dimensional Fig.47 As shown in FIG. 2B , the wafers 101 and 201 to be stacked are stacked on the wafer 481 in a state where the water channel 491 is formed to be positioned relative to the solid-state imaging element 120 and the logic circuit 122 of the wafers 101 and 201 to be stacked.

[0399] <Fourth Modification of Heat Dissipation Structure>

[0400] Despite Fig.48 The foregoing description is directed to an example in which the region where the gap is formed is filled with the oxide film 133 around the memory circuit 121 and the logic circuit 122, but filling the oxide film 133 requires a lot of time, and thus the process cost increases.

[0401] Therefore, if Fig.48 As shown in the upper right portion of , the gap in the peripheral portion of the memory circuit 121 and the logic circuit 122 may be filled with an organic material member 495 containing an organic material instead of the oxide film 133 to form a heat dissipation structure.

[0402] However, if the peripheral portions of the memory circuit 121 and the logic circuit 122 are filled with the organic material member 495, when the oxide film bonding layer 135 is formed on the uppermost surface, the flatness of the oxide film bonding layer 135 may be damaged by the influence of heat, or warping or swelling may occur due to the difference in the linear expansion coefficient of the embedded material. Therefore, sometimes the support substrate 132 cannot be attached.

[0403] Therefore, if Fig.48 As shown in the lower part of , it is preferable to form a layout in a manner that minimizes the gap based on the shapes of the memory circuit 121, the logic circuit 122, and the dummy circuit 441. By performing the layout in a manner that minimizes the gap, the amount of organic material member 495 used becomes the minimum necessary amount. Therefore, the influence of heat when the oxide film bonding layer 135 is formed on the uppermost surface and the influence of warping or swelling caused by the difference in the linear expansion coefficient of the embedded material can be minimized, and the attachment of the support substrate 132 can be achieved.

[0404] <<12. Application examples of electronic equipment>>

[0405] The above-described imaging element can be applied to various electronic devices, for example, an imaging device such as a digital camera or a digital video camera, a cellular phone having an imaging function, or other devices having an imaging function.

[0406] Fig.49 : is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied.

[0407] Fig.49 An imaging device 501 shown in FIG. 5 includes an optical system 502, a shutter device 503, a solid-state imaging element 504, a drive circuit 505, a signal processing circuit 506, a monitor 507, and a memory 508, and is capable of capturing still images and moving images.

[0408] The optical system 502 includes one or more lenses, and introduces light (incident light) from a subject to the solid-state imaging element 504 so that an image is formed on a light receiving surface of the solid-state imaging element 504 .

[0409] The shutter device 503 is arranged between the optical system 502 and the solid-state imaging element 504 , and under the control of the drive circuit 505 , the shutter device 503 controls a light irradiation period and a light shielding period to the solid-state imaging element 504 .

[0410] The solid-state imaging element 504 includes a package having the solid-state imaging element described above. The solid-state imaging element 504 accumulates signal charge for a period of time in response to light imaged on a light receiving surface of the solid-state imaging element 504 through the optical system 502 and the shutter device 503. The signal charge accumulated in the solid-state imaging element 504 is transmitted according to a drive signal (timing signal) supplied from the drive circuit 505.

[0411] The driving circuit 505 outputs a driving signal for controlling the transfer operation of the solid-state imaging element 504 and the shutter operation of the shutter device 503 to drive the solid-state imaging element 504 and the shutter device 503 , respectively.

[0412] The signal processing circuit 506 performs various signal processing on the signal charge output from the solid-state imaging element 504. The image (image data) obtained by the signal processing performed by the signal processing circuit 506 is supplied to the monitor 507 and displayed on the monitor 507, or is supplied to the memory 508 and stored (recorded) in the memory 508.

[0413] Furthermore, in the imaging apparatus 501 configured in this manner, by applying the solid-state imaging device 111 described above to the optical system 502 and the solid-state imaging element 504 , the yield rate can be improved and the cost required for manufacturing can be reduced.

[0414] <<13. Example of using the imaging element>>

[0415] Fig.50 : is a diagram showing a use example of using the solid-state imaging device 111 described above.

[0416] The above-mentioned imaging element can be used in various cases using visible light, infrared light, ultraviolet light, or X-rays, for example, as described below.

[0417] ・Equipment for taking images for viewing, such as digital cameras and portable devices with camera functions

[0418] Equipment for transportation, such as: automotive sensors that capture the front, rear, surroundings, and interior of a car for safe driving such as automatic parking and recognition of the driver's status; surveillance cameras for monitoring traveling vehicles or roads; and distance sensors that measure the distance between vehicles, etc.

[0419] Devices used in household appliances such as televisions, refrigerators, and air conditioners to capture user gestures and operate the device based on the gestures

[0420] · Equipment for medical or health care purposes, such as endoscopes and equipment for angiography by infrared light reception

[0421] Devices for security purposes, such as surveillance cameras for security applications and cameras for personnel authentication, etc.

[0422] Equipment for beauty care, such as a skin meter for taking images of the skin and a microscope for taking images of the scalp

[0423] Equipment for sports use, such as action cameras and wearable cameras for sports applications

[0424] Equipment for agricultural purposes, such as cameras for monitoring the status of fields and agricultural products

[0425] <<14. Application examples of endoscopic surgery systems>>

[0426] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be applied to an endoscopic surgery system.

[0427] Fig.51 : is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to the embodiment of the present invention (the present technology) can be applied.

[0428] exist Fig.51, a state in which a surgeon (physician) 11131 is performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000 is illustrated. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are installed.

[0429] The endoscope 11100 includes: a barrel 11101 having a region of a predetermined length from its distal end to be inserted into a body cavity of a patient 11132; and a camera 11102 connected to the proximal end of the barrel 11101. In the example shown, the endoscope 11100 shown includes a rigid endoscope having a hard barrel 11101. However, the endoscope 11100 may additionally include a flexible endoscope having a flexible barrel 11101.

[0430] The lens barrel 11101 has an opening at its distal end, in which an objective lens is installed. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through a light guide extending inside the lens barrel 11101, and the light is irradiated toward the observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 may be a forward-looking endoscope, or may be an oblique-looking endoscope or a side-looking endoscope.

[0431] The optical system and the imaging element are arranged inside the camera head 11102 so that the reflected light (observation light) from the observation target is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as RAW data.

[0432] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing on the image signal to display an image based on the image signal, such as development processing (demosaic processing).

[0433] Under the control of the CCU 11201 , the display device 11202 displays thereon an image based on an image signal that has been image-processed by the CCU 11201 .

[0434] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when imaging a surgical area.

[0435] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions to change the imaging conditions of the endoscope 11100 (such as the type of irradiation light, magnification or focal length).

[0436] The treatment tool control device 11205 controls the driving of the energy device 11112 for cauterization or incision of tissue, closure of blood vessels, etc. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity in order to ensure the field of view of the endoscope 11100 and to ensure the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, images, or charts.

[0437] It should be noted that the light source device 11203 that supplies irradiation light to the endoscope 11100 when imaging the surgical area may include a white light source, which includes, for example, an LED, a laser light source, or a combination of the two. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing can be controlled with high precision for various colors (various wavelengths), the light source device 11203 can perform white balance adjustment for the captured image. In addition, in this case, if the laser beams from the corresponding RGB laser light sources are irradiated on the observation target in a time-division manner, and the driving of the imaging element of the camera 11102 is controlled in a manner synchronized with the irradiation timing, images corresponding to the R, G, and B colors, respectively, can also be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0438] In addition, the light source device 11203 can be controlled so that the intensity of the light to be output is changed for each predetermined time. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the light intensity change so as to acquire images in a time-division manner and synthesizing the images, it is possible to create an image with a high dynamic range that has no underexposed shadows and overexposed highlights.

[0439] In addition, the light source device 11203 can be configured to supply light of a predetermined wavelength band prepared for special light observation. In special light observation, for example, by irradiating a narrow band of light compared to the irradiation light (i.e., white light) during ordinary observation using the wavelength dependence of light absorption in human tissue, it is possible to perform narrow-band observation (narrow-band imaging) of predetermined tissues such as blood vessels in the surface part of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image from the fluorescence generated by irradiating excitation light. In fluorescence observation, observation of fluorescence from body tissue can be performed by irradiating excitation light onto body tissue (autofluorescence observation), or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into human tissue and irradiating excitation light corresponding to the fluorescence wavelength of the reagent on the human tissue. The light source device 11203 can be configured to supply such narrow-band light and / or excitation light suitable for special light observation as described above.

[0440] Fig.52 It shows Fig.51 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown in FIG.

[0441] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 to communicate with each other.

[0442] The lens unit 11401 is an optical system, which is provided at a connection position with the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses, including a zoom lens and a focus lens.

[0443] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). In the case where the imaging unit 11402 is constructed as a multi-board type imaging unit, for example, the imaging element generates image signals corresponding to the corresponding R, G and B, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be constructed to have a pair of imaging elements to respectively obtain image signals for the left eye and the right eye prepared for three-dimensional (3D) display. If a 3D display is performed, the surgeon 11131 can more accurately understand the depth of the biological tissue in the surgical area. It should be noted that in the case where the imaging unit 11402 is constructed as a stereoscopic type imaging unit, a system of multiple lens units 11401 is set corresponding to each imaging element.

[0444] In addition, the camera unit 11402 does not need to be arranged on the camera head. For example, the camera unit 11402 can be arranged inside the lens barrel 11101 just behind the objective lens.

[0445] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the camera unit 11402 can be appropriately adjusted.

[0446] The communication unit 11404 includes a communication device that transmits and receives various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0447] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, such as information specifying a frame rate for capturing an image, information specifying an exposure value when capturing an image, and / or information specifying a magnification and a focus for capturing an image.

[0448] It should be noted that imaging conditions such as frame rate, exposure value, magnification or focus may be specified by the user, or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 is equipped with an automatic exposure (AE: Auto Exposure) function, an automatic focus (AF: Auto Focus) function, and an automatic white balance (AWB: Auto White Balance) function.

[0449] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0450] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 through the transmission cable 11400.

[0451] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0452] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data transmitted from the camera 11102 .

[0453] The control unit 11413 performs various controls related to imaging the operation area, etc. through the endoscope 11100 and displaying the captured image obtained by imaging the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0454] In addition, the control unit 11413 controls the display device 11202 based on the image signal that has been image-processed by the image processing unit 11412 to display a captured image in which the surgical area, etc., is captured. Thus, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological body areas, bleeding, and mist when the energy device 11112 is used, etc., by detecting the shape and color of the edge of the object included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical support information in a manner overlapping with the image of the surgical area. In the case where the surgical support information is displayed in an overlapping manner and provided to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the operation with certainty.

[0455] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electrical signal cable prepared for communication of electrical signals, an optical fiber prepared for optical communication, or a composite cable prepared for both electrical communication and optical communication.

[0456] Here, although in the illustrated example, communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0457] An example of an endoscopic surgical system to which the technology according to the present invention can be applied has been described. The technology according to the present invention can be applied to the endoscope 11100 and the camera 11102 (the camera unit 11402) among the components described above. In particular, the solid-state imaging device 111 of the present invention can be applied to the camera unit 11402. By applying the technology of the present invention to the endoscope 11100 or the camera 11102 (the camera unit 11402), etc., the yield rate can be improved and the cost required for manufacturing can be reduced.

[0458] It should be noted that although the description has been made by taking an endoscopic surgery system as an example, the technology according to the present invention can also be applied to, for example, a microsurgery system and the like.

[0459] <<15. Application examples of mobile objects>>

[0460] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device mounted on any type of mobile body, such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0461] Fig.53 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present invention can be applied.

[0462] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.53 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0463] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device for generating a vehicle drive force, such as an internal combustion engine or a drive motor, etc.; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a vehicle braking force, etc.

[0464] The body system control unit 12020 controls the operation of various devices provided to the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, a radio wave transmitted from a mobile device that replaces the key or a signal of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, a power window device, or a light, etc. of the vehicle.

[0465] The vehicle exterior information detection unit 12030 detects external information of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform a process of detecting objects such as people, vehicles, obstacles, signs, or text on the road surface, or perform a process of detecting the distance to the above-mentioned objects.

[0466] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about distance measurement. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0467] The in-vehicle information detection unit 12040 detects the interior information of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 for detecting the state of the driver. The driver state detection unit 12041 includes, for example, a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0468] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and the microcomputer 12051 outputs the control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing the functions of the Advanced Driver Assistance System (ADAS), which includes collision avoidance or impact mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning or vehicle lane departure warning, etc.

[0469] In addition, based on the information inside and outside the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, the microcomputer 12051 can perform collaborative control such as automatic driving aimed at enabling the vehicle to drive autonomously without relying on the driver's operation by controlling the driving force generating device, steering mechanism or braking device, etc.

[0470] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the external information of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam.

[0471] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify the occupants of the vehicle or the outside of the vehicle of the information in a visual or auditory manner. Fig.53 In the example of FIG. 1 , an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0472] Fig.54 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0473] exist Fig.54 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0474] Camera units 12101, 12102, 12103, 12104 and 12105 are, for example, arranged at the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at the upper part of the windshield in the vehicle. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the side mirrors mainly obtain images from the side of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains images from the rear of the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle is mainly used to detect the preceding vehicle, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0475] By the way, Fig.54 An example of the photographing range of the camera units 12101 to 12104 is shown. The photographing range 12111 indicates the photographing range of the camera unit 12101 provided to the front nose. The photographing ranges 12112 and 12113 respectively indicate the photographing ranges of the camera units 12102 and 12103 provided to the side mirrors. The photographing range 12114 indicates the photographing range of the camera unit 12104 provided to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above can be obtained by superimposing the image data photographed by the camera units 12101 to 12104.

[0476] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0477] For example, the microcomputer 12051 can determine the distances to the three-dimensional objects within the imaging ranges 12111 to 12114 and the time changes of the distances (relative speed to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the preceding vehicle: the three-dimensional object is particularly present on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control such as automatic driving that is intended to make the vehicle autonomously travel without relying on the operation of the driver can be performed.

[0478] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles and other three-dimensional objects based on the distance information obtained from the camera units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines a collision risk for indicating the danger of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 is thus able to assist driving to avoid collisions.

[0479] At least one of the camera units 12101 to 12104 may be an infrared camera for detecting infrared rays. The microcomputer 12051 is capable of identifying pedestrians, for example, by determining whether there are pedestrians in the captured images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following process: a process of extracting feature points in the captured images of the camera units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by pattern matching a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there are pedestrians in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 so that the rectangular contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon representing a pedestrian, etc. is displayed at a desired position.

[0480] An example of a vehicle control system to which the technology according to the present invention can be applied has been described. The technology according to the present invention can be applied to, for example, the camera unit 12031 among the above-mentioned components. In particular, the solid-state imaging device 111 of the present invention can be applied to the camera unit 12031. By applying the technology according to the present invention to the camera unit 12031, the yield rate can be improved and the cost required for manufacturing can be reduced.

[0481] The technology according to the present invention can be applied to such a solid-state imaging device as described above.

[0482] It is to be noted that the present invention can have such a configuration as described below.

[0483] <1> A back-illuminated solid-state imaging device comprising:

[0484] a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels;

[0485] a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedding member; and

[0486] wiring that electrically connects the first semiconductor element and the second semiconductor element,

[0487] The first semiconductor element and the second semiconductor element are stacked by being bonded through an oxide film.

[0488] <2> according to <1> The back-illuminated solid-state imaging device, wherein

[0489] The first semiconductor element is larger than the second semiconductor element.

[0490] <3> according to <1> The back-illuminated solid-state imaging device, wherein

[0491] The first semiconductor element is smaller than the second semiconductor element.

[0492] <4> according to <1> to <3> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0493] The signal processing circuit includes a first signal processing circuit and a second signal processing circuit, and

[0494] In the second semiconductor element, the first signal processing circuit and the second signal processing circuit are arranged in parallel in the horizontal direction and embedded by the embedding member.

[0495] <5> according to <1> to <4> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0496] The signal processing circuit includes a first signal processing circuit and a second signal processing circuit,

[0497] The wiring includes a first wiring and a second wiring,

[0498] In the second semiconductor element, the first signal processing circuit is embedded by the embedding member,

[0499] The solid-state imaging device includes a third semiconductor element in which the second signal processing circuit is embedded by the embedding member.

[0500] The first wiring electrically connects the first semiconductor element and the second semiconductor element to each other,

[0501] The second wiring electrically connects the second semiconductor element and the third semiconductor element to each other, and

[0502] The second semiconductor element and the third semiconductor element are stacked by being bonded via an oxide film.

[0503] <6> according to <1> to <5> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0504] The wirings are bonded by CuCu bonding.

[0505] <7> according to <1> to <5> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0506] The wirings are electrically connected via through-holes.

[0507] <8> according to <7> The back-illuminated solid-state imaging device, wherein

[0508] The wiring is electrically connected via a through hole formed from the imaging surface side of the imaging element.

[0509] <9> according to <7> The back-illuminated solid-state imaging device, wherein

[0510] The wiring is electrically connected via a through hole formed from a surface on the opposite side to the imaging surface of the imaging element.

[0511] <10> according to <1> to <9> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0512] The embedded member includes an oxide film.

[0513] <11> according to <1> to <9> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0514] The embedded member includes an organic material.

[0515] <12> according to <11> The back-illuminated solid-state imaging device, wherein

[0516] In the second semiconductor element, the signal processing circuits are laid out in such a manner that a gap between the signal processing circuits is minimized, and the signal processing circuits are embedded by the embedding member including the organic material.

[0517] <13> according to <1> to <12> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0518] In the second semiconductor element, in addition to the signal processing circuit, a dummy circuit is embedded by the embedding member, the dummy circuit being constituted by a semiconductor element and including a dummy line.

[0519] <14> according to <1> to <13> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0520] On a surface of the second semiconductor element opposite to a surface on which the first semiconductor element is stacked, a heat dissipation member including a member having a thermal conductivity higher than a predetermined thermal conductivity and used to dissipate heat is stacked.

[0521] <15> according to <14> The back-illuminated solid-state imaging device, wherein

[0522] The heat dissipation member includes SiC, AlN, SIN, Cu, Al or C.

[0523] <16> according to <14> The back-illuminated solid-state imaging device, wherein

[0524] The heat dissipating member includes a water path for circulating cooling water.

[0525] <17> according to <1> to <16> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0526] The signal processing circuit includes a logic circuit, a storage circuit, a power supply circuit, an image signal compression circuit, a clock circuit and an optical communication conversion circuit.

[0527] <18> according to <1> to <17> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0528] The signal processing circuit is embedded in the first semiconductor element via the embedding member.

[0529] <19> according to <18> The back-illuminated solid-state imaging device, wherein

[0530] After the signal processing circuit is brought into contact with the first semiconductor element in a positioned state at a portion thereof and is gradually joined to the first semiconductor element from a peripheral portion of the contact portion, the signal processing circuit is respectively embedded by the embedding member.

[0531] <20> according to <19> The back-illuminated solid-state imaging device, wherein

[0532] The portion thereof includes edge edges and endpoints of the signal processing circuit.

[0533] <21> according to <19> The back-illuminated solid-state imaging device, wherein

[0534] The signal processing circuit is smaller than the first semiconductor element.

[0535] <22> according to <1> to <17> The back-illuminated solid-state imaging device according to any one of the preceding claims,

[0536] After the signal processing circuit is brought into contact with the second semiconductor element in a positioned state at a portion thereof and is gradually joined to the second semiconductor element from a peripheral portion of the contact portion, the signal processing circuit is respectively embedded by the embedding member.

[0537] <23> according to <22> The back-illuminated solid-state imaging device, wherein

[0538] The portion thereof includes edge edges and endpoints of the signal processing circuit.

[0539] <24> A method for manufacturing a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising:

[0540] a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels;

[0541] a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedding member; and

[0542] wiring that electrically connects the first semiconductor element and the second semiconductor element,

[0543] The first semiconductor element and the second semiconductor element are stacked by bonding through an oxide film, wherein

[0544] The first wafer and the second wafer are stacked by oxide film bonding in such a manner that the wiring between the first semiconductor element and the second semiconductor element is electrically connected, and then singulated,

[0545] The first wafer includes the imaging element formed by a semiconductor process, and

[0546] The signal processing circuits formed by the semiconductor process and confirmed as good products by the electrical inspection are arranged in the second wafer, and the signal processing circuits are embedded by the embedding member.

[0547] <25> An imaging device, comprising a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising:

[0548] a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels;

[0549] a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedding member; and

[0550] wiring that electrically connects the first semiconductor element and the second semiconductor element,

[0551] The first semiconductor element and the second semiconductor element are stacked by being bonded through an oxide film.

[0552] <26> An electronic device, comprising a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising:

[0553] a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels;

[0554] a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedding member; and

[0555] wiring that electrically connects the first semiconductor element and the second semiconductor element,

[0556] The first semiconductor element and the second semiconductor element are stacked by being bonded through an oxide film.

[0557] Reference numerals list

[0558] 101 to 104 wafers

[0559] 111 Solid-state imaging device

[0560] 120 Solid-state imaging element

[0561] 120a terminal

[0562] 121 Storage Circuit

[0563] 121a, 121a-1, 121a-2 terminals

[0564] 122 Logic Circuits

[0565] 122a terminal

[0566] 131 On-chip lenses and on-chip color filters

[0567] 132 Support substrate

[0568] 133 Oxide film

[0569] 134, 134-1, 134-2, 134A to 134H wiring

[0570] 135 Oxide film bonding layer

[0571] 151 Reconfiguration of the substrate

[0572] 152 Adhesive

[0573] 161, 171 support substrate

[0574] 321 first semiconductor substrate

[0575] 322 second semiconductor substrate

[0576] 323 Third semiconductor substrate

[0577] 331 to 333 multi-layer wiring layer

[0578] 351, 352, 361, 362, 372, 381, 382, ​​391, 401, 402 contacts

[0579] 441 Dummy Circuit

[0580] 441a Pseudowire

[0581] 471 High thermal conductivity material components

[0582] 491 waterway

[0583] 495 Organic material components

Claims

1. A back-illuminated solid-state imaging device, comprising: a first semiconductor element including an imaging element configured to generate a pixel signal in units of pixels; a second semiconductor element in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedding member; as well as wiring that electrically connects the first semiconductor element and the second semiconductor element, The first semiconductor element and the second semiconductor element are stacked by being bonded through an oxide film.

2. The back-illuminated solid-state imaging device according to claim 1, wherein The first semiconductor element is larger than the second semiconductor element.

3. The back-illuminated solid-state imaging device according to claim 1, wherein The first semiconductor element is smaller than the second semiconductor element.

4. The back-illuminated solid-state imaging device according to claim 1, wherein The signal processing circuit includes a first signal processing circuit and a second signal processing circuit, and In the second semiconductor element, the first signal processing circuit and the second signal processing circuit are arranged in parallel in the horizontal direction and embedded by the embedding member.

5. The back-illuminated solid-state imaging device according to claim 1, wherein The signal processing circuit includes a first signal processing circuit and a second signal processing circuit, The wiring includes a first wiring and a second wiring, In the second semiconductor element, the first signal processing circuit is embedded by the embedding member, The solid-state imaging device includes a third semiconductor element in which the second signal processing circuit is embedded by the embedding member. The first wiring electrically connects the first semiconductor element and the second semiconductor element to each other, The second wiring electrically connects the second semiconductor element and the third semiconductor element to each other, and The second semiconductor element and the third semiconductor element are stacked by being bonded via an oxide film.

6. The back-illuminated solid-state imaging device according to claim 1, wherein The wirings are bonded by CuCu bonding.

7. The back-illuminated solid-state imaging device according to claim 1, wherein The wirings are electrically connected via through-holes.

8. A method for manufacturing a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device being the back-illuminated solid-state imaging device according to any one of claims 1 to 7, wherein The first wafer and the second wafer are stacked by oxide film bonding in such a manner that the wiring between the first semiconductor element and the second semiconductor element is electrically connected, and then singulated, The first wafer includes the imaging element formed by a semiconductor process, and The signal processing circuits formed by the semiconductor process and confirmed as good products by the electrical inspection are arranged in the second wafer, and the signal processing circuits are embedded by the embedding member. 9 . An imaging apparatus comprising the back-illuminated solid-state imaging device according to claim 1 . 10 . An electronic device comprising the back-illuminated solid-state imaging device according to claim 1 .

Images